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1/*
2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
3 *
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/segment.h>
16#include <asm/pgtable.h>
17#include <asm/page.h>
18#include <asm/msr.h>
19#include <asm/cache.h>
20#include <asm/processor-flags.h>
21#include <asm/percpu.h>
22
23#ifdef CONFIG_PARAVIRT
24#include <asm/asm-offsets.h>
25#include <asm/paravirt.h>
26#else
27#define GET_CR2_INTO_RCX movq %cr2, %rcx
28#endif
29
30/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
31 * because we need identity-mapped pages.
32 *
33 */
34
35#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
36
37L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
38L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
39L4_START_KERNEL = pgd_index(__START_KERNEL_map)
40L3_START_KERNEL = pud_index(__START_KERNEL_map)
41
42 .text
43 __HEAD
44 .code64
45 .globl startup_64
46startup_64:
47
48 /*
49 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
50 * and someone has loaded an identity mapped page table
51 * for us. These identity mapped page tables map all of the
52 * kernel pages and possibly all of memory.
53 *
54 * %esi holds a physical pointer to real_mode_data.
55 *
56 * We come here either directly from a 64bit bootloader, or from
57 * arch/x86_64/boot/compressed/head.S.
58 *
59 * We only come here initially at boot nothing else comes here.
60 *
61 * Since we may be loaded at an address different from what we were
62 * compiled to run at we first fixup the physical addresses in our page
63 * tables and then reload them.
64 */
65
66 /* Compute the delta between the address I am compiled to run at and the
67 * address I am actually running at.
68 */
69 leaq _text(%rip), %rbp
70 subq $_text - __START_KERNEL_map, %rbp
71
72 /* Is the address not 2M aligned? */
73 movq %rbp, %rax
74 andl $~PMD_PAGE_MASK, %eax
75 testl %eax, %eax
76 jnz bad_address
77
78 /* Is the address too large? */
79 leaq _text(%rip), %rdx
80 movq $PGDIR_SIZE, %rax
81 cmpq %rax, %rdx
82 jae bad_address
83
84 /* Fixup the physical addresses in the page table
85 */
86 addq %rbp, init_level4_pgt + 0(%rip)
87 addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
88 addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
89
90 addq %rbp, level3_ident_pgt + 0(%rip)
91
92 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
93 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
94
95 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
96
97 /* Add an Identity mapping if I am above 1G */
98 leaq _text(%rip), %rdi
99 andq $PMD_PAGE_MASK, %rdi
100
101 movq %rdi, %rax
102 shrq $PUD_SHIFT, %rax
103 andq $(PTRS_PER_PUD - 1), %rax
104 jz ident_complete
105
106 leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
107 leaq level3_ident_pgt(%rip), %rbx
108 movq %rdx, 0(%rbx, %rax, 8)
109
110 movq %rdi, %rax
111 shrq $PMD_SHIFT, %rax
112 andq $(PTRS_PER_PMD - 1), %rax
113 leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
114 leaq level2_spare_pgt(%rip), %rbx
115 movq %rdx, 0(%rbx, %rax, 8)
116ident_complete:
117
118 /*
119 * Fixup the kernel text+data virtual addresses. Note that
120 * we might write invalid pmds, when the kernel is relocated
121 * cleanup_highmap() fixes this up along with the mappings
122 * beyond _end.
123 */
124
125 leaq level2_kernel_pgt(%rip), %rdi
126 leaq 4096(%rdi), %r8
127 /* See if it is a valid page table entry */
1281: testq $1, 0(%rdi)
129 jz 2f
130 addq %rbp, 0(%rdi)
131 /* Go to the next page */
1322: addq $8, %rdi
133 cmp %r8, %rdi
134 jne 1b
135
136 /* Fixup phys_base */
137 addq %rbp, phys_base(%rip)
138
139 /* Fixup trampoline */
140 addq %rbp, trampoline_level4_pgt + 0(%rip)
141 addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
142
143 /* Due to ENTRY(), sometimes the empty space gets filled with
144 * zeros. Better take a jmp than relying on empty space being
145 * filled with 0x90 (nop)
146 */
147 jmp secondary_startup_64
148ENTRY(secondary_startup_64)
149 /*
150 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
151 * and someone has loaded a mapped page table.
152 *
153 * %esi holds a physical pointer to real_mode_data.
154 *
155 * We come here either from startup_64 (using physical addresses)
156 * or from trampoline.S (using virtual addresses).
157 *
158 * Using virtual addresses from trampoline.S removes the need
159 * to have any identity mapped pages in the kernel page table
160 * after the boot processor executes this code.
161 */
162
163 /* Enable PAE mode and PGE */
164 movl $(X86_CR4_PAE | X86_CR4_PGE), %eax
165 movq %rax, %cr4
166
167 /* Setup early boot stage 4 level pagetables. */
168 movq $(init_level4_pgt - __START_KERNEL_map), %rax
169 addq phys_base(%rip), %rax
170 movq %rax, %cr3
171
172 /* Ensure I am executing from virtual addresses */
173 movq $1f, %rax
174 jmp *%rax
1751:
176
177 /* Check if nx is implemented */
178 movl $0x80000001, %eax
179 cpuid
180 movl %edx,%edi
181
182 /* Setup EFER (Extended Feature Enable Register) */
183 movl $MSR_EFER, %ecx
184 rdmsr
185 btsl $_EFER_SCE, %eax /* Enable System Call */
186 btl $20,%edi /* No Execute supported? */
187 jnc 1f
188 btsl $_EFER_NX, %eax
1891: wrmsr /* Make changes effective */
190
191 /* Setup cr0 */
192#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
193 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
194 X86_CR0_PG)
195 movl $CR0_STATE, %eax
196 /* Make changes effective */
197 movq %rax, %cr0
198
199 /* Setup a boot time stack */
200 movq stack_start(%rip),%rsp
201
202 /* zero EFLAGS after setting rsp */
203 pushq $0
204 popfq
205
206 /*
207 * We must switch to a new descriptor in kernel space for the GDT
208 * because soon the kernel won't have access anymore to the userspace
209 * addresses where we're currently running on. We have to do that here
210 * because in 32bit we couldn't load a 64bit linear address.
211 */
212 lgdt early_gdt_descr(%rip)
213
214 /* set up data segments */
215 xorl %eax,%eax
216 movl %eax,%ds
217 movl %eax,%ss
218 movl %eax,%es
219
220 /*
221 * We don't really need to load %fs or %gs, but load them anyway
222 * to kill any stale realmode selectors. This allows execution
223 * under VT hardware.
224 */
225 movl %eax,%fs
226 movl %eax,%gs
227
228 /* Set up %gs.
229 *
230 * The base of %gs always points to the bottom of the irqstack
231 * union. If the stack protector canary is enabled, it is
232 * located at %gs:40. Note that, on SMP, the boot cpu uses
233 * init data section till per cpu areas are set up.
234 */
235 movl $MSR_GS_BASE,%ecx
236 movl initial_gs(%rip),%eax
237 movl initial_gs+4(%rip),%edx
238 wrmsr
239
240 /* esi is pointer to real mode structure with interesting info.
241 pass it to C */
242 movl %esi, %edi
243
244 /* Finally jump to run C code and to be on real kernel address
245 * Since we are running on identity-mapped space we have to jump
246 * to the full 64bit address, this is only possible as indirect
247 * jump. In addition we need to ensure %cs is set so we make this
248 * a far return.
249 */
250 movq initial_code(%rip),%rax
251 pushq $0 # fake return address to stop unwinder
252 pushq $__KERNEL_CS # set correct cs
253 pushq %rax # target address in negative space
254 lretq
255
256 /* SMP bootup changes these two */
257 __REFDATA
258 .align 8
259 ENTRY(initial_code)
260 .quad x86_64_start_kernel
261 ENTRY(initial_gs)
262 .quad INIT_PER_CPU_VAR(irq_stack_union)
263
264 ENTRY(stack_start)
265 .quad init_thread_union+THREAD_SIZE-8
266 .word 0
267 __FINITDATA
268
269bad_address:
270 jmp bad_address
271
272 .section ".init.text","ax"
273#ifdef CONFIG_EARLY_PRINTK
274 .globl early_idt_handlers
275early_idt_handlers:
276 i = 0
277 .rept NUM_EXCEPTION_VECTORS
278 movl $i, %esi
279 jmp early_idt_handler
280 i = i + 1
281 .endr
282#endif
283
284ENTRY(early_idt_handler)
285#ifdef CONFIG_EARLY_PRINTK
286 cmpl $2,early_recursion_flag(%rip)
287 jz 1f
288 incl early_recursion_flag(%rip)
289 GET_CR2_INTO_RCX
290 movq %rcx,%r9
291 xorl %r8d,%r8d # zero for error code
292 movl %esi,%ecx # get vector number
293 # Test %ecx against mask of vectors that push error code.
294 cmpl $31,%ecx
295 ja 0f
296 movl $1,%eax
297 salq %cl,%rax
298 testl $0x27d00,%eax
299 je 0f
300 popq %r8 # get error code
3010: movq 0(%rsp),%rcx # get ip
302 movq 8(%rsp),%rdx # get cs
303 xorl %eax,%eax
304 leaq early_idt_msg(%rip),%rdi
305 call early_printk
306 cmpl $2,early_recursion_flag(%rip)
307 jz 1f
308 call dump_stack
309#ifdef CONFIG_KALLSYMS
310 leaq early_idt_ripmsg(%rip),%rdi
311 movq 0(%rsp),%rsi # get rip again
312 call __print_symbol
313#endif
314#endif /* EARLY_PRINTK */
3151: hlt
316 jmp 1b
317
318#ifdef CONFIG_EARLY_PRINTK
319early_recursion_flag:
320 .long 0
321
322early_idt_msg:
323 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
324early_idt_ripmsg:
325 .asciz "RIP %s\n"
326#endif /* CONFIG_EARLY_PRINTK */
327 .previous
328
329#define NEXT_PAGE(name) \
330 .balign PAGE_SIZE; \
331ENTRY(name)
332
333/* Automate the creation of 1 to 1 mapping pmd entries */
334#define PMDS(START, PERM, COUNT) \
335 i = 0 ; \
336 .rept (COUNT) ; \
337 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
338 i = i + 1 ; \
339 .endr
340
341 .data
342 /*
343 * This default setting generates an ident mapping at address 0x100000
344 * and a mapping for the kernel that precisely maps virtual address
345 * 0xffffffff80000000 to physical address 0x000000. (always using
346 * 2Mbyte large pages provided by PAE mode)
347 */
348NEXT_PAGE(init_level4_pgt)
349 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
350 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
351 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
352 .org init_level4_pgt + L4_START_KERNEL*8, 0
353 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
354 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
355
356NEXT_PAGE(level3_ident_pgt)
357 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
358 .fill 511,8,0
359
360NEXT_PAGE(level3_kernel_pgt)
361 .fill L3_START_KERNEL,8,0
362 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
363 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
364 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
365
366NEXT_PAGE(level2_fixmap_pgt)
367 .fill 506,8,0
368 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
369 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
370 .fill 5,8,0
371
372NEXT_PAGE(level1_fixmap_pgt)
373 .fill 512,8,0
374
375NEXT_PAGE(level2_ident_pgt)
376 /* Since I easily can, map the first 1G.
377 * Don't set NX because code runs from these pages.
378 */
379 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
380
381NEXT_PAGE(level2_kernel_pgt)
382 /*
383 * 512 MB kernel mapping. We spend a full page on this pagetable
384 * anyway.
385 *
386 * The kernel code+data+bss must not be bigger than that.
387 *
388 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
389 * If you want to increase this then increase MODULES_VADDR
390 * too.)
391 */
392 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
393 KERNEL_IMAGE_SIZE/PMD_SIZE)
394
395NEXT_PAGE(level2_spare_pgt)
396 .fill 512, 8, 0
397
398#undef PMDS
399#undef NEXT_PAGE
400
401 .data
402 .align 16
403 .globl early_gdt_descr
404early_gdt_descr:
405 .word GDT_ENTRIES*8-1
406early_gdt_descr_base:
407 .quad INIT_PER_CPU_VAR(gdt_page)
408
409ENTRY(phys_base)
410 /* This must match the first entry in level2_kernel_pgt */
411 .quad 0x0000000000000000
412
413#include "../../x86/xen/xen-head.S"
414
415 .section .bss, "aw", @nobits
416 .align L1_CACHE_BYTES
417ENTRY(idt_table)
418 .skip IDT_ENTRIES * 16
419
420 __PAGE_ALIGNED_BSS
421 .align PAGE_SIZE
422ENTRY(empty_zero_page)
423 .skip PAGE_SIZE
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <asm/segment.h>
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27
28#ifdef CONFIG_PARAVIRT
29#include <asm/asm-offsets.h>
30#include <asm/paravirt.h>
31#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
32#else
33#define GET_CR2_INTO(reg) movq %cr2, reg
34#define INTERRUPT_RETURN iretq
35#endif
36
37/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
38 * because we need identity-mapped pages.
39 *
40 */
41
42#define l4_index(x) (((x) >> 39) & 511)
43#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
44
45L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
46L4_START_KERNEL = l4_index(__START_KERNEL_map)
47
48L3_START_KERNEL = pud_index(__START_KERNEL_map)
49
50 .text
51 __HEAD
52 .code64
53 .globl startup_64
54startup_64:
55 UNWIND_HINT_EMPTY
56 /*
57 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
58 * and someone has loaded an identity mapped page table
59 * for us. These identity mapped page tables map all of the
60 * kernel pages and possibly all of memory.
61 *
62 * %rsi holds a physical pointer to real_mode_data.
63 *
64 * We come here either directly from a 64bit bootloader, or from
65 * arch/x86/boot/compressed/head_64.S.
66 *
67 * We only come here initially at boot nothing else comes here.
68 *
69 * Since we may be loaded at an address different from what we were
70 * compiled to run at we first fixup the physical addresses in our page
71 * tables and then reload them.
72 */
73
74 /* Set up the stack for verify_cpu(), similar to initial_stack below */
75 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
76
77 /* Sanitize CPU configuration */
78 call verify_cpu
79
80 /*
81 * Perform pagetable fixups. Additionally, if SME is active, encrypt
82 * the kernel and retrieve the modifier (SME encryption mask if SME
83 * is active) to be added to the initial pgdir entry that will be
84 * programmed into CR3.
85 */
86 leaq _text(%rip), %rdi
87 pushq %rsi
88 call __startup_64
89 popq %rsi
90
91 /* Form the CR3 value being sure to include the CR3 modifier */
92 addq $(early_top_pgt - __START_KERNEL_map), %rax
93 jmp 1f
94ENTRY(secondary_startup_64)
95 UNWIND_HINT_EMPTY
96 /*
97 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
98 * and someone has loaded a mapped page table.
99 *
100 * %rsi holds a physical pointer to real_mode_data.
101 *
102 * We come here either from startup_64 (using physical addresses)
103 * or from trampoline.S (using virtual addresses).
104 *
105 * Using virtual addresses from trampoline.S removes the need
106 * to have any identity mapped pages in the kernel page table
107 * after the boot processor executes this code.
108 */
109
110 /* Sanitize CPU configuration */
111 call verify_cpu
112
113 /*
114 * Retrieve the modifier (SME encryption mask if SME is active) to be
115 * added to the initial pgdir entry that will be programmed into CR3.
116 */
117 pushq %rsi
118 call __startup_secondary_64
119 popq %rsi
120
121 /* Form the CR3 value being sure to include the CR3 modifier */
122 addq $(init_top_pgt - __START_KERNEL_map), %rax
1231:
124
125 /* Enable PAE mode, PGE and LA57 */
126 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
127#ifdef CONFIG_X86_5LEVEL
128 testl $1, __pgtable_l5_enabled(%rip)
129 jz 1f
130 orl $X86_CR4_LA57, %ecx
1311:
132#endif
133 movq %rcx, %cr4
134
135 /* Setup early boot stage 4-/5-level pagetables. */
136 addq phys_base(%rip), %rax
137 movq %rax, %cr3
138
139 /* Ensure I am executing from virtual addresses */
140 movq $1f, %rax
141 ANNOTATE_RETPOLINE_SAFE
142 jmp *%rax
1431:
144 UNWIND_HINT_EMPTY
145
146 /* Check if nx is implemented */
147 movl $0x80000001, %eax
148 cpuid
149 movl %edx,%edi
150
151 /* Setup EFER (Extended Feature Enable Register) */
152 movl $MSR_EFER, %ecx
153 rdmsr
154 btsl $_EFER_SCE, %eax /* Enable System Call */
155 btl $20,%edi /* No Execute supported? */
156 jnc 1f
157 btsl $_EFER_NX, %eax
158 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1591: wrmsr /* Make changes effective */
160
161 /* Setup cr0 */
162 movl $CR0_STATE, %eax
163 /* Make changes effective */
164 movq %rax, %cr0
165
166 /* Setup a boot time stack */
167 movq initial_stack(%rip), %rsp
168
169 /* zero EFLAGS after setting rsp */
170 pushq $0
171 popfq
172
173 /*
174 * We must switch to a new descriptor in kernel space for the GDT
175 * because soon the kernel won't have access anymore to the userspace
176 * addresses where we're currently running on. We have to do that here
177 * because in 32bit we couldn't load a 64bit linear address.
178 */
179 lgdt early_gdt_descr(%rip)
180
181 /* set up data segments */
182 xorl %eax,%eax
183 movl %eax,%ds
184 movl %eax,%ss
185 movl %eax,%es
186
187 /*
188 * We don't really need to load %fs or %gs, but load them anyway
189 * to kill any stale realmode selectors. This allows execution
190 * under VT hardware.
191 */
192 movl %eax,%fs
193 movl %eax,%gs
194
195 /* Set up %gs.
196 *
197 * The base of %gs always points to the bottom of the irqstack
198 * union. If the stack protector canary is enabled, it is
199 * located at %gs:40. Note that, on SMP, the boot cpu uses
200 * init data section till per cpu areas are set up.
201 */
202 movl $MSR_GS_BASE,%ecx
203 movl initial_gs(%rip),%eax
204 movl initial_gs+4(%rip),%edx
205 wrmsr
206
207 /* rsi is pointer to real mode structure with interesting info.
208 pass it to C */
209 movq %rsi, %rdi
210
211.Ljump_to_C_code:
212 /*
213 * Jump to run C code and to be on a real kernel address.
214 * Since we are running on identity-mapped space we have to jump
215 * to the full 64bit address, this is only possible as indirect
216 * jump. In addition we need to ensure %cs is set so we make this
217 * a far return.
218 *
219 * Note: do not change to far jump indirect with 64bit offset.
220 *
221 * AMD does not support far jump indirect with 64bit offset.
222 * AMD64 Architecture Programmer's Manual, Volume 3: states only
223 * JMP FAR mem16:16 FF /5 Far jump indirect,
224 * with the target specified by a far pointer in memory.
225 * JMP FAR mem16:32 FF /5 Far jump indirect,
226 * with the target specified by a far pointer in memory.
227 *
228 * Intel64 does support 64bit offset.
229 * Software Developer Manual Vol 2: states:
230 * FF /5 JMP m16:16 Jump far, absolute indirect,
231 * address given in m16:16
232 * FF /5 JMP m16:32 Jump far, absolute indirect,
233 * address given in m16:32.
234 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
235 * address given in m16:64.
236 */
237 pushq $.Lafter_lret # put return address on stack for unwinder
238 xorq %rbp, %rbp # clear frame pointer
239 movq initial_code(%rip), %rax
240 pushq $__KERNEL_CS # set correct cs
241 pushq %rax # target address in negative space
242 lretq
243.Lafter_lret:
244END(secondary_startup_64)
245
246#include "verify_cpu.S"
247
248#ifdef CONFIG_HOTPLUG_CPU
249/*
250 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
251 * up already except stack. We just set up stack here. Then call
252 * start_secondary() via .Ljump_to_C_code.
253 */
254ENTRY(start_cpu0)
255 movq initial_stack(%rip), %rsp
256 UNWIND_HINT_EMPTY
257 jmp .Ljump_to_C_code
258ENDPROC(start_cpu0)
259#endif
260
261 /* Both SMP bootup and ACPI suspend change these variables */
262 __REFDATA
263 .balign 8
264 GLOBAL(initial_code)
265 .quad x86_64_start_kernel
266 GLOBAL(initial_gs)
267 .quad INIT_PER_CPU_VAR(irq_stack_union)
268 GLOBAL(initial_stack)
269 /*
270 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel
271 * unwinder reliably detect the end of the stack.
272 */
273 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
274 __FINITDATA
275
276 __INIT
277ENTRY(early_idt_handler_array)
278 i = 0
279 .rept NUM_EXCEPTION_VECTORS
280 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
281 UNWIND_HINT_IRET_REGS
282 pushq $0 # Dummy error code, to make stack frame uniform
283 .else
284 UNWIND_HINT_IRET_REGS offset=8
285 .endif
286 pushq $i # 72(%rsp) Vector number
287 jmp early_idt_handler_common
288 UNWIND_HINT_IRET_REGS
289 i = i + 1
290 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
291 .endr
292 UNWIND_HINT_IRET_REGS offset=16
293END(early_idt_handler_array)
294
295early_idt_handler_common:
296 /*
297 * The stack is the hardware frame, an error code or zero, and the
298 * vector number.
299 */
300 cld
301
302 incl early_recursion_flag(%rip)
303
304 /* The vector number is currently in the pt_regs->di slot. */
305 pushq %rsi /* pt_regs->si */
306 movq 8(%rsp), %rsi /* RSI = vector number */
307 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
308 pushq %rdx /* pt_regs->dx */
309 pushq %rcx /* pt_regs->cx */
310 pushq %rax /* pt_regs->ax */
311 pushq %r8 /* pt_regs->r8 */
312 pushq %r9 /* pt_regs->r9 */
313 pushq %r10 /* pt_regs->r10 */
314 pushq %r11 /* pt_regs->r11 */
315 pushq %rbx /* pt_regs->bx */
316 pushq %rbp /* pt_regs->bp */
317 pushq %r12 /* pt_regs->r12 */
318 pushq %r13 /* pt_regs->r13 */
319 pushq %r14 /* pt_regs->r14 */
320 pushq %r15 /* pt_regs->r15 */
321 UNWIND_HINT_REGS
322
323 cmpq $14,%rsi /* Page fault? */
324 jnz 10f
325 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
326 call early_make_pgtable
327 andl %eax,%eax
328 jz 20f /* All good */
329
33010:
331 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
332 call early_fixup_exception
333
33420:
335 decl early_recursion_flag(%rip)
336 jmp restore_regs_and_return_to_kernel
337END(early_idt_handler_common)
338
339 __INITDATA
340
341 .balign 4
342GLOBAL(early_recursion_flag)
343 .long 0
344
345#define NEXT_PAGE(name) \
346 .balign PAGE_SIZE; \
347GLOBAL(name)
348
349#ifdef CONFIG_PAGE_TABLE_ISOLATION
350/*
351 * Each PGD needs to be 8k long and 8k aligned. We do not
352 * ever go out to userspace with these, so we do not
353 * strictly *need* the second page, but this allows us to
354 * have a single set_pgd() implementation that does not
355 * need to worry about whether it has 4k or 8k to work
356 * with.
357 *
358 * This ensures PGDs are 8k long:
359 */
360#define PTI_USER_PGD_FILL 512
361/* This ensures they are 8k-aligned: */
362#define NEXT_PGD_PAGE(name) \
363 .balign 2 * PAGE_SIZE; \
364GLOBAL(name)
365#else
366#define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
367#define PTI_USER_PGD_FILL 0
368#endif
369
370/* Automate the creation of 1 to 1 mapping pmd entries */
371#define PMDS(START, PERM, COUNT) \
372 i = 0 ; \
373 .rept (COUNT) ; \
374 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
375 i = i + 1 ; \
376 .endr
377
378 __INITDATA
379NEXT_PGD_PAGE(early_top_pgt)
380 .fill 512,8,0
381 .fill PTI_USER_PGD_FILL,8,0
382
383NEXT_PAGE(early_dynamic_pgts)
384 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
385
386 .data
387
388#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
389NEXT_PGD_PAGE(init_top_pgt)
390 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
391 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
392 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
393 .org init_top_pgt + L4_START_KERNEL*8, 0
394 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
395 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
396 .fill PTI_USER_PGD_FILL,8,0
397
398NEXT_PAGE(level3_ident_pgt)
399 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
400 .fill 511, 8, 0
401NEXT_PAGE(level2_ident_pgt)
402 /*
403 * Since I easily can, map the first 1G.
404 * Don't set NX because code runs from these pages.
405 *
406 * Note: This sets _PAGE_GLOBAL despite whether
407 * the CPU supports it or it is enabled. But,
408 * the CPU should ignore the bit.
409 */
410 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
411#else
412NEXT_PGD_PAGE(init_top_pgt)
413 .fill 512,8,0
414 .fill PTI_USER_PGD_FILL,8,0
415#endif
416
417#ifdef CONFIG_X86_5LEVEL
418NEXT_PAGE(level4_kernel_pgt)
419 .fill 511,8,0
420 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
421#endif
422
423NEXT_PAGE(level3_kernel_pgt)
424 .fill L3_START_KERNEL,8,0
425 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
426 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
427 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
428
429NEXT_PAGE(level2_kernel_pgt)
430 /*
431 * 512 MB kernel mapping. We spend a full page on this pagetable
432 * anyway.
433 *
434 * The kernel code+data+bss must not be bigger than that.
435 *
436 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
437 * If you want to increase this then increase MODULES_VADDR
438 * too.)
439 *
440 * This table is eventually used by the kernel during normal
441 * runtime. Care must be taken to clear out undesired bits
442 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
443 */
444 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
445 KERNEL_IMAGE_SIZE/PMD_SIZE)
446
447NEXT_PAGE(level2_fixmap_pgt)
448 .fill 506,8,0
449 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
450 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
451 .fill 5,8,0
452
453NEXT_PAGE(level1_fixmap_pgt)
454 .fill 512,8,0
455
456#undef PMDS
457
458 .data
459 .align 16
460 .globl early_gdt_descr
461early_gdt_descr:
462 .word GDT_ENTRIES*8-1
463early_gdt_descr_base:
464 .quad INIT_PER_CPU_VAR(gdt_page)
465
466ENTRY(phys_base)
467 /* This must match the first entry in level2_kernel_pgt */
468 .quad 0x0000000000000000
469EXPORT_SYMBOL(phys_base)
470
471#include "../../x86/xen/xen-head.S"
472
473 __PAGE_ALIGNED_BSS
474NEXT_PAGE(empty_zero_page)
475 .skip PAGE_SIZE
476EXPORT_SYMBOL(empty_zero_page)
477