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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10#include <linux/interrupt.h>
11#include <linux/ioport.h>
12
13#include <asm/bootinfo.h>
14#include <asm/irq_cpu.h>
15
16#include <lantiq_soc.h>
17#include <irq.h>
18
19/* register definitions */
20#define LTQ_ICU_IM0_ISR 0x0000
21#define LTQ_ICU_IM0_IER 0x0008
22#define LTQ_ICU_IM0_IOSR 0x0010
23#define LTQ_ICU_IM0_IRSR 0x0018
24#define LTQ_ICU_IM0_IMR 0x0020
25#define LTQ_ICU_IM1_ISR 0x0028
26#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
27
28#define LTQ_EIU_EXIN_C 0x0000
29#define LTQ_EIU_EXIN_INIC 0x0004
30#define LTQ_EIU_EXIN_INEN 0x000C
31
32/* irq numbers used by the external interrupt unit (EIU) */
33#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
34#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
35#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
36#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
37#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
38#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
39#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
40
41#define MAX_EIU 6
42
43/* irqs generated by device attached to the EBU need to be acked in
44 * a special manner
45 */
46#define LTQ_ICU_EBU_IRQ 22
47
48#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
49#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
50
51#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
52#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
53
54static unsigned short ltq_eiu_irq[MAX_EIU] = {
55 LTQ_EIU_IR0,
56 LTQ_EIU_IR1,
57 LTQ_EIU_IR2,
58 LTQ_EIU_IR3,
59 LTQ_EIU_IR4,
60 LTQ_EIU_IR5,
61};
62
63static struct resource ltq_icu_resource = {
64 .name = "icu",
65 .start = LTQ_ICU_BASE_ADDR,
66 .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1,
67 .flags = IORESOURCE_MEM,
68};
69
70static struct resource ltq_eiu_resource = {
71 .name = "eiu",
72 .start = LTQ_EIU_BASE_ADDR,
73 .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75};
76
77static void __iomem *ltq_icu_membase;
78static void __iomem *ltq_eiu_membase;
79
80void ltq_disable_irq(struct irq_data *d)
81{
82 u32 ier = LTQ_ICU_IM0_IER;
83 int irq_nr = d->irq - INT_NUM_IRQ0;
84
85 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
86 irq_nr %= INT_NUM_IM_OFFSET;
87 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
88}
89
90void ltq_mask_and_ack_irq(struct irq_data *d)
91{
92 u32 ier = LTQ_ICU_IM0_IER;
93 u32 isr = LTQ_ICU_IM0_ISR;
94 int irq_nr = d->irq - INT_NUM_IRQ0;
95
96 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
97 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
98 irq_nr %= INT_NUM_IM_OFFSET;
99 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
100 ltq_icu_w32((1 << irq_nr), isr);
101}
102
103static void ltq_ack_irq(struct irq_data *d)
104{
105 u32 isr = LTQ_ICU_IM0_ISR;
106 int irq_nr = d->irq - INT_NUM_IRQ0;
107
108 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
109 irq_nr %= INT_NUM_IM_OFFSET;
110 ltq_icu_w32((1 << irq_nr), isr);
111}
112
113void ltq_enable_irq(struct irq_data *d)
114{
115 u32 ier = LTQ_ICU_IM0_IER;
116 int irq_nr = d->irq - INT_NUM_IRQ0;
117
118 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
119 irq_nr %= INT_NUM_IM_OFFSET;
120 ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
121}
122
123static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
124{
125 int i;
126
127 ltq_enable_irq(d);
128 for (i = 0; i < MAX_EIU; i++) {
129 if (d->irq == ltq_eiu_irq[i]) {
130 /* low level - we should really handle set_type */
131 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
132 (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
133 /* clear all pending */
134 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i),
135 LTQ_EIU_EXIN_INIC);
136 /* enable */
137 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i),
138 LTQ_EIU_EXIN_INEN);
139 break;
140 }
141 }
142
143 return 0;
144}
145
146static void ltq_shutdown_eiu_irq(struct irq_data *d)
147{
148 int i;
149
150 ltq_disable_irq(d);
151 for (i = 0; i < MAX_EIU; i++) {
152 if (d->irq == ltq_eiu_irq[i]) {
153 /* disable */
154 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
155 LTQ_EIU_EXIN_INEN);
156 break;
157 }
158 }
159}
160
161static struct irq_chip ltq_irq_type = {
162 "icu",
163 .irq_enable = ltq_enable_irq,
164 .irq_disable = ltq_disable_irq,
165 .irq_unmask = ltq_enable_irq,
166 .irq_ack = ltq_ack_irq,
167 .irq_mask = ltq_disable_irq,
168 .irq_mask_ack = ltq_mask_and_ack_irq,
169};
170
171static struct irq_chip ltq_eiu_type = {
172 "eiu",
173 .irq_startup = ltq_startup_eiu_irq,
174 .irq_shutdown = ltq_shutdown_eiu_irq,
175 .irq_enable = ltq_enable_irq,
176 .irq_disable = ltq_disable_irq,
177 .irq_unmask = ltq_enable_irq,
178 .irq_ack = ltq_ack_irq,
179 .irq_mask = ltq_disable_irq,
180 .irq_mask_ack = ltq_mask_and_ack_irq,
181};
182
183static void ltq_hw_irqdispatch(int module)
184{
185 u32 irq;
186
187 irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
188 if (irq == 0)
189 return;
190
191 /* silicon bug causes only the msb set to 1 to be valid. all
192 * other bits might be bogus
193 */
194 irq = __fls(irq);
195 do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
196
197 /* if this is a EBU irq, we need to ack it or get a deadlock */
198 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
199 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
200 LTQ_EBU_PCC_ISTAT);
201}
202
203#define DEFINE_HWx_IRQDISPATCH(x) \
204 static void ltq_hw ## x ## _irqdispatch(void) \
205 { \
206 ltq_hw_irqdispatch(x); \
207 }
208DEFINE_HWx_IRQDISPATCH(0)
209DEFINE_HWx_IRQDISPATCH(1)
210DEFINE_HWx_IRQDISPATCH(2)
211DEFINE_HWx_IRQDISPATCH(3)
212DEFINE_HWx_IRQDISPATCH(4)
213
214static void ltq_hw5_irqdispatch(void)
215{
216 do_IRQ(MIPS_CPU_TIMER_IRQ);
217}
218
219asmlinkage void plat_irq_dispatch(void)
220{
221 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
222 unsigned int i;
223
224 if (pending & CAUSEF_IP7) {
225 do_IRQ(MIPS_CPU_TIMER_IRQ);
226 goto out;
227 } else {
228 for (i = 0; i < 5; i++) {
229 if (pending & (CAUSEF_IP2 << i)) {
230 ltq_hw_irqdispatch(i);
231 goto out;
232 }
233 }
234 }
235 pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
236
237out:
238 return;
239}
240
241static struct irqaction cascade = {
242 .handler = no_action,
243 .flags = IRQF_DISABLED,
244 .name = "cascade",
245};
246
247void __init arch_init_irq(void)
248{
249 int i;
250
251 if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
252 panic("Failed to insert icu memory\n");
253
254 if (request_mem_region(ltq_icu_resource.start,
255 resource_size(<q_icu_resource), "icu") < 0)
256 panic("Failed to request icu memory\n");
257
258 ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
259 resource_size(<q_icu_resource));
260 if (!ltq_icu_membase)
261 panic("Failed to remap icu memory\n");
262
263 if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
264 panic("Failed to insert eiu memory\n");
265
266 if (request_mem_region(ltq_eiu_resource.start,
267 resource_size(<q_eiu_resource), "eiu") < 0)
268 panic("Failed to request eiu memory\n");
269
270 ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
271 resource_size(<q_eiu_resource));
272 if (!ltq_eiu_membase)
273 panic("Failed to remap eiu memory\n");
274
275 /* make sure all irqs are turned off by default */
276 for (i = 0; i < 5; i++)
277 ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
278
279 /* clear all possibly pending interrupts */
280 ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
281
282 mips_cpu_irq_init();
283
284 for (i = 2; i <= 6; i++)
285 setup_irq(i, &cascade);
286
287 if (cpu_has_vint) {
288 pr_info("Setting up vectored interrupts\n");
289 set_vi_handler(2, ltq_hw0_irqdispatch);
290 set_vi_handler(3, ltq_hw1_irqdispatch);
291 set_vi_handler(4, ltq_hw2_irqdispatch);
292 set_vi_handler(5, ltq_hw3_irqdispatch);
293 set_vi_handler(6, ltq_hw4_irqdispatch);
294 set_vi_handler(7, ltq_hw5_irqdispatch);
295 }
296
297 for (i = INT_NUM_IRQ0;
298 i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
299 if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
300 (i == LTQ_EIU_IR2))
301 irq_set_chip_and_handler(i, <q_eiu_type,
302 handle_level_irq);
303 /* EIU3-5 only exist on ar9 and vr9 */
304 else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
305 (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
306 irq_set_chip_and_handler(i, <q_eiu_type,
307 handle_level_irq);
308 else
309 irq_set_chip_and_handler(i, <q_irq_type,
310 handle_level_irq);
311
312#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
313 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
314 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
315#else
316 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
317 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
318#endif
319}
320
321unsigned int __cpuinit get_c0_compare_int(void)
322{
323 return CP0_LEGACY_COMPARE_IRQ;
324}
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10#include <linux/interrupt.h>
11#include <linux/ioport.h>
12#include <linux/sched.h>
13#include <linux/irqdomain.h>
14#include <linux/of_platform.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17
18#include <asm/bootinfo.h>
19#include <asm/irq_cpu.h>
20
21#include <lantiq_soc.h>
22#include <irq.h>
23
24/* register definitions - internal irqs */
25#define LTQ_ICU_IM0_ISR 0x0000
26#define LTQ_ICU_IM0_IER 0x0008
27#define LTQ_ICU_IM0_IOSR 0x0010
28#define LTQ_ICU_IM0_IRSR 0x0018
29#define LTQ_ICU_IM0_IMR 0x0020
30#define LTQ_ICU_IM1_ISR 0x0028
31#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
32
33/* register definitions - external irqs */
34#define LTQ_EIU_EXIN_C 0x0000
35#define LTQ_EIU_EXIN_INIC 0x0004
36#define LTQ_EIU_EXIN_INC 0x0008
37#define LTQ_EIU_EXIN_INEN 0x000C
38
39/* number of external interrupts */
40#define MAX_EIU 6
41
42/* the performance counter */
43#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
44
45/*
46 * irqs generated by devices attached to the EBU need to be acked in
47 * a special manner
48 */
49#define LTQ_ICU_EBU_IRQ 22
50
51#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
53
54#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
56
57/* our 2 ipi interrupts for VSMP */
58#define MIPS_CPU_IPI_RESCHED_IRQ 0
59#define MIPS_CPU_IPI_CALL_IRQ 1
60
61/* we have a cascade of 8 irqs */
62#define MIPS_CPU_IRQ_CASCADE 8
63
64static int exin_avail;
65static u32 ltq_eiu_irq[MAX_EIU];
66static void __iomem *ltq_icu_membase[MAX_IM];
67static void __iomem *ltq_eiu_membase;
68static struct irq_domain *ltq_domain;
69static int ltq_perfcount_irq;
70
71int ltq_eiu_get_irq(int exin)
72{
73 if (exin < exin_avail)
74 return ltq_eiu_irq[exin];
75 return -1;
76}
77
78void ltq_disable_irq(struct irq_data *d)
79{
80 u32 ier = LTQ_ICU_IM0_IER;
81 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
82 int im = offset / INT_NUM_IM_OFFSET;
83
84 offset %= INT_NUM_IM_OFFSET;
85 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
86}
87
88void ltq_mask_and_ack_irq(struct irq_data *d)
89{
90 u32 ier = LTQ_ICU_IM0_IER;
91 u32 isr = LTQ_ICU_IM0_ISR;
92 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
93 int im = offset / INT_NUM_IM_OFFSET;
94
95 offset %= INT_NUM_IM_OFFSET;
96 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
97 ltq_icu_w32(im, BIT(offset), isr);
98}
99
100static void ltq_ack_irq(struct irq_data *d)
101{
102 u32 isr = LTQ_ICU_IM0_ISR;
103 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
104 int im = offset / INT_NUM_IM_OFFSET;
105
106 offset %= INT_NUM_IM_OFFSET;
107 ltq_icu_w32(im, BIT(offset), isr);
108}
109
110void ltq_enable_irq(struct irq_data *d)
111{
112 u32 ier = LTQ_ICU_IM0_IER;
113 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
114 int im = offset / INT_NUM_IM_OFFSET;
115
116 offset %= INT_NUM_IM_OFFSET;
117 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
118}
119
120static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
121{
122 int i;
123
124 for (i = 0; i < exin_avail; i++) {
125 if (d->hwirq == ltq_eiu_irq[i]) {
126 int val = 0;
127 int edge = 0;
128
129 switch (type) {
130 case IRQF_TRIGGER_NONE:
131 break;
132 case IRQF_TRIGGER_RISING:
133 val = 1;
134 edge = 1;
135 break;
136 case IRQF_TRIGGER_FALLING:
137 val = 2;
138 edge = 1;
139 break;
140 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
141 val = 3;
142 edge = 1;
143 break;
144 case IRQF_TRIGGER_HIGH:
145 val = 5;
146 break;
147 case IRQF_TRIGGER_LOW:
148 val = 6;
149 break;
150 default:
151 pr_err("invalid type %d for irq %ld\n",
152 type, d->hwirq);
153 return -EINVAL;
154 }
155
156 if (edge)
157 irq_set_handler(d->hwirq, handle_edge_irq);
158
159 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
160 (val << (i * 4)), LTQ_EIU_EXIN_C);
161 }
162 }
163
164 return 0;
165}
166
167static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
168{
169 int i;
170
171 ltq_enable_irq(d);
172 for (i = 0; i < exin_avail; i++) {
173 if (d->hwirq == ltq_eiu_irq[i]) {
174 /* by default we are low level triggered */
175 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
176 /* clear all pending */
177 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
178 LTQ_EIU_EXIN_INC);
179 /* enable */
180 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
181 LTQ_EIU_EXIN_INEN);
182 break;
183 }
184 }
185
186 return 0;
187}
188
189static void ltq_shutdown_eiu_irq(struct irq_data *d)
190{
191 int i;
192
193 ltq_disable_irq(d);
194 for (i = 0; i < exin_avail; i++) {
195 if (d->hwirq == ltq_eiu_irq[i]) {
196 /* disable */
197 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
198 LTQ_EIU_EXIN_INEN);
199 break;
200 }
201 }
202}
203
204static struct irq_chip ltq_irq_type = {
205 .name = "icu",
206 .irq_enable = ltq_enable_irq,
207 .irq_disable = ltq_disable_irq,
208 .irq_unmask = ltq_enable_irq,
209 .irq_ack = ltq_ack_irq,
210 .irq_mask = ltq_disable_irq,
211 .irq_mask_ack = ltq_mask_and_ack_irq,
212};
213
214static struct irq_chip ltq_eiu_type = {
215 .name = "eiu",
216 .irq_startup = ltq_startup_eiu_irq,
217 .irq_shutdown = ltq_shutdown_eiu_irq,
218 .irq_enable = ltq_enable_irq,
219 .irq_disable = ltq_disable_irq,
220 .irq_unmask = ltq_enable_irq,
221 .irq_ack = ltq_ack_irq,
222 .irq_mask = ltq_disable_irq,
223 .irq_mask_ack = ltq_mask_and_ack_irq,
224 .irq_set_type = ltq_eiu_settype,
225};
226
227static void ltq_hw_irqdispatch(int module)
228{
229 u32 irq;
230
231 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
232 if (irq == 0)
233 return;
234
235 /*
236 * silicon bug causes only the msb set to 1 to be valid. all
237 * other bits might be bogus
238 */
239 irq = __fls(irq);
240 do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
241
242 /* if this is a EBU irq, we need to ack it or get a deadlock */
243 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
244 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
245 LTQ_EBU_PCC_ISTAT);
246}
247
248#define DEFINE_HWx_IRQDISPATCH(x) \
249 static void ltq_hw ## x ## _irqdispatch(void) \
250 { \
251 ltq_hw_irqdispatch(x); \
252 }
253DEFINE_HWx_IRQDISPATCH(0)
254DEFINE_HWx_IRQDISPATCH(1)
255DEFINE_HWx_IRQDISPATCH(2)
256DEFINE_HWx_IRQDISPATCH(3)
257DEFINE_HWx_IRQDISPATCH(4)
258
259#if MIPS_CPU_TIMER_IRQ == 7
260static void ltq_hw5_irqdispatch(void)
261{
262 do_IRQ(MIPS_CPU_TIMER_IRQ);
263}
264#else
265DEFINE_HWx_IRQDISPATCH(5)
266#endif
267
268static void ltq_hw_irq_handler(struct irq_desc *desc)
269{
270 ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
271}
272
273asmlinkage void plat_irq_dispatch(void)
274{
275 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
276 int irq;
277
278 if (!pending) {
279 spurious_interrupt();
280 return;
281 }
282
283 pending >>= CAUSEB_IP;
284 while (pending) {
285 irq = fls(pending) - 1;
286 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
287 pending &= ~BIT(irq);
288 }
289}
290
291static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
292{
293 struct irq_chip *chip = <q_irq_type;
294 int i;
295
296 if (hw < MIPS_CPU_IRQ_CASCADE)
297 return 0;
298
299 for (i = 0; i < exin_avail; i++)
300 if (hw == ltq_eiu_irq[i])
301 chip = <q_eiu_type;
302
303 irq_set_chip_and_handler(irq, chip, handle_level_irq);
304
305 return 0;
306}
307
308static const struct irq_domain_ops irq_domain_ops = {
309 .xlate = irq_domain_xlate_onetwocell,
310 .map = icu_map,
311};
312
313int __init icu_of_init(struct device_node *node, struct device_node *parent)
314{
315 struct device_node *eiu_node;
316 struct resource res;
317 int i, ret;
318
319 for (i = 0; i < MAX_IM; i++) {
320 if (of_address_to_resource(node, i, &res))
321 panic("Failed to get icu memory range");
322
323 if (!request_mem_region(res.start, resource_size(&res),
324 res.name))
325 pr_err("Failed to request icu memory");
326
327 ltq_icu_membase[i] = ioremap_nocache(res.start,
328 resource_size(&res));
329 if (!ltq_icu_membase[i])
330 panic("Failed to remap icu memory");
331 }
332
333 /* turn off all irqs by default */
334 for (i = 0; i < MAX_IM; i++) {
335 /* make sure all irqs are turned off by default */
336 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
337 /* clear all possibly pending interrupts */
338 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
339 }
340
341 mips_cpu_irq_init();
342
343 for (i = 0; i < MAX_IM; i++)
344 irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
345
346 if (cpu_has_vint) {
347 pr_info("Setting up vectored interrupts\n");
348 set_vi_handler(2, ltq_hw0_irqdispatch);
349 set_vi_handler(3, ltq_hw1_irqdispatch);
350 set_vi_handler(4, ltq_hw2_irqdispatch);
351 set_vi_handler(5, ltq_hw3_irqdispatch);
352 set_vi_handler(6, ltq_hw4_irqdispatch);
353 set_vi_handler(7, ltq_hw5_irqdispatch);
354 }
355
356 ltq_domain = irq_domain_add_linear(node,
357 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
358 &irq_domain_ops, 0);
359
360#ifndef CONFIG_MIPS_MT_SMP
361 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
362 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
363#else
364 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
365 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
366#endif
367
368 /* tell oprofile which irq to use */
369 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
370
371 /*
372 * if the timer irq is not one of the mips irqs we need to
373 * create a mapping
374 */
375 if (MIPS_CPU_TIMER_IRQ != 7)
376 irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
377
378 /* the external interrupts are optional and xway only */
379 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
380 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
381 /* find out how many external irq sources we have */
382 exin_avail = of_property_count_u32_elems(eiu_node,
383 "lantiq,eiu-irqs");
384
385 if (exin_avail > MAX_EIU)
386 exin_avail = MAX_EIU;
387
388 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
389 ltq_eiu_irq, exin_avail);
390 if (ret)
391 panic("failed to load external irq resources");
392
393 if (!request_mem_region(res.start, resource_size(&res),
394 res.name))
395 pr_err("Failed to request eiu memory");
396
397 ltq_eiu_membase = ioremap_nocache(res.start,
398 resource_size(&res));
399 if (!ltq_eiu_membase)
400 panic("Failed to remap eiu memory");
401 }
402
403 return 0;
404}
405
406int get_c0_perfcount_int(void)
407{
408 return ltq_perfcount_irq;
409}
410EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
411
412unsigned int get_c0_compare_int(void)
413{
414 return MIPS_CPU_TIMER_IRQ;
415}
416
417static struct of_device_id __initdata of_irq_ids[] = {
418 { .compatible = "lantiq,icu", .data = icu_of_init },
419 {},
420};
421
422void __init arch_init_irq(void)
423{
424 of_irq_init(of_irq_ids);
425}