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1/*
2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
8 *
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
31 *
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
33 *
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
35 *
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * more information.
40 *
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
45 *
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
50 */
51
52#include <linux/linkage.h>
53#include <linux/init.h>
54#include <asm/assembler.h>
55#include <asm/hwcap.h>
56#include <asm/pgtable-hwdef.h>
57#include <asm/pgtable.h>
58#include <asm/page.h>
59#include <asm/ptrace.h>
60#include "proc-macros.S"
61
62/*
63 * The size of one data cache line.
64 */
65#define CACHE_DLINESIZE 16
66
67/*
68 * The number of data cache segments.
69 */
70#define CACHE_DSEGMENTS 2
71
72/*
73 * The number of lines in a cache segment.
74 */
75#define CACHE_DENTRIES 256
76
77/*
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintenance instructions.
81 */
82#define CACHE_DLIMIT 8192
83
84 .text
85/*
86 * cpu_arm925_proc_init()
87 */
88ENTRY(cpu_arm925_proc_init)
89 mov pc, lr
90
91/*
92 * cpu_arm925_proc_fin()
93 */
94ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mov pc, lr
100
101/*
102 * cpu_arm925_reset(loc)
103 *
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
107 *
108 * loc: location to jump to for soft reset
109 */
110 .align 5
111ENTRY(cpu_arm925_reset)
112 /* Send software reset to MPU and DSP */
113 mov ip, #0xff000000
114 orr ip, ip, #0x00fe0000
115 orr ip, ip, #0x0000ce00
116 mov r4, #1
117 strh r4, [ip, #0x10]
118
119 mov ip, #0
120 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
121 mcr p15, 0, ip, c7, c10, 4 @ drain WB
122#ifdef CONFIG_MMU
123 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
124#endif
125 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
126 bic ip, ip, #0x000f @ ............wcam
127 bic ip, ip, #0x1100 @ ...i...s........
128 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
129 mov pc, r0
130
131/*
132 * cpu_arm925_do_idle()
133 *
134 * Called with IRQs disabled
135 */
136 .align 10
137ENTRY(cpu_arm925_do_idle)
138 mov r0, #0
139 mrc p15, 0, r1, c1, c0, 0 @ Read control register
140 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
141 bic r2, r1, #1 << 12
142 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
143 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
145 mov pc, lr
146
147/*
148 * flush_icache_all()
149 *
150 * Unconditionally clean and invalidate the entire icache.
151 */
152ENTRY(arm925_flush_icache_all)
153 mov r0, #0
154 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mov pc, lr
156ENDPROC(arm925_flush_icache_all)
157
158/*
159 * flush_user_cache_all()
160 *
161 * Clean and invalidate all cache entries in a particular
162 * address space.
163 */
164ENTRY(arm925_flush_user_cache_all)
165 /* FALLTHROUGH */
166
167/*
168 * flush_kern_cache_all()
169 *
170 * Clean and invalidate the entire cache.
171 */
172ENTRY(arm925_flush_kern_cache_all)
173 mov r2, #VM_EXEC
174 mov ip, #0
175__flush_whole_cache:
176#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
177 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
178#else
179 /* Flush entries in both segments at once, see NOTE1 above */
180 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
1812: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
182 subs r3, r3, #1 << 4
183 bcs 2b @ entries 255 to 0
184#endif
185 tst r2, #VM_EXEC
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 mov pc, lr
189
190/*
191 * flush_user_cache_range(start, end, flags)
192 *
193 * Clean and invalidate a range of cache entries in the
194 * specified address range.
195 *
196 * - start - start address (inclusive)
197 * - end - end address (exclusive)
198 * - flags - vm_flags describing address space
199 */
200ENTRY(arm925_flush_user_cache_range)
201 mov ip, #0
202 sub r3, r1, r0 @ calculate total size
203 cmp r3, #CACHE_DLIMIT
204 bgt __flush_whole_cache
2051: tst r2, #VM_EXEC
206#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
207 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 add r0, r0, #CACHE_DLINESIZE
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213#else
214 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
215 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
216 add r0, r0, #CACHE_DLINESIZE
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220#endif
221 cmp r0, r1
222 blo 1b
223 tst r2, #VM_EXEC
224 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
225 mov pc, lr
226
227/*
228 * coherent_kern_range(start, end)
229 *
230 * Ensure coherency between the Icache and the Dcache in the
231 * region described by start, end. If you have non-snooping
232 * Harvard caches, you need to implement this function.
233 *
234 * - start - virtual start address
235 * - end - virtual end address
236 */
237ENTRY(arm925_coherent_kern_range)
238 /* FALLTHROUGH */
239
240/*
241 * coherent_user_range(start, end)
242 *
243 * Ensure coherency between the Icache and the Dcache in the
244 * region described by start, end. If you have non-snooping
245 * Harvard caches, you need to implement this function.
246 *
247 * - start - virtual start address
248 * - end - virtual end address
249 */
250ENTRY(arm925_coherent_user_range)
251 bic r0, r0, #CACHE_DLINESIZE - 1
2521: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
253 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
254 add r0, r0, #CACHE_DLINESIZE
255 cmp r0, r1
256 blo 1b
257 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 mov pc, lr
259
260/*
261 * flush_kern_dcache_area(void *addr, size_t size)
262 *
263 * Ensure no D cache aliasing occurs, either with itself or
264 * the I cache
265 *
266 * - addr - kernel address
267 * - size - region size
268 */
269ENTRY(arm925_flush_kern_dcache_area)
270 add r1, r0, r1
2711: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
272 add r0, r0, #CACHE_DLINESIZE
273 cmp r0, r1
274 blo 1b
275 mov r0, #0
276 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
277 mcr p15, 0, r0, c7, c10, 4 @ drain WB
278 mov pc, lr
279
280/*
281 * dma_inv_range(start, end)
282 *
283 * Invalidate (discard) the specified virtual address range.
284 * May not write back any entries. If 'start' or 'end'
285 * are not cache line aligned, those lines must be written
286 * back.
287 *
288 * - start - virtual start address
289 * - end - virtual end address
290 *
291 * (same as v4wb)
292 */
293arm925_dma_inv_range:
294#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
295 tst r0, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
297 tst r1, #CACHE_DLINESIZE - 1
298 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
299#endif
300 bic r0, r0, #CACHE_DLINESIZE - 1
3011: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305 mcr p15, 0, r0, c7, c10, 4 @ drain WB
306 mov pc, lr
307
308/*
309 * dma_clean_range(start, end)
310 *
311 * Clean the specified virtual address range.
312 *
313 * - start - virtual start address
314 * - end - virtual end address
315 *
316 * (same as v4wb)
317 */
318arm925_dma_clean_range:
319#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
320 bic r0, r0, #CACHE_DLINESIZE - 1
3211: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
324 blo 1b
325#endif
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 mov pc, lr
328
329/*
330 * dma_flush_range(start, end)
331 *
332 * Clean and invalidate the specified virtual address range.
333 *
334 * - start - virtual start address
335 * - end - virtual end address
336 */
337ENTRY(arm925_dma_flush_range)
338 bic r0, r0, #CACHE_DLINESIZE - 1
3391:
340#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
342#else
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
344#endif
345 add r0, r0, #CACHE_DLINESIZE
346 cmp r0, r1
347 blo 1b
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
349 mov pc, lr
350
351/*
352 * dma_map_area(start, size, dir)
353 * - start - kernel virtual start address
354 * - size - size of region
355 * - dir - DMA direction
356 */
357ENTRY(arm925_dma_map_area)
358 add r1, r1, r0
359 cmp r2, #DMA_TO_DEVICE
360 beq arm925_dma_clean_range
361 bcs arm925_dma_inv_range
362 b arm925_dma_flush_range
363ENDPROC(arm925_dma_map_area)
364
365/*
366 * dma_unmap_area(start, size, dir)
367 * - start - kernel virtual start address
368 * - size - size of region
369 * - dir - DMA direction
370 */
371ENTRY(arm925_dma_unmap_area)
372 mov pc, lr
373ENDPROC(arm925_dma_unmap_area)
374
375 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
376 define_cache_functions arm925
377
378ENTRY(cpu_arm925_dcache_clean_area)
379#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
381 add r0, r0, #CACHE_DLINESIZE
382 subs r1, r1, #CACHE_DLINESIZE
383 bhi 1b
384#endif
385 mcr p15, 0, r0, c7, c10, 4 @ drain WB
386 mov pc, lr
387
388/* =============================== PageTable ============================== */
389
390/*
391 * cpu_arm925_switch_mm(pgd)
392 *
393 * Set the translation base pointer to be as described by pgd.
394 *
395 * pgd: new page tables
396 */
397 .align 5
398ENTRY(cpu_arm925_switch_mm)
399#ifdef CONFIG_MMU
400 mov ip, #0
401#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
402 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
403#else
404 /* Flush entries in bothe segments at once, see NOTE1 above */
405 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
4062: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
407 subs r3, r3, #1 << 4
408 bcs 2b @ entries 255 to 0
409#endif
410 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
411 mcr p15, 0, ip, c7, c10, 4 @ drain WB
412 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
413 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
414#endif
415 mov pc, lr
416
417/*
418 * cpu_arm925_set_pte_ext(ptep, pte, ext)
419 *
420 * Set a PTE and flush it out
421 */
422 .align 5
423ENTRY(cpu_arm925_set_pte_ext)
424#ifdef CONFIG_MMU
425 armv3_set_pte_ext
426 mov r0, r0
427#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
428 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
429#endif
430 mcr p15, 0, r0, c7, c10, 4 @ drain WB
431#endif /* CONFIG_MMU */
432 mov pc, lr
433
434 __CPUINIT
435
436 .type __arm925_setup, #function
437__arm925_setup:
438 mov r0, #0
439#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
440 orr r0,r0,#1 << 7
441#endif
442
443 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
444 orr r0,r0,#1 << 1 @ transparent mode on
445 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
446
447 mov r0, #0
448 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
449 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
450#ifdef CONFIG_MMU
451 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
452#endif
453
454#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
455 mov r0, #4 @ disable write-back on caches explicitly
456 mcr p15, 7, r0, c15, c0, 0
457#endif
458
459 adr r5, arm925_crval
460 ldmia r5, {r5, r6}
461 mrc p15, 0, r0, c1, c0 @ get control register v4
462 bic r0, r0, r5
463 orr r0, r0, r6
464#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
465 orr r0, r0, #0x4000 @ .1.. .... .... ....
466#endif
467 mov pc, lr
468 .size __arm925_setup, . - __arm925_setup
469
470 /*
471 * R
472 * .RVI ZFRS BLDP WCAM
473 * .011 0001 ..11 1101
474 *
475 */
476 .type arm925_crval, #object
477arm925_crval:
478 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
479
480 __INITDATA
481 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
482 define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
483
484 .section ".rodata"
485
486 string cpu_arch_name, "armv4t"
487 string cpu_elf_name, "v4"
488 string cpu_arm925_name, "ARM925T"
489
490 .align
491
492 .section ".proc.info.init", #alloc, #execinstr
493
494.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
495 .type __\name\()_proc_info,#object
496__\name\()_proc_info:
497 .long \cpu_val
498 .long \cpu_mask
499 .long PMD_TYPE_SECT | \
500 PMD_BIT4 | \
501 PMD_SECT_AP_WRITE | \
502 PMD_SECT_AP_READ
503 .long PMD_TYPE_SECT | \
504 PMD_BIT4 | \
505 PMD_SECT_AP_WRITE | \
506 PMD_SECT_AP_READ
507 b __arm925_setup
508 .long cpu_arch_name
509 .long cpu_elf_name
510 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
511 .long cpu_arm925_name
512 .long arm925_processor_functions
513 .long v4wbi_tlb_fns
514 .long v4wb_user_fns
515 .long arm925_cache_fns
516 .size __\name\()_proc_info, . - __\name\()_proc_info
517.endm
518
519 arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
520 arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name
1/*
2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
8 *
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
31 *
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
33 *
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
35 *
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * more information.
40 *
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
45 *
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
50 */
51
52#include <linux/linkage.h>
53#include <linux/init.h>
54#include <asm/assembler.h>
55#include <asm/hwcap.h>
56#include <asm/pgtable-hwdef.h>
57#include <asm/pgtable.h>
58#include <asm/page.h>
59#include <asm/ptrace.h>
60#include "proc-macros.S"
61
62/*
63 * The size of one data cache line.
64 */
65#define CACHE_DLINESIZE 16
66
67/*
68 * The number of data cache segments.
69 */
70#define CACHE_DSEGMENTS 2
71
72/*
73 * The number of lines in a cache segment.
74 */
75#define CACHE_DENTRIES 256
76
77/*
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintenance instructions.
81 */
82#define CACHE_DLIMIT 8192
83
84 .text
85/*
86 * cpu_arm925_proc_init()
87 */
88ENTRY(cpu_arm925_proc_init)
89 ret lr
90
91/*
92 * cpu_arm925_proc_fin()
93 */
94ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret lr
100
101/*
102 * cpu_arm925_reset(loc)
103 *
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
107 *
108 * loc: location to jump to for soft reset
109 */
110 .align 5
111 .pushsection .idmap.text, "ax"
112ENTRY(cpu_arm925_reset)
113 /* Send software reset to MPU and DSP */
114 mov ip, #0xff000000
115 orr ip, ip, #0x00fe0000
116 orr ip, ip, #0x0000ce00
117 mov r4, #1
118 strh r4, [ip, #0x10]
119ENDPROC(cpu_arm925_reset)
120 .popsection
121
122 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
125#ifdef CONFIG_MMU
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127#endif
128 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
129 bic ip, ip, #0x000f @ ............wcam
130 bic ip, ip, #0x1100 @ ...i...s........
131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 ret r0
133
134/*
135 * cpu_arm925_do_idle()
136 *
137 * Called with IRQs disabled
138 */
139 .align 10
140ENTRY(cpu_arm925_do_idle)
141 mov r0, #0
142 mrc p15, 0, r1, c1, c0, 0 @ Read control register
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
144 bic r2, r1, #1 << 12
145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
148 ret lr
149
150/*
151 * flush_icache_all()
152 *
153 * Unconditionally clean and invalidate the entire icache.
154 */
155ENTRY(arm925_flush_icache_all)
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 ret lr
159ENDPROC(arm925_flush_icache_all)
160
161/*
162 * flush_user_cache_all()
163 *
164 * Clean and invalidate all cache entries in a particular
165 * address space.
166 */
167ENTRY(arm925_flush_user_cache_all)
168 /* FALLTHROUGH */
169
170/*
171 * flush_kern_cache_all()
172 *
173 * Clean and invalidate the entire cache.
174 */
175ENTRY(arm925_flush_kern_cache_all)
176 mov r2, #VM_EXEC
177 mov ip, #0
178__flush_whole_cache:
179#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
181#else
182 /* Flush entries in both segments at once, see NOTE1 above */
183 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
1842: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
185 subs r3, r3, #1 << 4
186 bcs 2b @ entries 255 to 0
187#endif
188 tst r2, #VM_EXEC
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
191 ret lr
192
193/*
194 * flush_user_cache_range(start, end, flags)
195 *
196 * Clean and invalidate a range of cache entries in the
197 * specified address range.
198 *
199 * - start - start address (inclusive)
200 * - end - end address (exclusive)
201 * - flags - vm_flags describing address space
202 */
203ENTRY(arm925_flush_user_cache_range)
204 mov ip, #0
205 sub r3, r1, r0 @ calculate total size
206 cmp r3, #CACHE_DLIMIT
207 bgt __flush_whole_cache
2081: tst r2, #VM_EXEC
209#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
215 add r0, r0, #CACHE_DLINESIZE
216#else
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
223#endif
224 cmp r0, r1
225 blo 1b
226 tst r2, #VM_EXEC
227 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
228 ret lr
229
230/*
231 * coherent_kern_range(start, end)
232 *
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start, end. If you have non-snooping
235 * Harvard caches, you need to implement this function.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 */
240ENTRY(arm925_coherent_kern_range)
241 /* FALLTHROUGH */
242
243/*
244 * coherent_user_range(start, end)
245 *
246 * Ensure coherency between the Icache and the Dcache in the
247 * region described by start, end. If you have non-snooping
248 * Harvard caches, you need to implement this function.
249 *
250 * - start - virtual start address
251 * - end - virtual end address
252 */
253ENTRY(arm925_coherent_user_range)
254 bic r0, r0, #CACHE_DLINESIZE - 1
2551: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
257 add r0, r0, #CACHE_DLINESIZE
258 cmp r0, r1
259 blo 1b
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 mov r0, #0
262 ret lr
263
264/*
265 * flush_kern_dcache_area(void *addr, size_t size)
266 *
267 * Ensure no D cache aliasing occurs, either with itself or
268 * the I cache
269 *
270 * - addr - kernel address
271 * - size - region size
272 */
273ENTRY(arm925_flush_kern_dcache_area)
274 add r1, r0, r1
2751: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 add r0, r0, #CACHE_DLINESIZE
277 cmp r0, r1
278 blo 1b
279 mov r0, #0
280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
282 ret lr
283
284/*
285 * dma_inv_range(start, end)
286 *
287 * Invalidate (discard) the specified virtual address range.
288 * May not write back any entries. If 'start' or 'end'
289 * are not cache line aligned, those lines must be written
290 * back.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 *
295 * (same as v4wb)
296 */
297arm925_dma_inv_range:
298#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
299 tst r0, #CACHE_DLINESIZE - 1
300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
301 tst r1, #CACHE_DLINESIZE - 1
302 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
303#endif
304 bic r0, r0, #CACHE_DLINESIZE - 1
3051: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
306 add r0, r0, #CACHE_DLINESIZE
307 cmp r0, r1
308 blo 1b
309 mcr p15, 0, r0, c7, c10, 4 @ drain WB
310 ret lr
311
312/*
313 * dma_clean_range(start, end)
314 *
315 * Clean the specified virtual address range.
316 *
317 * - start - virtual start address
318 * - end - virtual end address
319 *
320 * (same as v4wb)
321 */
322arm925_dma_clean_range:
323#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
324 bic r0, r0, #CACHE_DLINESIZE - 1
3251: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE
327 cmp r0, r1
328 blo 1b
329#endif
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 ret lr
332
333/*
334 * dma_flush_range(start, end)
335 *
336 * Clean and invalidate the specified virtual address range.
337 *
338 * - start - virtual start address
339 * - end - virtual end address
340 */
341ENTRY(arm925_dma_flush_range)
342 bic r0, r0, #CACHE_DLINESIZE - 1
3431:
344#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
346#else
347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
348#endif
349 add r0, r0, #CACHE_DLINESIZE
350 cmp r0, r1
351 blo 1b
352 mcr p15, 0, r0, c7, c10, 4 @ drain WB
353 ret lr
354
355/*
356 * dma_map_area(start, size, dir)
357 * - start - kernel virtual start address
358 * - size - size of region
359 * - dir - DMA direction
360 */
361ENTRY(arm925_dma_map_area)
362 add r1, r1, r0
363 cmp r2, #DMA_TO_DEVICE
364 beq arm925_dma_clean_range
365 bcs arm925_dma_inv_range
366 b arm925_dma_flush_range
367ENDPROC(arm925_dma_map_area)
368
369/*
370 * dma_unmap_area(start, size, dir)
371 * - start - kernel virtual start address
372 * - size - size of region
373 * - dir - DMA direction
374 */
375ENTRY(arm925_dma_unmap_area)
376 ret lr
377ENDPROC(arm925_dma_unmap_area)
378
379 .globl arm925_flush_kern_cache_louis
380 .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
381
382 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
383 define_cache_functions arm925
384
385ENTRY(cpu_arm925_dcache_clean_area)
386#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3871: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
388 add r0, r0, #CACHE_DLINESIZE
389 subs r1, r1, #CACHE_DLINESIZE
390 bhi 1b
391#endif
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
393 ret lr
394
395/* =============================== PageTable ============================== */
396
397/*
398 * cpu_arm925_switch_mm(pgd)
399 *
400 * Set the translation base pointer to be as described by pgd.
401 *
402 * pgd: new page tables
403 */
404 .align 5
405ENTRY(cpu_arm925_switch_mm)
406#ifdef CONFIG_MMU
407 mov ip, #0
408#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
409 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
410#else
411 /* Flush entries in bothe segments at once, see NOTE1 above */
412 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
4132: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
414 subs r3, r3, #1 << 4
415 bcs 2b @ entries 255 to 0
416#endif
417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
418 mcr p15, 0, ip, c7, c10, 4 @ drain WB
419 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
421#endif
422 ret lr
423
424/*
425 * cpu_arm925_set_pte_ext(ptep, pte, ext)
426 *
427 * Set a PTE and flush it out
428 */
429 .align 5
430ENTRY(cpu_arm925_set_pte_ext)
431#ifdef CONFIG_MMU
432 armv3_set_pte_ext
433 mov r0, r0
434#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
435 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
436#endif
437 mcr p15, 0, r0, c7, c10, 4 @ drain WB
438#endif /* CONFIG_MMU */
439 ret lr
440
441 .type __arm925_setup, #function
442__arm925_setup:
443 mov r0, #0
444
445 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
446 orr r0,r0,#1 << 1 @ transparent mode on
447 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
448
449 mov r0, #0
450 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
451 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
452#ifdef CONFIG_MMU
453 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
454#endif
455
456#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
457 mov r0, #4 @ disable write-back on caches explicitly
458 mcr p15, 7, r0, c15, c0, 0
459#endif
460
461 adr r5, arm925_crval
462 ldmia r5, {r5, r6}
463 mrc p15, 0, r0, c1, c0 @ get control register v4
464 bic r0, r0, r5
465 orr r0, r0, r6
466#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
467 orr r0, r0, #0x4000 @ .1.. .... .... ....
468#endif
469 ret lr
470 .size __arm925_setup, . - __arm925_setup
471
472 /*
473 * R
474 * .RVI ZFRS BLDP WCAM
475 * .011 0001 ..11 1101
476 *
477 */
478 .type arm925_crval, #object
479arm925_crval:
480 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
481
482 __INITDATA
483 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
484 define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
485
486 .section ".rodata"
487
488 string cpu_arch_name, "armv4t"
489 string cpu_elf_name, "v4"
490 string cpu_arm925_name, "ARM925T"
491
492 .align
493
494 .section ".proc.info.init", #alloc
495
496.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
497 .type __\name\()_proc_info,#object
498__\name\()_proc_info:
499 .long \cpu_val
500 .long \cpu_mask
501 .long PMD_TYPE_SECT | \
502 PMD_SECT_CACHEABLE | \
503 PMD_BIT4 | \
504 PMD_SECT_AP_WRITE | \
505 PMD_SECT_AP_READ
506 .long PMD_TYPE_SECT | \
507 PMD_BIT4 | \
508 PMD_SECT_AP_WRITE | \
509 PMD_SECT_AP_READ
510 initfn __arm925_setup, __\name\()_proc_info
511 .long cpu_arch_name
512 .long cpu_elf_name
513 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
514 .long cpu_arm925_name
515 .long arm925_processor_functions
516 .long v4wbi_tlb_fns
517 .long v4wb_user_fns
518 .long arm925_cache_fns
519 .size __\name\()_proc_info, . - __\name\()_proc_info
520.endm
521
522 arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
523 arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name