Loading...
Note: File does not exist in v3.1.
1/*
2 * arch/arm/include/asm/arch_gicv3.h
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __ASM_ARCH_GICV3_H
19#define __ASM_ARCH_GICV3_H
20
21#ifndef __ASSEMBLY__
22
23#include <linux/io.h>
24#include <asm/barrier.h>
25#include <asm/cacheflush.h>
26#include <asm/cp15.h>
27
28#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
29#define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
30#define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
31#define ICC_SGI1R __ACCESS_CP15_64(0, c12)
32#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
33#define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
34#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
35#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
36#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
37
38#define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
39#define ICC_AP0R0 __ICC_AP0Rx(0)
40#define ICC_AP0R1 __ICC_AP0Rx(1)
41#define ICC_AP0R2 __ICC_AP0Rx(2)
42#define ICC_AP0R3 __ICC_AP0Rx(3)
43
44#define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
45#define ICC_AP1R0 __ICC_AP1Rx(0)
46#define ICC_AP1R1 __ICC_AP1Rx(1)
47#define ICC_AP1R2 __ICC_AP1Rx(2)
48#define ICC_AP1R3 __ICC_AP1Rx(3)
49
50#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
51
52#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
53#define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
54#define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
55#define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
56#define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
57#define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5)
58#define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
59
60#define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
61#define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
62
63#define ICH_LR0 __LR0(0)
64#define ICH_LR1 __LR0(1)
65#define ICH_LR2 __LR0(2)
66#define ICH_LR3 __LR0(3)
67#define ICH_LR4 __LR0(4)
68#define ICH_LR5 __LR0(5)
69#define ICH_LR6 __LR0(6)
70#define ICH_LR7 __LR0(7)
71#define ICH_LR8 __LR8(0)
72#define ICH_LR9 __LR8(1)
73#define ICH_LR10 __LR8(2)
74#define ICH_LR11 __LR8(3)
75#define ICH_LR12 __LR8(4)
76#define ICH_LR13 __LR8(5)
77#define ICH_LR14 __LR8(6)
78#define ICH_LR15 __LR8(7)
79
80/* LR top half */
81#define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
82#define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
83
84#define ICH_LRC0 __LRC0(0)
85#define ICH_LRC1 __LRC0(1)
86#define ICH_LRC2 __LRC0(2)
87#define ICH_LRC3 __LRC0(3)
88#define ICH_LRC4 __LRC0(4)
89#define ICH_LRC5 __LRC0(5)
90#define ICH_LRC6 __LRC0(6)
91#define ICH_LRC7 __LRC0(7)
92#define ICH_LRC8 __LRC8(0)
93#define ICH_LRC9 __LRC8(1)
94#define ICH_LRC10 __LRC8(2)
95#define ICH_LRC11 __LRC8(3)
96#define ICH_LRC12 __LRC8(4)
97#define ICH_LRC13 __LRC8(5)
98#define ICH_LRC14 __LRC8(6)
99#define ICH_LRC15 __LRC8(7)
100
101#define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
102#define ICH_AP0R0 __ICH_AP0Rx(0)
103#define ICH_AP0R1 __ICH_AP0Rx(1)
104#define ICH_AP0R2 __ICH_AP0Rx(2)
105#define ICH_AP0R3 __ICH_AP0Rx(3)
106
107#define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
108#define ICH_AP1R0 __ICH_AP1Rx(0)
109#define ICH_AP1R1 __ICH_AP1Rx(1)
110#define ICH_AP1R2 __ICH_AP1Rx(2)
111#define ICH_AP1R3 __ICH_AP1Rx(3)
112
113/* A32-to-A64 mappings used by VGIC save/restore */
114
115#define CPUIF_MAP(a32, a64) \
116static inline void write_ ## a64(u32 val) \
117{ \
118 write_sysreg(val, a32); \
119} \
120static inline u32 read_ ## a64(void) \
121{ \
122 return read_sysreg(a32); \
123} \
124
125#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
126static inline void write_ ## a64(u64 val) \
127{ \
128 write_sysreg(lower_32_bits(val), a32lo);\
129 write_sysreg(upper_32_bits(val), a32hi);\
130} \
131static inline u64 read_ ## a64(void) \
132{ \
133 u64 val = read_sysreg(a32lo); \
134 \
135 val |= (u64)read_sysreg(a32hi) << 32; \
136 \
137 return val; \
138}
139
140CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
141CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
142CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
143CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
144CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
145CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
146CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
147CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
148CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
149
150CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
151CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
152CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
153CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
154CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
155CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
156CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
157CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
158CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
159CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
160CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
161CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
162CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
163CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
164CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
165CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
166
167CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
168CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
169CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
170CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
171CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
172CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
173CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
174CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
175CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
176CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
177CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
178CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
179CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
180CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
181CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
182CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
183
184#define read_gicreg(r) read_##r()
185#define write_gicreg(v, r) write_##r(v)
186
187/* Low-level accessors */
188
189static inline void gic_write_eoir(u32 irq)
190{
191 write_sysreg(irq, ICC_EOIR1);
192 isb();
193}
194
195static inline void gic_write_dir(u32 val)
196{
197 write_sysreg(val, ICC_DIR);
198 isb();
199}
200
201static inline u32 gic_read_iar(void)
202{
203 u32 irqstat = read_sysreg(ICC_IAR1);
204
205 dsb(sy);
206
207 return irqstat;
208}
209
210static inline void gic_write_ctlr(u32 val)
211{
212 write_sysreg(val, ICC_CTLR);
213 isb();
214}
215
216static inline u32 gic_read_ctlr(void)
217{
218 return read_sysreg(ICC_CTLR);
219}
220
221static inline void gic_write_grpen1(u32 val)
222{
223 write_sysreg(val, ICC_IGRPEN1);
224 isb();
225}
226
227static inline void gic_write_sgi1r(u64 val)
228{
229 write_sysreg(val, ICC_SGI1R);
230}
231
232static inline u32 gic_read_sre(void)
233{
234 return read_sysreg(ICC_SRE);
235}
236
237static inline void gic_write_sre(u32 val)
238{
239 write_sysreg(val, ICC_SRE);
240 isb();
241}
242
243static inline void gic_write_bpr1(u32 val)
244{
245 write_sysreg(val, ICC_BPR1);
246}
247
248/*
249 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
250 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
251 * make much sense.
252 * Moreover, 64bit I/O emulation is extremely difficult to implement on
253 * AArch32, since the syndrome register doesn't provide any information for
254 * them.
255 * Consequently, the following IO helpers use 32bit accesses.
256 */
257static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
258{
259 writel_relaxed((u32)val, addr);
260 writel_relaxed((u32)(val >> 32), addr + 4);
261}
262
263static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
264{
265 u64 val;
266
267 val = readl_relaxed(addr);
268 val |= (u64)readl_relaxed(addr + 4) << 32;
269 return val;
270}
271
272#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
273
274/*
275 * GICD_IROUTERn, contain the affinity values associated to each interrupt.
276 * The upper-word (aff3) will always be 0, so there is no need for a lock.
277 */
278#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
279
280/*
281 * GICR_TYPER is an ID register and doesn't need atomicity.
282 */
283#define gic_read_typer(c) __gic_readq_nonatomic(c)
284
285/*
286 * GITS_BASER - hi and lo bits may be accessed independently.
287 */
288#define gits_read_baser(c) __gic_readq_nonatomic(c)
289#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
290
291/*
292 * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
293 * won't be being used during any updates and can be changed non-atomically
294 */
295#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
296#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
297#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
298#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
299
300/*
301 * GICR_xLPIR - only the lower bits are significant
302 */
303#define gic_read_lpir(c) readl_relaxed(c)
304#define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c)
305
306/*
307 * GITS_TYPER is an ID register and doesn't need atomicity.
308 */
309#define gits_read_typer(c) __gic_readq_nonatomic(c)
310
311/*
312 * GITS_CBASER - hi and lo bits may be accessed independently.
313 */
314#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
315#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
316
317/*
318 * GITS_CWRITER - hi and lo bits may be accessed independently.
319 */
320#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
321
322/*
323 * GITS_VPROPBASER - hi and lo bits may be accessed independently.
324 */
325#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
326
327/*
328 * GITS_VPENDBASER - the Valid bit must be cleared before changing
329 * anything else.
330 */
331static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
332{
333 u32 tmp;
334
335 tmp = readl_relaxed(addr + 4);
336 if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
337 tmp &= ~(GICR_VPENDBASER_Valid >> 32);
338 writel_relaxed(tmp, addr + 4);
339 }
340
341 /*
342 * Use the fact that __gic_writeq_nonatomic writes the second
343 * half of the 64bit quantity after the first.
344 */
345 __gic_writeq_nonatomic(val, addr);
346}
347
348#define gits_read_vpendbaser(c) __gic_readq_nonatomic(c)
349
350#endif /* !__ASSEMBLY__ */
351#endif /* !__ASM_ARCH_GICV3_H */