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1/*
2 * Copyright (c) 2007 Ben Dooks
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 *
7 * PWM driver for Samsung SoCs
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/export.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/time.h>
27
28/* For struct samsung_timer_variant and samsung_pwm_lock. */
29#include <clocksource/samsung_pwm.h>
30
31#define REG_TCFG0 0x00
32#define REG_TCFG1 0x04
33#define REG_TCON 0x08
34
35#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
36#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
37
38#define TCFG0_PRESCALER_MASK 0xff
39#define TCFG0_PRESCALER1_SHIFT 8
40
41#define TCFG1_MUX_MASK 0xf
42#define TCFG1_SHIFT(chan) (4 * (chan))
43
44/*
45 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
46 * bits (one channel) after channel 0, so channels have different numbering
47 * when accessing TCON register. See to_tcon_channel() function.
48 *
49 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
50 * in its set of bits is 2 as opposed to 3 for other channels.
51 */
52#define TCON_START(chan) BIT(4 * (chan) + 0)
53#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
54#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
55#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
56#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
57#define TCON_AUTORELOAD(chan) \
58 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
59
60/**
61 * struct samsung_pwm_channel - private data of PWM channel
62 * @period_ns: current period in nanoseconds programmed to the hardware
63 * @duty_ns: current duty time in nanoseconds programmed to the hardware
64 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
65 */
66struct samsung_pwm_channel {
67 u32 period_ns;
68 u32 duty_ns;
69 u32 tin_ns;
70};
71
72/**
73 * struct samsung_pwm_chip - private data of PWM chip
74 * @chip: generic PWM chip
75 * @variant: local copy of hardware variant data
76 * @inverter_mask: inverter status for all channels - one bit per channel
77 * @base: base address of mapped PWM registers
78 * @base_clk: base clock used to drive the timers
79 * @tclk0: external clock 0 (can be ERR_PTR if not present)
80 * @tclk1: external clock 1 (can be ERR_PTR if not present)
81 */
82struct samsung_pwm_chip {
83 struct pwm_chip chip;
84 struct samsung_pwm_variant variant;
85 u8 inverter_mask;
86
87 void __iomem *base;
88 struct clk *base_clk;
89 struct clk *tclk0;
90 struct clk *tclk1;
91};
92
93#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
94/*
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
96 * and some registers need access synchronization. If both drivers are
97 * compiled in, the spinlock is defined in the clocksource driver,
98 * otherwise following definition is used.
99 *
100 * Currently we do not need any more complex synchronization method
101 * because all the supported SoCs contain only one instance of the PWM
102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.
104 */
105static DEFINE_SPINLOCK(samsung_pwm_lock);
106#endif
107
108static inline
109struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
110{
111 return container_of(chip, struct samsung_pwm_chip, chip);
112}
113
114static inline unsigned int to_tcon_channel(unsigned int channel)
115{
116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
117 return (channel == 0) ? 0 : (channel + 1);
118}
119
120static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
121 unsigned int channel, u8 divisor)
122{
123 u8 shift = TCFG1_SHIFT(channel);
124 unsigned long flags;
125 u32 reg;
126 u8 bits;
127
128 bits = (fls(divisor) - 1) - pwm->variant.div_base;
129
130 spin_lock_irqsave(&samsung_pwm_lock, flags);
131
132 reg = readl(pwm->base + REG_TCFG1);
133 reg &= ~(TCFG1_MUX_MASK << shift);
134 reg |= bits << shift;
135 writel(reg, pwm->base + REG_TCFG1);
136
137 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
138}
139
140static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
141{
142 struct samsung_pwm_variant *variant = &chip->variant;
143 u32 reg;
144
145 reg = readl(chip->base + REG_TCFG1);
146 reg >>= TCFG1_SHIFT(chan);
147 reg &= TCFG1_MUX_MASK;
148
149 return (BIT(reg) & variant->tclk_mask) == 0;
150}
151
152static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
153 unsigned int chan)
154{
155 unsigned long rate;
156 u32 reg;
157
158 rate = clk_get_rate(chip->base_clk);
159
160 reg = readl(chip->base + REG_TCFG0);
161 if (chan >= 2)
162 reg >>= TCFG0_PRESCALER1_SHIFT;
163 reg &= TCFG0_PRESCALER_MASK;
164
165 return rate / (reg + 1);
166}
167
168static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
169 unsigned int chan, unsigned long freq)
170{
171 struct samsung_pwm_variant *variant = &chip->variant;
172 unsigned long rate;
173 struct clk *clk;
174 u8 div;
175
176 if (!pwm_samsung_is_tdiv(chip, chan)) {
177 clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
178 if (!IS_ERR(clk)) {
179 rate = clk_get_rate(clk);
180 if (rate)
181 return rate;
182 }
183
184 dev_warn(chip->chip.dev,
185 "tclk of PWM %d is inoperational, using tdiv\n", chan);
186 }
187
188 rate = pwm_samsung_get_tin_rate(chip, chan);
189 dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
190
191 /*
192 * Compare minimum PWM frequency that can be achieved with possible
193 * divider settings and choose the lowest divisor that can generate
194 * frequencies lower than requested.
195 */
196 if (variant->bits < 32) {
197 /* Only for s3c24xx */
198 for (div = variant->div_base; div < 4; ++div)
199 if ((rate >> (variant->bits + div)) < freq)
200 break;
201 } else {
202 /*
203 * Other variants have enough counter bits to generate any
204 * requested rate, so no need to check higher divisors.
205 */
206 div = variant->div_base;
207 }
208
209 pwm_samsung_set_divisor(chip, chan, BIT(div));
210
211 return rate >> div;
212}
213
214static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
215{
216 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
217 struct samsung_pwm_channel *our_chan;
218
219 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
220 dev_warn(chip->dev,
221 "tried to request PWM channel %d without output\n",
222 pwm->hwpwm);
223 return -EINVAL;
224 }
225
226 our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
227 if (!our_chan)
228 return -ENOMEM;
229
230 pwm_set_chip_data(pwm, our_chan);
231
232 return 0;
233}
234
235static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
236{
237 devm_kfree(chip->dev, pwm_get_chip_data(pwm));
238 pwm_set_chip_data(pwm, NULL);
239}
240
241static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
242{
243 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
244 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
245 unsigned long flags;
246 u32 tcon;
247
248 spin_lock_irqsave(&samsung_pwm_lock, flags);
249
250 tcon = readl(our_chip->base + REG_TCON);
251
252 tcon &= ~TCON_START(tcon_chan);
253 tcon |= TCON_MANUALUPDATE(tcon_chan);
254 writel(tcon, our_chip->base + REG_TCON);
255
256 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
257 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
258 writel(tcon, our_chip->base + REG_TCON);
259
260 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
261
262 return 0;
263}
264
265static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
266{
267 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
268 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
269 unsigned long flags;
270 u32 tcon;
271
272 spin_lock_irqsave(&samsung_pwm_lock, flags);
273
274 tcon = readl(our_chip->base + REG_TCON);
275 tcon &= ~TCON_AUTORELOAD(tcon_chan);
276 writel(tcon, our_chip->base + REG_TCON);
277
278 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
279}
280
281static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
282 struct pwm_device *pwm)
283{
284 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
285 u32 tcon;
286 unsigned long flags;
287
288 spin_lock_irqsave(&samsung_pwm_lock, flags);
289
290 tcon = readl(chip->base + REG_TCON);
291 tcon |= TCON_MANUALUPDATE(tcon_chan);
292 writel(tcon, chip->base + REG_TCON);
293
294 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
295 writel(tcon, chip->base + REG_TCON);
296
297 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
298}
299
300static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
301 int duty_ns, int period_ns)
302{
303 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
304 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
305 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
306
307 /*
308 * We currently avoid using 64bit arithmetic by using the
309 * fact that anything faster than 1Hz is easily representable
310 * by 32bits.
311 */
312 if (period_ns > NSEC_PER_SEC)
313 return -ERANGE;
314
315 if (period_ns == chan->period_ns && duty_ns == chan->duty_ns)
316 return 0;
317
318 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
319 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
320
321 /* We need tick count for calculation, not last tick. */
322 ++tcnt;
323
324 /* Check to see if we are changing the clock rate of the PWM. */
325 if (chan->period_ns != period_ns) {
326 unsigned long tin_rate;
327 u32 period;
328
329 period = NSEC_PER_SEC / period_ns;
330
331 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
332 duty_ns, period_ns, period);
333
334 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
335
336 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
337
338 tin_ns = NSEC_PER_SEC / tin_rate;
339 tcnt = period_ns / tin_ns;
340 }
341
342 /* Period is too short. */
343 if (tcnt <= 1)
344 return -ERANGE;
345
346 /* Note that counters count down. */
347 tcmp = duty_ns / tin_ns;
348
349 /* 0% duty is not available */
350 if (!tcmp)
351 ++tcmp;
352
353 tcmp = tcnt - tcmp;
354
355 /* Decrement to get tick numbers, instead of tick counts. */
356 --tcnt;
357 /* -1UL will give 100% duty. */
358 --tcmp;
359
360 dev_dbg(our_chip->chip.dev,
361 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
362
363 /* Update PWM registers. */
364 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
365 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
366
367 /*
368 * In case the PWM is currently at 100% duty cycle, force a manual
369 * update to prevent the signal staying high if the PWM is disabled
370 * shortly afer this update (before it autoreloaded the new values).
371 */
372 if (oldtcmp == (u32) -1) {
373 dev_dbg(our_chip->chip.dev, "Forcing manual update");
374 pwm_samsung_manual_update(our_chip, pwm);
375 }
376
377 chan->period_ns = period_ns;
378 chan->tin_ns = tin_ns;
379 chan->duty_ns = duty_ns;
380
381 return 0;
382}
383
384static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
385 unsigned int channel, bool invert)
386{
387 unsigned int tcon_chan = to_tcon_channel(channel);
388 unsigned long flags;
389 u32 tcon;
390
391 spin_lock_irqsave(&samsung_pwm_lock, flags);
392
393 tcon = readl(chip->base + REG_TCON);
394
395 if (invert) {
396 chip->inverter_mask |= BIT(channel);
397 tcon |= TCON_INVERT(tcon_chan);
398 } else {
399 chip->inverter_mask &= ~BIT(channel);
400 tcon &= ~TCON_INVERT(tcon_chan);
401 }
402
403 writel(tcon, chip->base + REG_TCON);
404
405 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
406}
407
408static int pwm_samsung_set_polarity(struct pwm_chip *chip,
409 struct pwm_device *pwm,
410 enum pwm_polarity polarity)
411{
412 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
413 bool invert = (polarity == PWM_POLARITY_NORMAL);
414
415 /* Inverted means normal in the hardware. */
416 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
417
418 return 0;
419}
420
421static const struct pwm_ops pwm_samsung_ops = {
422 .request = pwm_samsung_request,
423 .free = pwm_samsung_free,
424 .enable = pwm_samsung_enable,
425 .disable = pwm_samsung_disable,
426 .config = pwm_samsung_config,
427 .set_polarity = pwm_samsung_set_polarity,
428 .owner = THIS_MODULE,
429};
430
431#ifdef CONFIG_OF
432static const struct samsung_pwm_variant s3c24xx_variant = {
433 .bits = 16,
434 .div_base = 1,
435 .has_tint_cstat = false,
436 .tclk_mask = BIT(4),
437};
438
439static const struct samsung_pwm_variant s3c64xx_variant = {
440 .bits = 32,
441 .div_base = 0,
442 .has_tint_cstat = true,
443 .tclk_mask = BIT(7) | BIT(6) | BIT(5),
444};
445
446static const struct samsung_pwm_variant s5p64x0_variant = {
447 .bits = 32,
448 .div_base = 0,
449 .has_tint_cstat = true,
450 .tclk_mask = 0,
451};
452
453static const struct samsung_pwm_variant s5pc100_variant = {
454 .bits = 32,
455 .div_base = 0,
456 .has_tint_cstat = true,
457 .tclk_mask = BIT(5),
458};
459
460static const struct of_device_id samsung_pwm_matches[] = {
461 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
462 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
463 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
464 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
465 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
466 {},
467};
468MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
469
470static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
471{
472 struct device_node *np = chip->chip.dev->of_node;
473 const struct of_device_id *match;
474 struct property *prop;
475 const __be32 *cur;
476 u32 val;
477
478 match = of_match_node(samsung_pwm_matches, np);
479 if (!match)
480 return -ENODEV;
481
482 memcpy(&chip->variant, match->data, sizeof(chip->variant));
483
484 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
485 if (val >= SAMSUNG_PWM_NUM) {
486 dev_err(chip->chip.dev,
487 "%s: invalid channel index in samsung,pwm-outputs property\n",
488 __func__);
489 continue;
490 }
491 chip->variant.output_mask |= BIT(val);
492 }
493
494 return 0;
495}
496#else
497static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
498{
499 return -ENODEV;
500}
501#endif
502
503static int pwm_samsung_probe(struct platform_device *pdev)
504{
505 struct device *dev = &pdev->dev;
506 struct samsung_pwm_chip *chip;
507 struct resource *res;
508 unsigned int chan;
509 int ret;
510
511 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
512 if (chip == NULL)
513 return -ENOMEM;
514
515 chip->chip.dev = &pdev->dev;
516 chip->chip.ops = &pwm_samsung_ops;
517 chip->chip.base = -1;
518 chip->chip.npwm = SAMSUNG_PWM_NUM;
519 chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
520
521 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
522 ret = pwm_samsung_parse_dt(chip);
523 if (ret)
524 return ret;
525
526 chip->chip.of_xlate = of_pwm_xlate_with_flags;
527 chip->chip.of_pwm_n_cells = 3;
528 } else {
529 if (!pdev->dev.platform_data) {
530 dev_err(&pdev->dev, "no platform data specified\n");
531 return -EINVAL;
532 }
533
534 memcpy(&chip->variant, pdev->dev.platform_data,
535 sizeof(chip->variant));
536 }
537
538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
539 chip->base = devm_ioremap_resource(&pdev->dev, res);
540 if (IS_ERR(chip->base))
541 return PTR_ERR(chip->base);
542
543 chip->base_clk = devm_clk_get(&pdev->dev, "timers");
544 if (IS_ERR(chip->base_clk)) {
545 dev_err(dev, "failed to get timer base clk\n");
546 return PTR_ERR(chip->base_clk);
547 }
548
549 ret = clk_prepare_enable(chip->base_clk);
550 if (ret < 0) {
551 dev_err(dev, "failed to enable base clock\n");
552 return ret;
553 }
554
555 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
556 if (chip->variant.output_mask & BIT(chan))
557 pwm_samsung_set_invert(chip, chan, true);
558
559 /* Following clocks are optional. */
560 chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
561 chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
562
563 platform_set_drvdata(pdev, chip);
564
565 ret = pwmchip_add(&chip->chip);
566 if (ret < 0) {
567 dev_err(dev, "failed to register PWM chip\n");
568 clk_disable_unprepare(chip->base_clk);
569 return ret;
570 }
571
572 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
573 clk_get_rate(chip->base_clk),
574 !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
575 !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
576
577 return 0;
578}
579
580static int pwm_samsung_remove(struct platform_device *pdev)
581{
582 struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
583 int ret;
584
585 ret = pwmchip_remove(&chip->chip);
586 if (ret < 0)
587 return ret;
588
589 clk_disable_unprepare(chip->base_clk);
590
591 return 0;
592}
593
594#ifdef CONFIG_PM_SLEEP
595static int pwm_samsung_suspend(struct device *dev)
596{
597 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
598 unsigned int i;
599
600 /*
601 * No one preserves these values during suspend so reset them.
602 * Otherwise driver leaves PWM unconfigured if same values are
603 * passed to pwm_config() next time.
604 */
605 for (i = 0; i < SAMSUNG_PWM_NUM; ++i) {
606 struct pwm_device *pwm = &chip->chip.pwms[i];
607 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
608
609 if (!chan)
610 continue;
611
612 chan->period_ns = 0;
613 chan->duty_ns = 0;
614 }
615
616 return 0;
617}
618
619static int pwm_samsung_resume(struct device *dev)
620{
621 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
622 unsigned int chan;
623
624 /*
625 * Inverter setting must be preserved across suspend/resume
626 * as nobody really seems to configure it more than once.
627 */
628 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) {
629 if (chip->variant.output_mask & BIT(chan))
630 pwm_samsung_set_invert(chip, chan,
631 chip->inverter_mask & BIT(chan));
632 }
633
634 return 0;
635}
636#endif
637
638static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, pwm_samsung_suspend,
639 pwm_samsung_resume);
640
641static struct platform_driver pwm_samsung_driver = {
642 .driver = {
643 .name = "samsung-pwm",
644 .pm = &pwm_samsung_pm_ops,
645 .of_match_table = of_match_ptr(samsung_pwm_matches),
646 },
647 .probe = pwm_samsung_probe,
648 .remove = pwm_samsung_remove,
649};
650module_platform_driver(pwm_samsung_driver);
651
652MODULE_LICENSE("GPL");
653MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
654MODULE_ALIAS("platform:samsung-pwm");