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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
28 *
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#ifndef __iwl_csr_h__
67#define __iwl_csr_h__
68/*
69 * CSR (control and status registers)
70 *
71 * CSR registers are mapped directly into PCI bus space, and are accessible
72 * whenever platform supplies power to device, even when device is in
73 * low power states due to driver-invoked device resets
74 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
75 *
76 * Use iwl_write32() and iwl_read32() family to access these registers;
77 * these provide simple PCI bus access, without waking up the MAC.
78 * Do not use iwl_write_direct32() family for these registers;
79 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
80 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
81 * the CSR registers.
82 *
83 * NOTE: Device does need to be awake in order to read this memory
84 * via CSR_EEPROM and CSR_OTP registers
85 */
86#define CSR_BASE (0x000)
87
88#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
89#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
90#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
91#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
92#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
93#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
94#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
95#define CSR_GP_CNTRL (CSR_BASE+0x024)
96
97/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
98#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
99
100/*
101 * Hardware revision info
102 * Bit fields:
103 * 31-16: Reserved
104 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
105 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
106 * 1-0: "Dash" (-) value, as in A-1, etc.
107 */
108#define CSR_HW_REV (CSR_BASE+0x028)
109
110/*
111 * RF ID revision info
112 * Bit fields:
113 * 31:24: Reserved (set to 0x0)
114 * 23:12: Type
115 * 11:8: Step (A - 0x0, B - 0x1, etc)
116 * 7:4: Dash
117 * 3:0: Flavor
118 */
119#define CSR_HW_RF_ID (CSR_BASE+0x09c)
120
121/*
122 * EEPROM and OTP (one-time-programmable) memory reads
123 *
124 * NOTE: Device must be awake, initialized via apm_ops.init(),
125 * in order to read.
126 */
127#define CSR_EEPROM_REG (CSR_BASE+0x02c)
128#define CSR_EEPROM_GP (CSR_BASE+0x030)
129#define CSR_OTP_GP_REG (CSR_BASE+0x034)
130
131#define CSR_GIO_REG (CSR_BASE+0x03C)
132#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
133#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
134
135/*
136 * UCODE-DRIVER GP (general purpose) mailbox registers.
137 * SET/CLR registers set/clear bit(s) if "1" is written.
138 */
139#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
140#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
141#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
142#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
143
144#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
145
146#define CSR_LED_REG (CSR_BASE+0x094)
147#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
148#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
149#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
150#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
151#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
152
153/* GIO Chicken Bits (PCI Express bus link power management) */
154#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
155
156/* Analog phase-lock-loop configuration */
157#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
158
159/*
160 * CSR HW resources monitor registers
161 */
162#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
163#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
164#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
165
166/*
167 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
168 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
169 * See also CSR_HW_REV register.
170 * Bit fields:
171 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
172 * 1-0: "Dash" (-) value, as in C-1, etc.
173 */
174#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
175
176#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
177#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
178
179/* Bits for CSR_HW_IF_CONFIG_REG */
180#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
181#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
182#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
183#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
184#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
185#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
186#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
187#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
188
189#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
190#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
191#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
192#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
193#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
194#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
195
196#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
197#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
198#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
199#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
200#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
201#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
202#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
203
204#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
205
206#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
207#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
208
209/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
210 * acknowledged (reset) by host writing "1" to flagged bits. */
211#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
212#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
213#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
214#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
215#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
216#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
217#define CSR_INT_BIT_PAGING (1 << 24) /* SDIO PAGING */
218#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
219#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
220#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
221#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
222#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
223
224#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
225 CSR_INT_BIT_HW_ERR | \
226 CSR_INT_BIT_FH_TX | \
227 CSR_INT_BIT_SW_ERR | \
228 CSR_INT_BIT_PAGING | \
229 CSR_INT_BIT_RF_KILL | \
230 CSR_INT_BIT_SW_RX | \
231 CSR_INT_BIT_WAKEUP | \
232 CSR_INT_BIT_ALIVE | \
233 CSR_INT_BIT_RX_PERIODIC)
234
235/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
236#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
237#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
238#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
239#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
240#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
241#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
242
243#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
244 CSR_FH_INT_BIT_RX_CHNL1 | \
245 CSR_FH_INT_BIT_RX_CHNL0)
246
247#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
248 CSR_FH_INT_BIT_TX_CHNL0)
249
250/* GPIO */
251#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
252#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
253#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
254
255/* RESET */
256#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
257#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
258#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
259#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
260#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
261#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
262
263/*
264 * GP (general purpose) CONTROL REGISTER
265 * Bit fields:
266 * 27: HW_RF_KILL_SW
267 * Indicates state of (platform's) hardware RF-Kill switch
268 * 26-24: POWER_SAVE_TYPE
269 * Indicates current power-saving mode:
270 * 000 -- No power saving
271 * 001 -- MAC power-down
272 * 010 -- PHY (radio) power-down
273 * 011 -- Error
274 * 10: XTAL ON request
275 * 9-6: SYS_CONFIG
276 * Indicates current system configuration, reflecting pins on chip
277 * as forced high/low by device circuit board.
278 * 4: GOING_TO_SLEEP
279 * Indicates MAC is entering a power-saving sleep power-down.
280 * Not a good time to access device-internal resources.
281 * 3: MAC_ACCESS_REQ
282 * Host sets this to request and maintain MAC wakeup, to allow host
283 * access to device-internal resources. Host must wait for
284 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
285 * device registers.
286 * 2: INIT_DONE
287 * Host sets this to put device into fully operational D0 power mode.
288 * Host resets this after SW_RESET to put device into low power mode.
289 * 0: MAC_CLOCK_READY
290 * Indicates MAC (ucode processor, etc.) is powered up and can run.
291 * Internal resources are accessible.
292 * NOTE: This does not indicate that the processor is actually running.
293 * NOTE: This does not indicate that device has completed
294 * init or post-power-down restore of internal SRAM memory.
295 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
296 * SRAM is restored and uCode is in normal operation mode.
297 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
298 * do not need to save/restore it.
299 * NOTE: After device reset, this bit remains "0" until host sets
300 * INIT_DONE
301 */
302#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
303#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
304#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
305#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
306#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
307
308#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
309
310#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
311#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
312#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
313
314
315/* HW REV */
316#define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
317#define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
318
319
320/**
321 * hw_rev values
322 */
323enum {
324 SILICON_A_STEP = 0,
325 SILICON_B_STEP,
326 SILICON_C_STEP,
327};
328
329
330#define CSR_HW_REV_TYPE_MSK (0x000FFF0)
331#define CSR_HW_REV_TYPE_5300 (0x0000020)
332#define CSR_HW_REV_TYPE_5350 (0x0000030)
333#define CSR_HW_REV_TYPE_5100 (0x0000050)
334#define CSR_HW_REV_TYPE_5150 (0x0000040)
335#define CSR_HW_REV_TYPE_1000 (0x0000060)
336#define CSR_HW_REV_TYPE_6x00 (0x0000070)
337#define CSR_HW_REV_TYPE_6x50 (0x0000080)
338#define CSR_HW_REV_TYPE_6150 (0x0000084)
339#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
340#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
341#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
342#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
343#define CSR_HW_REV_TYPE_2x00 (0x0000100)
344#define CSR_HW_REV_TYPE_105 (0x0000110)
345#define CSR_HW_REV_TYPE_135 (0x0000120)
346#define CSR_HW_REV_TYPE_7265D (0x0000210)
347#define CSR_HW_REV_TYPE_NONE (0x00001F0)
348
349/* RF_ID value */
350#define CSR_HW_RF_ID_TYPE_JF (0x00105000)
351#define CSR_HW_RF_ID_TYPE_LC (0x00101000)
352
353/* EEPROM REG */
354#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
355#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
356#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
357#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
358
359/* EEPROM GP */
360#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
361#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
362#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
363#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
364#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
365#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
366
367/* One-time-programmable memory general purpose reg */
368#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
369#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
370#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
371#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
372
373/* GP REG */
374#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
375#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
376#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
377#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
378#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
379
380
381/* CSR GIO */
382#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
383
384/*
385 * UCODE-DRIVER GP (general purpose) mailbox register 1
386 * Host driver and uCode write and/or read this register to communicate with
387 * each other.
388 * Bit fields:
389 * 4: UCODE_DISABLE
390 * Host sets this to request permanent halt of uCode, same as
391 * sending CARD_STATE command with "halt" bit set.
392 * 3: CT_KILL_EXIT
393 * Host sets this to request exit from CT_KILL state, i.e. host thinks
394 * device temperature is low enough to continue normal operation.
395 * 2: CMD_BLOCKED
396 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
397 * to release uCode to clear all Tx and command queues, enter
398 * unassociated mode, and power down.
399 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
400 * 1: SW_BIT_RFKILL
401 * Host sets this when issuing CARD_STATE command to request
402 * device sleep.
403 * 0: MAC_SLEEP
404 * uCode sets this when preparing a power-saving power-down.
405 * uCode resets this when power-up is complete and SRAM is sane.
406 * NOTE: device saves internal SRAM data to host when powering down,
407 * and must restore this data after powering back up.
408 * MAC_SLEEP is the best indication that restore is complete.
409 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
410 * do not need to save/restore it.
411 */
412#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
413#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
414#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
415#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
416#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
417
418/* GP Driver */
419#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
420#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
421#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
422#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
423#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
424#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
425
426#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
427
428/* GIO Chicken Bits (PCI Express bus link power management) */
429#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
430#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
431
432/* LED */
433#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
434#define CSR_LED_REG_TURN_ON (0x60)
435#define CSR_LED_REG_TURN_OFF (0x20)
436
437/* ANA_PLL */
438#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
439
440/* HPET MEM debug */
441#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
442
443/* DRAM INT TABLE */
444#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
445#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
446#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
447
448/*
449 * SHR target access (Shared block memory space)
450 *
451 * Shared internal registers can be accessed directly from PCI bus through SHR
452 * arbiter without need for the MAC HW to be powered up. This is possible due to
453 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
454 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
455 *
456 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
457 * need not be powered up so no "grab inc access" is required.
458 */
459
460/*
461 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
462 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
463 * first, write to the control register:
464 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
465 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
466 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
467 *
468 * To write the register, first, write to the data register
469 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
470 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
471 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
472 */
473#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
474#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
475
476/*
477 * HBUS (Host-side Bus)
478 *
479 * HBUS registers are mapped directly into PCI bus space, but are used
480 * to indirectly access device's internal memory or registers that
481 * may be powered-down.
482 *
483 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
484 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
485 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
486 * internal resources.
487 *
488 * Do not use iwl_write32()/iwl_read32() family to access these registers;
489 * these provide only simple PCI bus access, without waking up the MAC.
490 */
491#define HBUS_BASE (0x400)
492
493/*
494 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
495 * structures, error log, event log, verifying uCode load).
496 * First write to address register, then read from or write to data register
497 * to complete the job. Once the address register is set up, accesses to
498 * data registers auto-increment the address by one dword.
499 * Bit usage for address registers (read or write):
500 * 0-31: memory address within device
501 */
502#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
503#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
504#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
505#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
506
507/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
508#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
509#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
510
511/*
512 * Registers for accessing device's internal peripheral registers
513 * (e.g. SCD, BSM, etc.). First write to address register,
514 * then read from or write to data register to complete the job.
515 * Bit usage for address registers (read or write):
516 * 0-15: register address (offset) within device
517 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
518 */
519#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
520#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
521#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
522#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
523
524/* Used to enable DBGM */
525#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
526
527/*
528 * Per-Tx-queue write pointer (index, really!)
529 * Indicates index to next TFD that driver will fill (1 past latest filled).
530 * Bit usage:
531 * 0-7: queue write index
532 * 11-8: queue selector
533 */
534#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
535
536/**********************************************************
537 * CSR values
538 **********************************************************/
539 /*
540 * host interrupt timeout value
541 * used with setting interrupt coalescing timer
542 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
543 *
544 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
545 */
546#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
547#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
548#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
549#define IWL_HOST_INT_OPER_MODE BIT(31)
550
551/*****************************************************************************
552 * 7000/3000 series SHR DTS addresses *
553 *****************************************************************************/
554
555/* Diode Results Register Structure: */
556enum dtd_diode_reg {
557 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
558 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
559 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
560 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
561 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
562 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
563/* Those are the masks INSIDE the flags bit-field: */
564 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
565 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
566 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
567 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
568};
569
570/*****************************************************************************
571 * MSIX related registers *
572 *****************************************************************************/
573
574#define CSR_MSIX_BASE (0x2000)
575#define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
576#define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
577#define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
578#define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
579#define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
580#define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
581#define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
582#define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
583#define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
584#define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
585
586#define MSIX_FH_INT_CAUSES_Q(q) (q)
587
588/*
589 * Causes for the FH register interrupts
590 */
591enum msix_fh_int_causes {
592 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
593 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
594 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
595 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
596 MSIX_FH_INT_CAUSES_S2D = BIT(19),
597 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
598};
599
600/*
601 * Causes for the HW register interrupts
602 */
603enum msix_hw_int_causes {
604 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
605 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
606 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
607 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
608 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
609 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
610 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
611 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
612 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
613 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
614};
615
616#define MSIX_MIN_INTERRUPT_VECTORS 2
617#define MSIX_AUTO_CLEAR_CAUSE 0
618#define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
619
620/*****************************************************************************
621 * HW address related registers *
622 *****************************************************************************/
623
624#define CSR_ADDR_BASE (0x380)
625#define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
626#define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
627#define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
628#define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
629
630#endif /* !__iwl_csr_h__ */