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1/*
2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the names of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef _MLXSW_CMD_H
37#define _MLXSW_CMD_H
38
39#include "item.h"
40
41#define MLXSW_CMD_MBOX_SIZE 4096
42
43static inline char *mlxsw_cmd_mbox_alloc(void)
44{
45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL);
46}
47
48static inline void mlxsw_cmd_mbox_free(char *mbox)
49{
50 kfree(mbox);
51}
52
53static inline void mlxsw_cmd_mbox_zero(char *mbox)
54{
55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE);
56}
57
58struct mlxsw_core;
59
60int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod,
61 u32 in_mod, bool out_mbox_direct,
62 char *in_mbox, size_t in_mbox_size,
63 char *out_mbox, size_t out_mbox_size);
64
65static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode,
66 u8 opcode_mod, u32 in_mod, char *in_mbox,
67 size_t in_mbox_size)
68{
69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
70 in_mbox, in_mbox_size, NULL, 0);
71}
72
73static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode,
74 u8 opcode_mod, u32 in_mod,
75 bool out_mbox_direct,
76 char *out_mbox, size_t out_mbox_size)
77{
78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod,
79 out_mbox_direct, NULL, 0,
80 out_mbox, out_mbox_size);
81}
82
83static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode,
84 u8 opcode_mod, u32 in_mod)
85{
86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
87 NULL, 0, NULL, 0);
88}
89
90enum mlxsw_cmd_opcode {
91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004,
92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006,
93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003,
94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF,
95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE,
96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100,
97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040,
98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201,
99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202,
100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E,
101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022,
102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016,
103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017,
104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018,
105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013,
106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014,
107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015,
108 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101,
109};
110
111static inline const char *mlxsw_cmd_opcode_str(u16 opcode)
112{
113 switch (opcode) {
114 case MLXSW_CMD_OPCODE_QUERY_FW:
115 return "QUERY_FW";
116 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO:
117 return "QUERY_BOARDINFO";
118 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP:
119 return "QUERY_AQ_CAP";
120 case MLXSW_CMD_OPCODE_MAP_FA:
121 return "MAP_FA";
122 case MLXSW_CMD_OPCODE_UNMAP_FA:
123 return "UNMAP_FA";
124 case MLXSW_CMD_OPCODE_CONFIG_PROFILE:
125 return "CONFIG_PROFILE";
126 case MLXSW_CMD_OPCODE_ACCESS_REG:
127 return "ACCESS_REG";
128 case MLXSW_CMD_OPCODE_SW2HW_DQ:
129 return "SW2HW_DQ";
130 case MLXSW_CMD_OPCODE_HW2SW_DQ:
131 return "HW2SW_DQ";
132 case MLXSW_CMD_OPCODE_2ERR_DQ:
133 return "2ERR_DQ";
134 case MLXSW_CMD_OPCODE_QUERY_DQ:
135 return "QUERY_DQ";
136 case MLXSW_CMD_OPCODE_SW2HW_CQ:
137 return "SW2HW_CQ";
138 case MLXSW_CMD_OPCODE_HW2SW_CQ:
139 return "HW2SW_CQ";
140 case MLXSW_CMD_OPCODE_QUERY_CQ:
141 return "QUERY_CQ";
142 case MLXSW_CMD_OPCODE_SW2HW_EQ:
143 return "SW2HW_EQ";
144 case MLXSW_CMD_OPCODE_HW2SW_EQ:
145 return "HW2SW_EQ";
146 case MLXSW_CMD_OPCODE_QUERY_EQ:
147 return "QUERY_EQ";
148 case MLXSW_CMD_OPCODE_QUERY_RESOURCES:
149 return "QUERY_RESOURCES";
150 default:
151 return "*UNKNOWN*";
152 }
153}
154
155enum mlxsw_cmd_status {
156 /* Command execution succeeded. */
157 MLXSW_CMD_STATUS_OK = 0x00,
158 /* Internal error (e.g. bus error) occurred while processing command. */
159 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01,
160 /* Operation/command not supported or opcode modifier not supported. */
161 MLXSW_CMD_STATUS_BAD_OP = 0x02,
162 /* Parameter not supported, parameter out of range. */
163 MLXSW_CMD_STATUS_BAD_PARAM = 0x03,
164 /* System was not enabled or bad system state. */
165 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04,
166 /* Attempt to access reserved or unallocated resource, or resource in
167 * inappropriate ownership.
168 */
169 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05,
170 /* Requested resource is currently executing a command. */
171 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06,
172 /* Required capability exceeds device limits. */
173 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08,
174 /* Resource is not in the appropriate state or ownership. */
175 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09,
176 /* Index out of range (might be beyond table size or attempt to
177 * access a reserved resource).
178 */
179 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A,
180 /* NVMEM checksum/CRC failed. */
181 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B,
182 /* Bad management packet (silently discarded). */
183 MLXSW_CMD_STATUS_BAD_PKT = 0x30,
184};
185
186static inline const char *mlxsw_cmd_status_str(u8 status)
187{
188 switch (status) {
189 case MLXSW_CMD_STATUS_OK:
190 return "OK";
191 case MLXSW_CMD_STATUS_INTERNAL_ERR:
192 return "INTERNAL_ERR";
193 case MLXSW_CMD_STATUS_BAD_OP:
194 return "BAD_OP";
195 case MLXSW_CMD_STATUS_BAD_PARAM:
196 return "BAD_PARAM";
197 case MLXSW_CMD_STATUS_BAD_SYS_STATE:
198 return "BAD_SYS_STATE";
199 case MLXSW_CMD_STATUS_BAD_RESOURCE:
200 return "BAD_RESOURCE";
201 case MLXSW_CMD_STATUS_RESOURCE_BUSY:
202 return "RESOURCE_BUSY";
203 case MLXSW_CMD_STATUS_EXCEED_LIM:
204 return "EXCEED_LIM";
205 case MLXSW_CMD_STATUS_BAD_RES_STATE:
206 return "BAD_RES_STATE";
207 case MLXSW_CMD_STATUS_BAD_INDEX:
208 return "BAD_INDEX";
209 case MLXSW_CMD_STATUS_BAD_NVMEM:
210 return "BAD_NVMEM";
211 case MLXSW_CMD_STATUS_BAD_PKT:
212 return "BAD_PKT";
213 default:
214 return "*UNKNOWN*";
215 }
216}
217
218/* QUERY_FW - Query Firmware
219 * -------------------------
220 * OpMod == 0, INMmod == 0
221 * -----------------------
222 * The QUERY_FW command retrieves information related to firmware, command
223 * interface version and the amount of resources that should be allocated to
224 * the firmware.
225 */
226
227static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core,
228 char *out_mbox)
229{
230 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW,
231 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
232}
233
234/* cmd_mbox_query_fw_fw_pages
235 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages.
236 */
237MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
238
239/* cmd_mbox_query_fw_fw_rev_major
240 * Firmware Revision - Major
241 */
242MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
243
244/* cmd_mbox_query_fw_fw_rev_subminor
245 * Firmware Sub-minor version (Patch level)
246 */
247MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
248
249/* cmd_mbox_query_fw_fw_rev_minor
250 * Firmware Revision - Minor
251 */
252MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
253
254/* cmd_mbox_query_fw_core_clk
255 * Internal Clock Frequency (in MHz)
256 */
257MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
258
259/* cmd_mbox_query_fw_cmd_interface_rev
260 * Command Interface Interpreter Revision ID. This number is bumped up
261 * every time a non-backward-compatible change is done for the command
262 * interface. The current cmd_interface_rev is 1.
263 */
264MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
265
266/* cmd_mbox_query_fw_dt
267 * If set, Debug Trace is supported
268 */
269MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
270
271/* cmd_mbox_query_fw_api_version
272 * Indicates the version of the API, to enable software querying
273 * for compatibility. The current api_version is 1.
274 */
275MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
276
277/* cmd_mbox_query_fw_fw_hour
278 * Firmware timestamp - hour
279 */
280MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
281
282/* cmd_mbox_query_fw_fw_minutes
283 * Firmware timestamp - minutes
284 */
285MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
286
287/* cmd_mbox_query_fw_fw_seconds
288 * Firmware timestamp - seconds
289 */
290MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8);
291
292/* cmd_mbox_query_fw_fw_year
293 * Firmware timestamp - year
294 */
295MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16);
296
297/* cmd_mbox_query_fw_fw_month
298 * Firmware timestamp - month
299 */
300MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
301
302/* cmd_mbox_query_fw_fw_day
303 * Firmware timestamp - day
304 */
305MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
306
307/* cmd_mbox_query_fw_clr_int_base_offset
308 * Clear Interrupt register's offset from clr_int_bar register
309 * in PCI address space.
310 */
311MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64);
312
313/* cmd_mbox_query_fw_clr_int_bar
314 * PCI base address register (BAR) where clr_int register is located.
315 * 00 - BAR 0-1 (64 bit BAR)
316 */
317MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2);
318
319/* cmd_mbox_query_fw_error_buf_offset
320 * Read Only buffer for internal error reports of offset
321 * from error_buf_bar register in PCI address space).
322 */
323MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64);
324
325/* cmd_mbox_query_fw_error_buf_size
326 * Internal error buffer size in DWORDs
327 */
328MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32);
329
330/* cmd_mbox_query_fw_error_int_bar
331 * PCI base address register (BAR) where error buffer
332 * register is located.
333 * 00 - BAR 0-1 (64 bit BAR)
334 */
335MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2);
336
337/* cmd_mbox_query_fw_doorbell_page_offset
338 * Offset of the doorbell page
339 */
340MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64);
341
342/* cmd_mbox_query_fw_doorbell_page_bar
343 * PCI base address register (BAR) of the doorbell page
344 * 00 - BAR 0-1 (64 bit BAR)
345 */
346MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2);
347
348/* QUERY_BOARDINFO - Query Board Information
349 * -----------------------------------------
350 * OpMod == 0 (N/A), INMmod == 0 (N/A)
351 * -----------------------------------
352 * The QUERY_BOARDINFO command retrieves adapter specific parameters.
353 */
354
355static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core,
356 char *out_mbox)
357{
358 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO,
359 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
360}
361
362/* cmd_mbox_boardinfo_intapin
363 * When PCIe interrupt messages are being used, this value is used for clearing
364 * an interrupt. When using MSI-X, this register is not used.
365 */
366MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8);
367
368/* cmd_mbox_boardinfo_vsd_vendor_id
369 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor
370 * specifying/formatting the VSD. The vsd_vendor_id identifies the management
371 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID
372 * format and encoding as long as they use their assigned vsd_vendor_id.
373 */
374MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16);
375
376/* cmd_mbox_boardinfo_vsd
377 * Vendor Specific Data. The VSD string that is burnt to the Flash
378 * with the firmware.
379 */
380#define MLXSW_CMD_BOARDINFO_VSD_LEN 208
381MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN);
382
383/* cmd_mbox_boardinfo_psid
384 * The PSID field is a 16-ascii (byte) character string which acts as
385 * the board ID. The PSID format is used in conjunction with
386 * Mellanox vsd_vendor_id (15B3h).
387 */
388#define MLXSW_CMD_BOARDINFO_PSID_LEN 16
389MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN);
390
391/* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities
392 * -----------------------------------------------------
393 * OpMod == 0 (N/A), INMmod == 0 (N/A)
394 * -----------------------------------
395 * The QUERY_AQ_CAP command returns the device asynchronous queues
396 * capabilities supported.
397 */
398
399static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core,
400 char *out_mbox)
401{
402 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP,
403 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
404}
405
406/* cmd_mbox_query_aq_cap_log_max_sdq_sz
407 * Log (base 2) of max WQEs allowed on SDQ.
408 */
409MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8);
410
411/* cmd_mbox_query_aq_cap_max_num_sdqs
412 * Maximum number of SDQs.
413 */
414MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8);
415
416/* cmd_mbox_query_aq_cap_log_max_rdq_sz
417 * Log (base 2) of max WQEs allowed on RDQ.
418 */
419MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8);
420
421/* cmd_mbox_query_aq_cap_max_num_rdqs
422 * Maximum number of RDQs.
423 */
424MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8);
425
426/* cmd_mbox_query_aq_cap_log_max_cq_sz
427 * Log (base 2) of max CQEs allowed on CQ.
428 */
429MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8);
430
431/* cmd_mbox_query_aq_cap_max_num_cqs
432 * Maximum number of CQs.
433 */
434MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8);
435
436/* cmd_mbox_query_aq_cap_log_max_eq_sz
437 * Log (base 2) of max EQEs allowed on EQ.
438 */
439MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8);
440
441/* cmd_mbox_query_aq_cap_max_num_eqs
442 * Maximum number of EQs.
443 */
444MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8);
445
446/* cmd_mbox_query_aq_cap_max_sg_sq
447 * The maximum S/G list elements in an DSQ. DSQ must not contain
448 * more S/G entries than indicated here.
449 */
450MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8);
451
452/* cmd_mbox_query_aq_cap_
453 * The maximum S/G list elements in an DRQ. DRQ must not contain
454 * more S/G entries than indicated here.
455 */
456MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8);
457
458/* MAP_FA - Map Firmware Area
459 * --------------------------
460 * OpMod == 0 (N/A), INMmod == Number of VPM entries
461 * -------------------------------------------------
462 * The MAP_FA command passes physical pages to the switch. These pages
463 * are used to store the device firmware. MAP_FA can be executed multiple
464 * times until all the firmware area is mapped (the size that should be
465 * mapped is retrieved through the QUERY_FW command). All required pages
466 * must be mapped to finish the initialization phase. Physical memory
467 * passed in this command must be pinned.
468 */
469
470#define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32
471
472static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core,
473 char *in_mbox, u32 vpm_entries_count)
474{
475 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA,
476 0, vpm_entries_count,
477 in_mbox, MLXSW_CMD_MBOX_SIZE);
478}
479
480/* cmd_mbox_map_fa_pa
481 * Physical Address.
482 */
483MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true);
484
485/* cmd_mbox_map_fa_log2size
486 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory
487 * that starts at PA_L/H.
488 */
489MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false);
490
491/* UNMAP_FA - Unmap Firmware Area
492 * ------------------------------
493 * OpMod == 0 (N/A), INMmod == 0 (N/A)
494 * -----------------------------------
495 * The UNMAP_FA command unload the firmware and unmaps all the
496 * firmware area. After this command is completed the device will not access
497 * the pages that were mapped to the firmware area. After executing UNMAP_FA
498 * command, software reset must be done prior to execution of MAP_FW command.
499 */
500
501static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core)
502{
503 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0);
504}
505
506/* QUERY_RESOURCES - Query chip resources
507 * --------------------------------------
508 * OpMod == 0 (N/A) , INMmod is index
509 * ----------------------------------
510 * The QUERY_RESOURCES command retrieves information related to chip resources
511 * by resource ID. Every command returns 32 entries. INmod is being use as base.
512 * for example, index 1 will return entries 32-63. When the tables end and there
513 * are no more sources in the table, will return resource id 0xFFF to indicate
514 * it.
515 */
516
517#define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff
518#define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100
519#define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32
520
521static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core,
522 char *out_mbox, int index)
523{
524 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES,
525 0, index, false, out_mbox,
526 MLXSW_CMD_MBOX_SIZE);
527}
528
529/* cmd_mbox_query_resource_id
530 * The resource id. 0xFFFF indicates table's end.
531 */
532MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false);
533
534/* cmd_mbox_query_resource_data
535 * The resource
536 */
537MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data,
538 0x00, 0, 40, 0x8, 0, false);
539
540/* CONFIG_PROFILE (Set) - Configure Switch Profile
541 * ------------------------------
542 * OpMod == 1 (Set), INMmod == 0 (N/A)
543 * -----------------------------------
544 * The CONFIG_PROFILE command sets the switch profile. The command can be
545 * executed on the device only once at startup in order to allocate and
546 * configure all switch resources and prepare it for operational mode.
547 * It is not possible to change the device profile after the chip is
548 * in operational mode.
549 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate
550 * state therefore it is required to perform software reset to the device
551 * following an unsuccessful completion of the command. It is required
552 * to perform software reset to the device to change an existing profile.
553 */
554
555static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core,
556 char *in_mbox)
557{
558 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE,
559 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE);
560}
561
562/* cmd_mbox_config_profile_set_max_vepa_channels
563 * Capability bit. Setting a bit to 1 configures the profile
564 * according to the mailbox contents.
565 */
566MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1);
567
568/* cmd_mbox_config_profile_set_max_lag
569 * Capability bit. Setting a bit to 1 configures the profile
570 * according to the mailbox contents.
571 */
572MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1);
573
574/* cmd_mbox_config_profile_set_max_port_per_lag
575 * Capability bit. Setting a bit to 1 configures the profile
576 * according to the mailbox contents.
577 */
578MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1);
579
580/* cmd_mbox_config_profile_set_max_mid
581 * Capability bit. Setting a bit to 1 configures the profile
582 * according to the mailbox contents.
583 */
584MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1);
585
586/* cmd_mbox_config_profile_set_max_pgt
587 * Capability bit. Setting a bit to 1 configures the profile
588 * according to the mailbox contents.
589 */
590MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1);
591
592/* cmd_mbox_config_profile_set_max_system_port
593 * Capability bit. Setting a bit to 1 configures the profile
594 * according to the mailbox contents.
595 */
596MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1);
597
598/* cmd_mbox_config_profile_set_max_vlan_groups
599 * Capability bit. Setting a bit to 1 configures the profile
600 * according to the mailbox contents.
601 */
602MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1);
603
604/* cmd_mbox_config_profile_set_max_regions
605 * Capability bit. Setting a bit to 1 configures the profile
606 * according to the mailbox contents.
607 */
608MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1);
609
610/* cmd_mbox_config_profile_set_flood_mode
611 * Capability bit. Setting a bit to 1 configures the profile
612 * according to the mailbox contents.
613 */
614MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1);
615
616/* cmd_mbox_config_profile_set_max_flood_tables
617 * Capability bit. Setting a bit to 1 configures the profile
618 * according to the mailbox contents.
619 */
620MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1);
621
622/* cmd_mbox_config_profile_set_max_ib_mc
623 * Capability bit. Setting a bit to 1 configures the profile
624 * according to the mailbox contents.
625 */
626MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1);
627
628/* cmd_mbox_config_profile_set_max_pkey
629 * Capability bit. Setting a bit to 1 configures the profile
630 * according to the mailbox contents.
631 */
632MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1);
633
634/* cmd_mbox_config_profile_set_adaptive_routing_group_cap
635 * Capability bit. Setting a bit to 1 configures the profile
636 * according to the mailbox contents.
637 */
638MLXSW_ITEM32(cmd_mbox, config_profile,
639 set_adaptive_routing_group_cap, 0x0C, 14, 1);
640
641/* cmd_mbox_config_profile_set_ar_sec
642 * Capability bit. Setting a bit to 1 configures the profile
643 * according to the mailbox contents.
644 */
645MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1);
646
647/* cmd_mbox_config_set_kvd_linear_size
648 * Capability bit. Setting a bit to 1 configures the profile
649 * according to the mailbox contents.
650 */
651MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1);
652
653/* cmd_mbox_config_set_kvd_hash_single_size
654 * Capability bit. Setting a bit to 1 configures the profile
655 * according to the mailbox contents.
656 */
657MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1);
658
659/* cmd_mbox_config_set_kvd_hash_double_size
660 * Capability bit. Setting a bit to 1 configures the profile
661 * according to the mailbox contents.
662 */
663MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
664
665/* cmd_mbox_config_profile_max_vepa_channels
666 * Maximum number of VEPA channels per port (0 through 16)
667 * 0 - multi-channel VEPA is disabled
668 */
669MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8);
670
671/* cmd_mbox_config_profile_max_lag
672 * Maximum number of LAG IDs requested.
673 */
674MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16);
675
676/* cmd_mbox_config_profile_max_port_per_lag
677 * Maximum number of ports per LAG requested.
678 */
679MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16);
680
681/* cmd_mbox_config_profile_max_mid
682 * Maximum Multicast IDs.
683 * Multicast IDs are allocated from 0 to max_mid-1
684 */
685MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16);
686
687/* cmd_mbox_config_profile_max_pgt
688 * Maximum records in the Port Group Table per Switch Partition.
689 * Port Group Table indexes are from 0 to max_pgt-1
690 */
691MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16);
692
693/* cmd_mbox_config_profile_max_system_port
694 * The maximum number of system ports that can be allocated.
695 */
696MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16);
697
698/* cmd_mbox_config_profile_max_vlan_groups
699 * Maximum number VLAN Groups for VLAN binding.
700 */
701MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12);
702
703/* cmd_mbox_config_profile_max_regions
704 * Maximum number of TCAM Regions.
705 */
706MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16);
707
708/* cmd_mbox_config_profile_max_flood_tables
709 * Maximum number of single-entry flooding tables. Different flooding tables
710 * can be associated with different packet types.
711 */
712MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4);
713
714/* cmd_mbox_config_profile_max_vid_flood_tables
715 * Maximum number of per-vid flooding tables. Flooding tables are associated
716 * to the different packet types for the different switch partitions.
717 * Table size is 4K entries covering all VID space.
718 */
719MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4);
720
721/* cmd_mbox_config_profile_flood_mode
722 * Flooding mode to use.
723 * 0-2 - Backward compatible modes for SwitchX devices.
724 * 3 - Mixed mode, where:
725 * max_flood_tables indicates the number of single-entry tables.
726 * max_vid_flood_tables indicates the number of per-VID tables.
727 * max_fid_offset_flood_tables indicates the number of FID-offset tables.
728 * max_fid_flood_tables indicates the number of per-FID tables.
729 */
730MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2);
731
732/* cmd_mbox_config_profile_max_fid_offset_flood_tables
733 * Maximum number of FID-offset flooding tables.
734 */
735MLXSW_ITEM32(cmd_mbox, config_profile,
736 max_fid_offset_flood_tables, 0x34, 24, 4);
737
738/* cmd_mbox_config_profile_fid_offset_flood_table_size
739 * The size (number of entries) of each FID-offset flood table.
740 */
741MLXSW_ITEM32(cmd_mbox, config_profile,
742 fid_offset_flood_table_size, 0x34, 0, 16);
743
744/* cmd_mbox_config_profile_max_fid_flood_tables
745 * Maximum number of per-FID flooding tables.
746 *
747 * Note: This flooding tables cover special FIDs only (vFIDs), starting at
748 * FID value 4K and higher.
749 */
750MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4);
751
752/* cmd_mbox_config_profile_fid_flood_table_size
753 * The size (number of entries) of each per-FID table.
754 */
755MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16);
756
757/* cmd_mbox_config_profile_max_ib_mc
758 * Maximum number of multicast FDB records for InfiniBand
759 * FDB (in 512 chunks) per InfiniBand switch partition.
760 */
761MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15);
762
763/* cmd_mbox_config_profile_max_pkey
764 * Maximum per port PKEY table size (for PKEY enforcement)
765 */
766MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15);
767
768/* cmd_mbox_config_profile_ar_sec
769 * Primary/secondary capability
770 * Describes the number of adaptive routing sub-groups
771 * 0 - disable primary/secondary (single group)
772 * 1 - enable primary/secondary (2 sub-groups)
773 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2
774 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2
775 */
776MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2);
777
778/* cmd_mbox_config_profile_adaptive_routing_group_cap
779 * Adaptive Routing Group Capability. Indicates the number of AR groups
780 * supported. Note that when Primary/secondary is enabled, each
781 * primary/secondary couple consumes 2 adaptive routing entries.
782 */
783MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16);
784
785/* cmd_mbox_config_profile_arn
786 * Adaptive Routing Notification Enable
787 * Not supported in SwitchX, SwitchX-2
788 */
789MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1);
790
791/* cmd_mbox_config_kvd_linear_size
792 * KVD Linear Size
793 * Valid for Spectrum only
794 * Allowed values are 128*N where N=0 or higher
795 */
796MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24);
797
798/* cmd_mbox_config_kvd_hash_single_size
799 * KVD Hash single-entries size
800 * Valid for Spectrum only
801 * Allowed values are 128*N where N=0 or higher
802 * Must be greater or equal to cap_min_kvd_hash_single_size
803 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
804 */
805MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24);
806
807/* cmd_mbox_config_kvd_hash_double_size
808 * KVD Hash double-entries size (units of single-size entries)
809 * Valid for Spectrum only
810 * Allowed values are 128*N where N=0 or higher
811 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size
812 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
813 */
814MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24);
815
816/* cmd_mbox_config_profile_swid_config_mask
817 * Modify Switch Partition Configuration mask. When set, the configu-
818 * ration value for the Switch Partition are taken from the mailbox.
819 * When clear, the current configuration values are used.
820 * Bit 0 - set type
821 * Bit 1 - properties
822 * Other - reserved
823 */
824MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask,
825 0x60, 24, 8, 0x08, 0x00, false);
826
827/* cmd_mbox_config_profile_swid_config_type
828 * Switch Partition type.
829 * 0000 - disabled (Switch Partition does not exist)
830 * 0001 - InfiniBand
831 * 0010 - Ethernet
832 * 1000 - router port (SwitchX-2 only)
833 * Other - reserved
834 */
835MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
836 0x60, 20, 4, 0x08, 0x00, false);
837
838/* cmd_mbox_config_profile_swid_config_properties
839 * Switch Partition properties.
840 */
841MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
842 0x60, 0, 8, 0x08, 0x00, false);
843
844/* ACCESS_REG - Access EMAD Supported Register
845 * ----------------------------------
846 * OpMod == 0 (N/A), INMmod == 0 (N/A)
847 * -------------------------------------
848 * The ACCESS_REG command supports accessing device registers. This access
849 * is mainly used for bootstrapping.
850 */
851
852static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core,
853 char *in_mbox, char *out_mbox)
854{
855 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG,
856 0, 0, false, in_mbox, MLXSW_CMD_MBOX_SIZE,
857 out_mbox, MLXSW_CMD_MBOX_SIZE);
858}
859
860/* SW2HW_DQ - Software to Hardware DQ
861 * ----------------------------------
862 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
863 * INMmod == DQ number
864 * ----------------------------------------------
865 * The SW2HW_DQ command transitions a descriptor queue from software to
866 * hardware ownership. The command enables posting WQEs and ringing DoorBells
867 * on the descriptor queue.
868 */
869
870static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core,
871 char *in_mbox, u32 dq_number,
872 u8 opcode_mod)
873{
874 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ,
875 opcode_mod, dq_number,
876 in_mbox, MLXSW_CMD_MBOX_SIZE);
877}
878
879enum {
880 MLXSW_CMD_OPCODE_MOD_SDQ = 0,
881 MLXSW_CMD_OPCODE_MOD_RDQ = 1,
882};
883
884static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core,
885 char *in_mbox, u32 dq_number)
886{
887 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
888 MLXSW_CMD_OPCODE_MOD_SDQ);
889}
890
891static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core,
892 char *in_mbox, u32 dq_number)
893{
894 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
895 MLXSW_CMD_OPCODE_MOD_RDQ);
896}
897
898/* cmd_mbox_sw2hw_dq_cq
899 * Number of the CQ that this Descriptor Queue reports completions to.
900 */
901MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
902
903/* cmd_mbox_sw2hw_dq_sdq_tclass
904 * SDQ: CPU Egress TClass
905 * RDQ: Reserved
906 */
907MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6);
908
909/* cmd_mbox_sw2hw_dq_log2_dq_sz
910 * Log (base 2) of the Descriptor Queue size in 4KB pages.
911 */
912MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6);
913
914/* cmd_mbox_sw2hw_dq_pa
915 * Physical Address.
916 */
917MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true);
918
919/* HW2SW_DQ - Hardware to Software DQ
920 * ----------------------------------
921 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
922 * INMmod == DQ number
923 * ----------------------------------------------
924 * The HW2SW_DQ command transitions a descriptor queue from hardware to
925 * software ownership. Incoming packets on the DQ are silently discarded,
926 * SW should not post descriptors on nonoperational DQs.
927 */
928
929static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core,
930 u32 dq_number, u8 opcode_mod)
931{
932 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ,
933 opcode_mod, dq_number);
934}
935
936static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core,
937 u32 dq_number)
938{
939 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
940 MLXSW_CMD_OPCODE_MOD_SDQ);
941}
942
943static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core,
944 u32 dq_number)
945{
946 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
947 MLXSW_CMD_OPCODE_MOD_RDQ);
948}
949
950/* 2ERR_DQ - To Error DQ
951 * ---------------------
952 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
953 * INMmod == DQ number
954 * ----------------------------------------------
955 * The 2ERR_DQ command transitions the DQ into the error state from the state
956 * in which it has been. While the command is executed, some in-process
957 * descriptors may complete. Once the DQ transitions into the error state,
958 * if there are posted descriptors on the RDQ/SDQ, the hardware writes
959 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ.
960 * When the command is completed successfully, the DQ is already in
961 * the error state.
962 */
963
964static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core,
965 u32 dq_number, u8 opcode_mod)
966{
967 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
968 opcode_mod, dq_number);
969}
970
971static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core,
972 u32 dq_number)
973{
974 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
975 MLXSW_CMD_OPCODE_MOD_SDQ);
976}
977
978static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core,
979 u32 dq_number)
980{
981 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
982 MLXSW_CMD_OPCODE_MOD_RDQ);
983}
984
985/* QUERY_DQ - Query DQ
986 * ---------------------
987 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
988 * INMmod == DQ number
989 * ----------------------------------------------
990 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware.
991 *
992 * Note: Output mailbox has the same format as SW2HW_DQ.
993 */
994
995static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core,
996 char *out_mbox, u32 dq_number,
997 u8 opcode_mod)
998{
999 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
1000 opcode_mod, dq_number, false,
1001 out_mbox, MLXSW_CMD_MBOX_SIZE);
1002}
1003
1004static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core,
1005 char *out_mbox, u32 dq_number)
1006{
1007 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1008 MLXSW_CMD_OPCODE_MOD_SDQ);
1009}
1010
1011static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core,
1012 char *out_mbox, u32 dq_number)
1013{
1014 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1015 MLXSW_CMD_OPCODE_MOD_RDQ);
1016}
1017
1018/* SW2HW_CQ - Software to Hardware CQ
1019 * ----------------------------------
1020 * OpMod == 0 (N/A), INMmod == CQ number
1021 * -------------------------------------
1022 * The SW2HW_CQ command transfers ownership of a CQ context entry from software
1023 * to hardware. The command takes the CQ context entry from the input mailbox
1024 * and stores it in the CQC in the ownership of the hardware. The command fails
1025 * if the requested CQC entry is already in the ownership of the hardware.
1026 */
1027
1028static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core,
1029 char *in_mbox, u32 cq_number)
1030{
1031 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ,
1032 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1033}
1034
1035/* cmd_mbox_sw2hw_cq_cv
1036 * CQE Version.
1037 * 0 - CQE Version 0, 1 - CQE Version 1
1038 */
1039MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cv, 0x00, 28, 4);
1040
1041/* cmd_mbox_sw2hw_cq_c_eqn
1042 * Event Queue this CQ reports completion events to.
1043 */
1044MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1);
1045
1046/* cmd_mbox_sw2hw_cq_oi
1047 * When set, overrun ignore is enabled. When set, updates of
1048 * CQ consumer counter (poll for completion) or Request completion
1049 * notifications (Arm CQ) DoorBells should not be rung on that CQ.
1050 */
1051MLXSW_ITEM32(cmd_mbox, sw2hw_cq, oi, 0x00, 12, 1);
1052
1053/* cmd_mbox_sw2hw_cq_st
1054 * Event delivery state machine
1055 * 0x0 - FIRED
1056 * 0x1 - ARMED (Request for Notification)
1057 */
1058MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1);
1059
1060/* cmd_mbox_sw2hw_cq_log_cq_size
1061 * Log (base 2) of the CQ size (in entries).
1062 */
1063MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4);
1064
1065/* cmd_mbox_sw2hw_cq_producer_counter
1066 * Producer Counter. The counter is incremented for each CQE that is
1067 * written by the HW to the CQ.
1068 * Maintained by HW (valid for the QUERY_CQ command only)
1069 */
1070MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16);
1071
1072/* cmd_mbox_sw2hw_cq_pa
1073 * Physical Address.
1074 */
1075MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1076
1077/* HW2SW_CQ - Hardware to Software CQ
1078 * ----------------------------------
1079 * OpMod == 0 (N/A), INMmod == CQ number
1080 * -------------------------------------
1081 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware
1082 * to software. The CQC entry is invalidated as a result of this command.
1083 */
1084
1085static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core,
1086 u32 cq_number)
1087{
1088 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ,
1089 0, cq_number);
1090}
1091
1092/* QUERY_CQ - Query CQ
1093 * ----------------------------------
1094 * OpMod == 0 (N/A), INMmod == CQ number
1095 * -------------------------------------
1096 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry.
1097 * The command stores the snapshot in the output mailbox in the software format.
1098 * Note that the CQ context state and values are not affected by the QUERY_CQ
1099 * command. The QUERY_CQ command is for debug purposes only.
1100 *
1101 * Note: Output mailbox has the same format as SW2HW_CQ.
1102 */
1103
1104static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core,
1105 char *out_mbox, u32 cq_number)
1106{
1107 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ,
1108 0, cq_number, false,
1109 out_mbox, MLXSW_CMD_MBOX_SIZE);
1110}
1111
1112/* SW2HW_EQ - Software to Hardware EQ
1113 * ----------------------------------
1114 * OpMod == 0 (N/A), INMmod == EQ number
1115 * -------------------------------------
1116 * The SW2HW_EQ command transfers ownership of an EQ context entry from software
1117 * to hardware. The command takes the EQ context entry from the input mailbox
1118 * and stores it in the EQC in the ownership of the hardware. The command fails
1119 * if the requested EQC entry is already in the ownership of the hardware.
1120 */
1121
1122static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core,
1123 char *in_mbox, u32 eq_number)
1124{
1125 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ,
1126 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1127}
1128
1129/* cmd_mbox_sw2hw_eq_int_msix
1130 * When set, MSI-X cycles will be generated by this EQ.
1131 * When cleared, an interrupt will be generated by this EQ.
1132 */
1133MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1);
1134
1135/* cmd_mbox_sw2hw_eq_int_oi
1136 * When set, overrun ignore is enabled.
1137 */
1138MLXSW_ITEM32(cmd_mbox, sw2hw_eq, oi, 0x00, 12, 1);
1139
1140/* cmd_mbox_sw2hw_eq_int_st
1141 * Event delivery state machine
1142 * 0x0 - FIRED
1143 * 0x1 - ARMED (Request for Notification)
1144 * 0x11 - Always ARMED
1145 * other - reserved
1146 */
1147MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2);
1148
1149/* cmd_mbox_sw2hw_eq_int_log_eq_size
1150 * Log (base 2) of the EQ size (in entries).
1151 */
1152MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4);
1153
1154/* cmd_mbox_sw2hw_eq_int_producer_counter
1155 * Producer Counter. The counter is incremented for each EQE that is written
1156 * by the HW to the EQ.
1157 * Maintained by HW (valid for the QUERY_EQ command only)
1158 */
1159MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16);
1160
1161/* cmd_mbox_sw2hw_eq_int_pa
1162 * Physical Address.
1163 */
1164MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1165
1166/* HW2SW_EQ - Hardware to Software EQ
1167 * ----------------------------------
1168 * OpMod == 0 (N/A), INMmod == EQ number
1169 * -------------------------------------
1170 */
1171
1172static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core,
1173 u32 eq_number)
1174{
1175 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ,
1176 0, eq_number);
1177}
1178
1179/* QUERY_EQ - Query EQ
1180 * ----------------------------------
1181 * OpMod == 0 (N/A), INMmod == EQ number
1182 * -------------------------------------
1183 *
1184 * Note: Output mailbox has the same format as SW2HW_EQ.
1185 */
1186
1187static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core,
1188 char *out_mbox, u32 eq_number)
1189{
1190 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ,
1191 0, eq_number, false,
1192 out_mbox, MLXSW_CMD_MBOX_SIZE);
1193}
1194
1195#endif