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1/*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/errno.h>
15#include <linux/platform_device.h>
16#include <linux/sched.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/timer.h>
24#include <linux/jiffies.h>
25#include <linux/completion.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/spi-nor.h>
29#include <linux/mutex.h>
30#include <linux/pm_qos.h>
31#include <linux/sizes.h>
32
33/* Controller needs driver to swap endian */
34#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
35/* Controller needs 4x internal clock */
36#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
37/*
38 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
39 * trigger data transfer even though extern data will not transferred.
40 */
41#define QUADSPI_QUIRK_TKT253890 (1 << 2)
42/* Controller cannot wake up from wait mode, TKT245618 */
43#define QUADSPI_QUIRK_TKT245618 (1 << 3)
44
45/* The registers */
46#define QUADSPI_MCR 0x00
47#define QUADSPI_MCR_RESERVED_SHIFT 16
48#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
49#define QUADSPI_MCR_MDIS_SHIFT 14
50#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
51#define QUADSPI_MCR_CLR_TXF_SHIFT 11
52#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
53#define QUADSPI_MCR_CLR_RXF_SHIFT 10
54#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
55#define QUADSPI_MCR_DDR_EN_SHIFT 7
56#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
57#define QUADSPI_MCR_END_CFG_SHIFT 2
58#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
59#define QUADSPI_MCR_SWRSTHD_SHIFT 1
60#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
61#define QUADSPI_MCR_SWRSTSD_SHIFT 0
62#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
63
64#define QUADSPI_IPCR 0x08
65#define QUADSPI_IPCR_SEQID_SHIFT 24
66#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
67
68#define QUADSPI_BUF0CR 0x10
69#define QUADSPI_BUF1CR 0x14
70#define QUADSPI_BUF2CR 0x18
71#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
72
73#define QUADSPI_BUF3CR 0x1c
74#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
75#define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
76#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
77#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
78
79#define QUADSPI_BFGENCR 0x20
80#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
81#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
82#define QUADSPI_BFGENCR_SEQID_SHIFT 12
83#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
84
85#define QUADSPI_BUF0IND 0x30
86#define QUADSPI_BUF1IND 0x34
87#define QUADSPI_BUF2IND 0x38
88#define QUADSPI_SFAR 0x100
89
90#define QUADSPI_SMPR 0x108
91#define QUADSPI_SMPR_DDRSMP_SHIFT 16
92#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
93#define QUADSPI_SMPR_FSDLY_SHIFT 6
94#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
95#define QUADSPI_SMPR_FSPHS_SHIFT 5
96#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
97#define QUADSPI_SMPR_HSENA_SHIFT 0
98#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
99
100#define QUADSPI_RBSR 0x10c
101#define QUADSPI_RBSR_RDBFL_SHIFT 8
102#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
103
104#define QUADSPI_RBCT 0x110
105#define QUADSPI_RBCT_WMRK_MASK 0x1F
106#define QUADSPI_RBCT_RXBRD_SHIFT 8
107#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
108
109#define QUADSPI_TBSR 0x150
110#define QUADSPI_TBDR 0x154
111#define QUADSPI_SR 0x15c
112#define QUADSPI_SR_IP_ACC_SHIFT 1
113#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
114#define QUADSPI_SR_AHB_ACC_SHIFT 2
115#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
116
117#define QUADSPI_FR 0x160
118#define QUADSPI_FR_TFF_MASK 0x1
119
120#define QUADSPI_SFA1AD 0x180
121#define QUADSPI_SFA2AD 0x184
122#define QUADSPI_SFB1AD 0x188
123#define QUADSPI_SFB2AD 0x18c
124#define QUADSPI_RBDR 0x200
125
126#define QUADSPI_LUTKEY 0x300
127#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
128
129#define QUADSPI_LCKCR 0x304
130#define QUADSPI_LCKER_LOCK 0x1
131#define QUADSPI_LCKER_UNLOCK 0x2
132
133#define QUADSPI_RSER 0x164
134#define QUADSPI_RSER_TFIE (0x1 << 0)
135
136#define QUADSPI_LUT_BASE 0x310
137
138/*
139 * The definition of the LUT register shows below:
140 *
141 * ---------------------------------------------------
142 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
143 * ---------------------------------------------------
144 */
145#define OPRND0_SHIFT 0
146#define PAD0_SHIFT 8
147#define INSTR0_SHIFT 10
148#define OPRND1_SHIFT 16
149
150/* Instruction set for the LUT register. */
151#define LUT_STOP 0
152#define LUT_CMD 1
153#define LUT_ADDR 2
154#define LUT_DUMMY 3
155#define LUT_MODE 4
156#define LUT_MODE2 5
157#define LUT_MODE4 6
158#define LUT_FSL_READ 7
159#define LUT_FSL_WRITE 8
160#define LUT_JMP_ON_CS 9
161#define LUT_ADDR_DDR 10
162#define LUT_MODE_DDR 11
163#define LUT_MODE2_DDR 12
164#define LUT_MODE4_DDR 13
165#define LUT_FSL_READ_DDR 14
166#define LUT_FSL_WRITE_DDR 15
167#define LUT_DATA_LEARN 16
168
169/*
170 * The PAD definitions for LUT register.
171 *
172 * The pad stands for the lines number of IO[0:3].
173 * For example, the Quad read need four IO lines, so you should
174 * set LUT_PAD4 which means we use four IO lines.
175 */
176#define LUT_PAD1 0
177#define LUT_PAD2 1
178#define LUT_PAD4 2
179
180/* Oprands for the LUT register. */
181#define ADDR24BIT 0x18
182#define ADDR32BIT 0x20
183
184/* Macros for constructing the LUT register. */
185#define LUT0(ins, pad, opr) \
186 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
187 ((LUT_##ins) << INSTR0_SHIFT))
188
189#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
190
191/* other macros for LUT register. */
192#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
193#define QUADSPI_LUT_NUM 64
194
195/* SEQID -- we can have 16 seqids at most. */
196#define SEQID_QUAD_READ 0
197#define SEQID_WREN 1
198#define SEQID_WRDI 2
199#define SEQID_RDSR 3
200#define SEQID_SE 4
201#define SEQID_CHIP_ERASE 5
202#define SEQID_PP 6
203#define SEQID_RDID 7
204#define SEQID_WRSR 8
205#define SEQID_RDCR 9
206#define SEQID_EN4B 10
207#define SEQID_BRWR 11
208
209#define QUADSPI_MIN_IOMAP SZ_4M
210
211enum fsl_qspi_devtype {
212 FSL_QUADSPI_VYBRID,
213 FSL_QUADSPI_IMX6SX,
214 FSL_QUADSPI_IMX7D,
215 FSL_QUADSPI_IMX6UL,
216 FSL_QUADSPI_LS1021A,
217};
218
219struct fsl_qspi_devtype_data {
220 enum fsl_qspi_devtype devtype;
221 int rxfifo;
222 int txfifo;
223 int ahb_buf_size;
224 int driver_data;
225};
226
227static const struct fsl_qspi_devtype_data vybrid_data = {
228 .devtype = FSL_QUADSPI_VYBRID,
229 .rxfifo = 128,
230 .txfifo = 64,
231 .ahb_buf_size = 1024,
232 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
233};
234
235static const struct fsl_qspi_devtype_data imx6sx_data = {
236 .devtype = FSL_QUADSPI_IMX6SX,
237 .rxfifo = 128,
238 .txfifo = 512,
239 .ahb_buf_size = 1024,
240 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
241 | QUADSPI_QUIRK_TKT245618,
242};
243
244static const struct fsl_qspi_devtype_data imx7d_data = {
245 .devtype = FSL_QUADSPI_IMX7D,
246 .rxfifo = 512,
247 .txfifo = 512,
248 .ahb_buf_size = 1024,
249 .driver_data = QUADSPI_QUIRK_TKT253890
250 | QUADSPI_QUIRK_4X_INT_CLK,
251};
252
253static const struct fsl_qspi_devtype_data imx6ul_data = {
254 .devtype = FSL_QUADSPI_IMX6UL,
255 .rxfifo = 128,
256 .txfifo = 512,
257 .ahb_buf_size = 1024,
258 .driver_data = QUADSPI_QUIRK_TKT253890
259 | QUADSPI_QUIRK_4X_INT_CLK,
260};
261
262static struct fsl_qspi_devtype_data ls1021a_data = {
263 .devtype = FSL_QUADSPI_LS1021A,
264 .rxfifo = 128,
265 .txfifo = 64,
266 .ahb_buf_size = 1024,
267 .driver_data = 0,
268};
269
270#define FSL_QSPI_MAX_CHIP 4
271struct fsl_qspi {
272 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
273 void __iomem *iobase;
274 void __iomem *ahb_addr;
275 u32 memmap_phy;
276 u32 memmap_offs;
277 u32 memmap_len;
278 struct clk *clk, *clk_en;
279 struct device *dev;
280 struct completion c;
281 const struct fsl_qspi_devtype_data *devtype_data;
282 u32 nor_size;
283 u32 nor_num;
284 u32 clk_rate;
285 unsigned int chip_base_addr; /* We may support two chips. */
286 bool has_second_chip;
287 bool big_endian;
288 struct mutex lock;
289 struct pm_qos_request pm_qos_req;
290};
291
292static inline int needs_swap_endian(struct fsl_qspi *q)
293{
294 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
295}
296
297static inline int needs_4x_clock(struct fsl_qspi *q)
298{
299 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
300}
301
302static inline int needs_fill_txfifo(struct fsl_qspi *q)
303{
304 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
305}
306
307static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
308{
309 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
310}
311
312/*
313 * R/W functions for big- or little-endian registers:
314 * The qSPI controller's endian is independent of the CPU core's endian.
315 * So far, although the CPU core is little-endian but the qSPI have two
316 * versions for big-endian and little-endian.
317 */
318static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
319{
320 if (q->big_endian)
321 iowrite32be(val, addr);
322 else
323 iowrite32(val, addr);
324}
325
326static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
327{
328 if (q->big_endian)
329 return ioread32be(addr);
330 else
331 return ioread32(addr);
332}
333
334/*
335 * An IC bug makes us to re-arrange the 32-bit data.
336 * The following chips, such as IMX6SLX, have fixed this bug.
337 */
338static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
339{
340 return needs_swap_endian(q) ? __swab32(a) : a;
341}
342
343static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
344{
345 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
346 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
347}
348
349static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
350{
351 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
352 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
353}
354
355static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
356{
357 struct fsl_qspi *q = dev_id;
358 u32 reg;
359
360 /* clear interrupt */
361 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
362 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
363
364 if (reg & QUADSPI_FR_TFF_MASK)
365 complete(&q->c);
366
367 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
368 return IRQ_HANDLED;
369}
370
371static void fsl_qspi_init_lut(struct fsl_qspi *q)
372{
373 void __iomem *base = q->iobase;
374 int rxfifo = q->devtype_data->rxfifo;
375 u32 lut_base;
376 u8 cmd, addrlen, dummy;
377 int i;
378
379 fsl_qspi_unlock_lut(q);
380
381 /* Clear all the LUT table */
382 for (i = 0; i < QUADSPI_LUT_NUM; i++)
383 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
384
385 /* Quad Read */
386 lut_base = SEQID_QUAD_READ * 4;
387
388 if (q->nor_size <= SZ_16M) {
389 cmd = SPINOR_OP_READ_1_1_4;
390 addrlen = ADDR24BIT;
391 dummy = 8;
392 } else {
393 /* use the 4-byte address */
394 cmd = SPINOR_OP_READ_1_1_4;
395 addrlen = ADDR32BIT;
396 dummy = 8;
397 }
398
399 qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
400 base + QUADSPI_LUT(lut_base));
401 qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
402 base + QUADSPI_LUT(lut_base + 1));
403
404 /* Write enable */
405 lut_base = SEQID_WREN * 4;
406 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
407 base + QUADSPI_LUT(lut_base));
408
409 /* Page Program */
410 lut_base = SEQID_PP * 4;
411
412 if (q->nor_size <= SZ_16M) {
413 cmd = SPINOR_OP_PP;
414 addrlen = ADDR24BIT;
415 } else {
416 /* use the 4-byte address */
417 cmd = SPINOR_OP_PP;
418 addrlen = ADDR32BIT;
419 }
420
421 qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
422 base + QUADSPI_LUT(lut_base));
423 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
424 base + QUADSPI_LUT(lut_base + 1));
425
426 /* Read Status */
427 lut_base = SEQID_RDSR * 4;
428 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
429 LUT1(FSL_READ, PAD1, 0x1),
430 base + QUADSPI_LUT(lut_base));
431
432 /* Erase a sector */
433 lut_base = SEQID_SE * 4;
434
435 cmd = q->nor[0].erase_opcode;
436 addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
437
438 qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
439 base + QUADSPI_LUT(lut_base));
440
441 /* Erase the whole chip */
442 lut_base = SEQID_CHIP_ERASE * 4;
443 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
444 base + QUADSPI_LUT(lut_base));
445
446 /* READ ID */
447 lut_base = SEQID_RDID * 4;
448 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
449 LUT1(FSL_READ, PAD1, 0x8),
450 base + QUADSPI_LUT(lut_base));
451
452 /* Write Register */
453 lut_base = SEQID_WRSR * 4;
454 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
455 LUT1(FSL_WRITE, PAD1, 0x2),
456 base + QUADSPI_LUT(lut_base));
457
458 /* Read Configuration Register */
459 lut_base = SEQID_RDCR * 4;
460 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
461 LUT1(FSL_READ, PAD1, 0x1),
462 base + QUADSPI_LUT(lut_base));
463
464 /* Write disable */
465 lut_base = SEQID_WRDI * 4;
466 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
467 base + QUADSPI_LUT(lut_base));
468
469 /* Enter 4 Byte Mode (Micron) */
470 lut_base = SEQID_EN4B * 4;
471 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
472 base + QUADSPI_LUT(lut_base));
473
474 /* Enter 4 Byte Mode (Spansion) */
475 lut_base = SEQID_BRWR * 4;
476 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
477 base + QUADSPI_LUT(lut_base));
478
479 fsl_qspi_lock_lut(q);
480}
481
482/* Get the SEQID for the command */
483static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
484{
485 switch (cmd) {
486 case SPINOR_OP_READ_1_1_4:
487 return SEQID_QUAD_READ;
488 case SPINOR_OP_WREN:
489 return SEQID_WREN;
490 case SPINOR_OP_WRDI:
491 return SEQID_WRDI;
492 case SPINOR_OP_RDSR:
493 return SEQID_RDSR;
494 case SPINOR_OP_SE:
495 return SEQID_SE;
496 case SPINOR_OP_CHIP_ERASE:
497 return SEQID_CHIP_ERASE;
498 case SPINOR_OP_PP:
499 return SEQID_PP;
500 case SPINOR_OP_RDID:
501 return SEQID_RDID;
502 case SPINOR_OP_WRSR:
503 return SEQID_WRSR;
504 case SPINOR_OP_RDCR:
505 return SEQID_RDCR;
506 case SPINOR_OP_EN4B:
507 return SEQID_EN4B;
508 case SPINOR_OP_BRWR:
509 return SEQID_BRWR;
510 default:
511 if (cmd == q->nor[0].erase_opcode)
512 return SEQID_SE;
513 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
514 break;
515 }
516 return -EINVAL;
517}
518
519static int
520fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
521{
522 void __iomem *base = q->iobase;
523 int seqid;
524 u32 reg, reg2;
525 int err;
526
527 init_completion(&q->c);
528 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
529 q->chip_base_addr, addr, len, cmd);
530
531 /* save the reg */
532 reg = qspi_readl(q, base + QUADSPI_MCR);
533
534 qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
535 base + QUADSPI_SFAR);
536 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
537 base + QUADSPI_RBCT);
538 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
539
540 do {
541 reg2 = qspi_readl(q, base + QUADSPI_SR);
542 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
543 udelay(1);
544 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
545 continue;
546 }
547 break;
548 } while (1);
549
550 /* trigger the LUT now */
551 seqid = fsl_qspi_get_seqid(q, cmd);
552 qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
553 base + QUADSPI_IPCR);
554
555 /* Wait for the interrupt. */
556 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
557 dev_err(q->dev,
558 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
559 cmd, addr, qspi_readl(q, base + QUADSPI_FR),
560 qspi_readl(q, base + QUADSPI_SR));
561 err = -ETIMEDOUT;
562 } else {
563 err = 0;
564 }
565
566 /* restore the MCR */
567 qspi_writel(q, reg, base + QUADSPI_MCR);
568
569 return err;
570}
571
572/* Read out the data from the QUADSPI_RBDR buffer registers. */
573static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
574{
575 u32 tmp;
576 int i = 0;
577
578 while (len > 0) {
579 tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
580 tmp = fsl_qspi_endian_xchg(q, tmp);
581 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
582 q->chip_base_addr, tmp);
583
584 if (len >= 4) {
585 *((u32 *)rxbuf) = tmp;
586 rxbuf += 4;
587 } else {
588 memcpy(rxbuf, &tmp, len);
589 break;
590 }
591
592 len -= 4;
593 i++;
594 }
595}
596
597/*
598 * If we have changed the content of the flash by writing or erasing,
599 * we need to invalidate the AHB buffer. If we do not do so, we may read out
600 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
601 * domain at the same time.
602 */
603static inline void fsl_qspi_invalid(struct fsl_qspi *q)
604{
605 u32 reg;
606
607 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
608 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
609 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
610
611 /*
612 * The minimum delay : 1 AHB + 2 SFCK clocks.
613 * Delay 1 us is enough.
614 */
615 udelay(1);
616
617 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
618 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
619}
620
621static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
622 u8 opcode, unsigned int to, u32 *txbuf,
623 unsigned count)
624{
625 int ret, i, j;
626 u32 tmp;
627
628 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
629 q->chip_base_addr, to, count);
630
631 /* clear the TX FIFO. */
632 tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
633 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
634
635 /* fill the TX data to the FIFO */
636 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
637 tmp = fsl_qspi_endian_xchg(q, *txbuf);
638 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
639 txbuf++;
640 }
641
642 /* fill the TXFIFO upto 16 bytes for i.MX7d */
643 if (needs_fill_txfifo(q))
644 for (; i < 4; i++)
645 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
646
647 /* Trigger it */
648 ret = fsl_qspi_runcmd(q, opcode, to, count);
649
650 if (ret == 0)
651 return count;
652
653 return ret;
654}
655
656static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
657{
658 int nor_size = q->nor_size;
659 void __iomem *base = q->iobase;
660
661 qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
662 qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
663 qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
664 qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
665}
666
667/*
668 * There are two different ways to read out the data from the flash:
669 * the "IP Command Read" and the "AHB Command Read".
670 *
671 * The IC guy suggests we use the "AHB Command Read" which is faster
672 * then the "IP Command Read". (What's more is that there is a bug in
673 * the "IP Command Read" in the Vybrid.)
674 *
675 * After we set up the registers for the "AHB Command Read", we can use
676 * the memcpy to read the data directly. A "missed" access to the buffer
677 * causes the controller to clear the buffer, and use the sequence pointed
678 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
679 */
680static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
681{
682 void __iomem *base = q->iobase;
683 int seqid;
684
685 /* AHB configuration for access buffer 0/1/2 .*/
686 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
687 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
688 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
689 /*
690 * Set ADATSZ with the maximum AHB buffer size to improve the
691 * read performance.
692 */
693 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
694 ((q->devtype_data->ahb_buf_size / 8)
695 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
696 base + QUADSPI_BUF3CR);
697
698 /* We only use the buffer3 */
699 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
700 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
701 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
702
703 /* Set the default lut sequence for AHB Read. */
704 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
705 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
706 q->iobase + QUADSPI_BFGENCR);
707}
708
709/* This function was used to prepare and enable QSPI clock */
710static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
711{
712 int ret;
713
714 ret = clk_prepare_enable(q->clk_en);
715 if (ret)
716 return ret;
717
718 ret = clk_prepare_enable(q->clk);
719 if (ret) {
720 clk_disable_unprepare(q->clk_en);
721 return ret;
722 }
723
724 if (needs_wakeup_wait_mode(q))
725 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
726
727 return 0;
728}
729
730/* This function was used to disable and unprepare QSPI clock */
731static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
732{
733 if (needs_wakeup_wait_mode(q))
734 pm_qos_remove_request(&q->pm_qos_req);
735
736 clk_disable_unprepare(q->clk);
737 clk_disable_unprepare(q->clk_en);
738
739}
740
741/* We use this function to do some basic init for spi_nor_scan(). */
742static int fsl_qspi_nor_setup(struct fsl_qspi *q)
743{
744 void __iomem *base = q->iobase;
745 u32 reg;
746 int ret;
747
748 /* disable and unprepare clock to avoid glitch pass to controller */
749 fsl_qspi_clk_disable_unprep(q);
750
751 /* the default frequency, we will change it in the future. */
752 ret = clk_set_rate(q->clk, 66000000);
753 if (ret)
754 return ret;
755
756 ret = fsl_qspi_clk_prep_enable(q);
757 if (ret)
758 return ret;
759
760 /* Reset the module */
761 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
762 base + QUADSPI_MCR);
763 udelay(1);
764
765 /* Init the LUT table. */
766 fsl_qspi_init_lut(q);
767
768 /* Disable the module */
769 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
770 base + QUADSPI_MCR);
771
772 reg = qspi_readl(q, base + QUADSPI_SMPR);
773 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
774 | QUADSPI_SMPR_FSPHS_MASK
775 | QUADSPI_SMPR_HSENA_MASK
776 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
777
778 /* Enable the module */
779 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
780 base + QUADSPI_MCR);
781
782 /* clear all interrupt status */
783 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
784
785 /* enable the interrupt */
786 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
787
788 return 0;
789}
790
791static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
792{
793 unsigned long rate = q->clk_rate;
794 int ret;
795
796 if (needs_4x_clock(q))
797 rate *= 4;
798
799 /* disable and unprepare clock to avoid glitch pass to controller */
800 fsl_qspi_clk_disable_unprep(q);
801
802 ret = clk_set_rate(q->clk, rate);
803 if (ret)
804 return ret;
805
806 ret = fsl_qspi_clk_prep_enable(q);
807 if (ret)
808 return ret;
809
810 /* Init the LUT table again. */
811 fsl_qspi_init_lut(q);
812
813 /* Init for AHB read */
814 fsl_qspi_init_abh_read(q);
815
816 return 0;
817}
818
819static const struct of_device_id fsl_qspi_dt_ids[] = {
820 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
821 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
822 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
823 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
824 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
825 { /* sentinel */ }
826};
827MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
828
829static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
830{
831 q->chip_base_addr = q->nor_size * (nor - q->nor);
832}
833
834static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
835{
836 int ret;
837 struct fsl_qspi *q = nor->priv;
838
839 ret = fsl_qspi_runcmd(q, opcode, 0, len);
840 if (ret)
841 return ret;
842
843 fsl_qspi_read_data(q, len, buf);
844 return 0;
845}
846
847static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
848{
849 struct fsl_qspi *q = nor->priv;
850 int ret;
851
852 if (!buf) {
853 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
854 if (ret)
855 return ret;
856
857 if (opcode == SPINOR_OP_CHIP_ERASE)
858 fsl_qspi_invalid(q);
859
860 } else if (len > 0) {
861 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
862 (u32 *)buf, len);
863 if (ret > 0)
864 return 0;
865 } else {
866 dev_err(q->dev, "invalid cmd %d\n", opcode);
867 ret = -EINVAL;
868 }
869
870 return ret;
871}
872
873static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
874 size_t len, const u_char *buf)
875{
876 struct fsl_qspi *q = nor->priv;
877 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
878 (u32 *)buf, len);
879
880 /* invalid the data in the AHB buffer. */
881 fsl_qspi_invalid(q);
882 return ret;
883}
884
885static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
886 size_t len, u_char *buf)
887{
888 struct fsl_qspi *q = nor->priv;
889 u8 cmd = nor->read_opcode;
890
891 /* if necessary,ioremap buffer before AHB read, */
892 if (!q->ahb_addr) {
893 q->memmap_offs = q->chip_base_addr + from;
894 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
895
896 q->ahb_addr = ioremap_nocache(
897 q->memmap_phy + q->memmap_offs,
898 q->memmap_len);
899 if (!q->ahb_addr) {
900 dev_err(q->dev, "ioremap failed\n");
901 return -ENOMEM;
902 }
903 /* ioremap if the data requested is out of range */
904 } else if (q->chip_base_addr + from < q->memmap_offs
905 || q->chip_base_addr + from + len >
906 q->memmap_offs + q->memmap_len) {
907 iounmap(q->ahb_addr);
908
909 q->memmap_offs = q->chip_base_addr + from;
910 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
911 q->ahb_addr = ioremap_nocache(
912 q->memmap_phy + q->memmap_offs,
913 q->memmap_len);
914 if (!q->ahb_addr) {
915 dev_err(q->dev, "ioremap failed\n");
916 return -ENOMEM;
917 }
918 }
919
920 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
921 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
922 len);
923
924 /* Read out the data directly from the AHB buffer.*/
925 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
926 len);
927
928 return len;
929}
930
931static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
932{
933 struct fsl_qspi *q = nor->priv;
934 int ret;
935
936 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
937 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
938
939 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
940 if (ret)
941 return ret;
942
943 fsl_qspi_invalid(q);
944 return 0;
945}
946
947static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
948{
949 struct fsl_qspi *q = nor->priv;
950 int ret;
951
952 mutex_lock(&q->lock);
953
954 ret = fsl_qspi_clk_prep_enable(q);
955 if (ret)
956 goto err_mutex;
957
958 fsl_qspi_set_base_addr(q, nor);
959 return 0;
960
961err_mutex:
962 mutex_unlock(&q->lock);
963 return ret;
964}
965
966static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
967{
968 struct fsl_qspi *q = nor->priv;
969
970 fsl_qspi_clk_disable_unprep(q);
971 mutex_unlock(&q->lock);
972}
973
974static int fsl_qspi_probe(struct platform_device *pdev)
975{
976 struct device_node *np = pdev->dev.of_node;
977 struct device *dev = &pdev->dev;
978 struct fsl_qspi *q;
979 struct resource *res;
980 struct spi_nor *nor;
981 struct mtd_info *mtd;
982 int ret, i = 0;
983
984 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
985 if (!q)
986 return -ENOMEM;
987
988 q->nor_num = of_get_child_count(dev->of_node);
989 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
990 return -ENODEV;
991
992 q->dev = dev;
993 q->devtype_data = of_device_get_match_data(dev);
994 if (!q->devtype_data)
995 return -ENODEV;
996 platform_set_drvdata(pdev, q);
997
998 /* find the resources */
999 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
1000 q->iobase = devm_ioremap_resource(dev, res);
1001 if (IS_ERR(q->iobase))
1002 return PTR_ERR(q->iobase);
1003
1004 q->big_endian = of_property_read_bool(np, "big-endian");
1005 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1006 "QuadSPI-memory");
1007 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1008 res->name)) {
1009 dev_err(dev, "can't request region for resource %pR\n", res);
1010 return -EBUSY;
1011 }
1012
1013 q->memmap_phy = res->start;
1014
1015 /* find the clocks */
1016 q->clk_en = devm_clk_get(dev, "qspi_en");
1017 if (IS_ERR(q->clk_en))
1018 return PTR_ERR(q->clk_en);
1019
1020 q->clk = devm_clk_get(dev, "qspi");
1021 if (IS_ERR(q->clk))
1022 return PTR_ERR(q->clk);
1023
1024 ret = fsl_qspi_clk_prep_enable(q);
1025 if (ret) {
1026 dev_err(dev, "can not enable the clock\n");
1027 goto clk_failed;
1028 }
1029
1030 /* find the irq */
1031 ret = platform_get_irq(pdev, 0);
1032 if (ret < 0) {
1033 dev_err(dev, "failed to get the irq: %d\n", ret);
1034 goto irq_failed;
1035 }
1036
1037 ret = devm_request_irq(dev, ret,
1038 fsl_qspi_irq_handler, 0, pdev->name, q);
1039 if (ret) {
1040 dev_err(dev, "failed to request irq: %d\n", ret);
1041 goto irq_failed;
1042 }
1043
1044 ret = fsl_qspi_nor_setup(q);
1045 if (ret)
1046 goto irq_failed;
1047
1048 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1049 q->has_second_chip = true;
1050
1051 mutex_init(&q->lock);
1052
1053 /* iterate the subnodes. */
1054 for_each_available_child_of_node(dev->of_node, np) {
1055 /* skip the holes */
1056 if (!q->has_second_chip)
1057 i *= 2;
1058
1059 nor = &q->nor[i];
1060 mtd = &nor->mtd;
1061
1062 nor->dev = dev;
1063 spi_nor_set_flash_node(nor, np);
1064 nor->priv = q;
1065
1066 /* fill the hooks */
1067 nor->read_reg = fsl_qspi_read_reg;
1068 nor->write_reg = fsl_qspi_write_reg;
1069 nor->read = fsl_qspi_read;
1070 nor->write = fsl_qspi_write;
1071 nor->erase = fsl_qspi_erase;
1072
1073 nor->prepare = fsl_qspi_prep;
1074 nor->unprepare = fsl_qspi_unprep;
1075
1076 ret = of_property_read_u32(np, "spi-max-frequency",
1077 &q->clk_rate);
1078 if (ret < 0)
1079 goto mutex_failed;
1080
1081 /* set the chip address for READID */
1082 fsl_qspi_set_base_addr(q, nor);
1083
1084 ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
1085 if (ret)
1086 goto mutex_failed;
1087
1088 ret = mtd_device_register(mtd, NULL, 0);
1089 if (ret)
1090 goto mutex_failed;
1091
1092 /* Set the correct NOR size now. */
1093 if (q->nor_size == 0) {
1094 q->nor_size = mtd->size;
1095
1096 /* Map the SPI NOR to accessiable address */
1097 fsl_qspi_set_map_addr(q);
1098 }
1099
1100 /*
1101 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1102 * may writes 265 bytes per time. The write is working in the
1103 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1104 * size.
1105 *
1106 * So shrink the spi_nor->page_size if it is larger then the
1107 * TX FIFO.
1108 */
1109 if (nor->page_size > q->devtype_data->txfifo)
1110 nor->page_size = q->devtype_data->txfifo;
1111
1112 i++;
1113 }
1114
1115 /* finish the rest init. */
1116 ret = fsl_qspi_nor_setup_last(q);
1117 if (ret)
1118 goto last_init_failed;
1119
1120 fsl_qspi_clk_disable_unprep(q);
1121 return 0;
1122
1123last_init_failed:
1124 for (i = 0; i < q->nor_num; i++) {
1125 /* skip the holes */
1126 if (!q->has_second_chip)
1127 i *= 2;
1128 mtd_device_unregister(&q->nor[i].mtd);
1129 }
1130mutex_failed:
1131 mutex_destroy(&q->lock);
1132irq_failed:
1133 fsl_qspi_clk_disable_unprep(q);
1134clk_failed:
1135 dev_err(dev, "Freescale QuadSPI probe failed\n");
1136 return ret;
1137}
1138
1139static int fsl_qspi_remove(struct platform_device *pdev)
1140{
1141 struct fsl_qspi *q = platform_get_drvdata(pdev);
1142 int i;
1143
1144 for (i = 0; i < q->nor_num; i++) {
1145 /* skip the holes */
1146 if (!q->has_second_chip)
1147 i *= 2;
1148 mtd_device_unregister(&q->nor[i].mtd);
1149 }
1150
1151 /* disable the hardware */
1152 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1153 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
1154
1155 mutex_destroy(&q->lock);
1156
1157 if (q->ahb_addr)
1158 iounmap(q->ahb_addr);
1159
1160 return 0;
1161}
1162
1163static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1164{
1165 return 0;
1166}
1167
1168static int fsl_qspi_resume(struct platform_device *pdev)
1169{
1170 int ret;
1171 struct fsl_qspi *q = platform_get_drvdata(pdev);
1172
1173 ret = fsl_qspi_clk_prep_enable(q);
1174 if (ret)
1175 return ret;
1176
1177 fsl_qspi_nor_setup(q);
1178 fsl_qspi_set_map_addr(q);
1179 fsl_qspi_nor_setup_last(q);
1180
1181 fsl_qspi_clk_disable_unprep(q);
1182
1183 return 0;
1184}
1185
1186static struct platform_driver fsl_qspi_driver = {
1187 .driver = {
1188 .name = "fsl-quadspi",
1189 .bus = &platform_bus_type,
1190 .of_match_table = fsl_qspi_dt_ids,
1191 },
1192 .probe = fsl_qspi_probe,
1193 .remove = fsl_qspi_remove,
1194 .suspend = fsl_qspi_suspend,
1195 .resume = fsl_qspi_resume,
1196};
1197module_platform_driver(fsl_qspi_driver);
1198
1199MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1200MODULE_AUTHOR("Freescale Semiconductor Inc.");
1201MODULE_LICENSE("GPL v2");