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1/*
2 * twl6030-irq.c - TWL6030 irq support
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * TWL6030 specific code and IRQ handling changes by
16 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
17 * Balaji T K <balajitk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 */
33
34#include <linux/init.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/kthread.h>
38#include <linux/i2c/twl.h>
39#include <linux/platform_device.h>
40
41#include "twl-core.h"
42
43/*
44 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
45 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
46 * It exposes status bits saying who has raised an interrupt. There are
47 * three mask registers that corresponds to these status registers, that
48 * enables/disables these interrupts.
49 *
50 * We set up IRQs starting at a platform-specified base. An interrupt map table,
51 * specifies mapping between interrupt number and the associated module.
52 *
53 */
54
55static int twl6030_interrupt_mapping[24] = {
56 PWR_INTR_OFFSET, /* Bit 0 PWRON */
57 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
58 PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
59 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
60 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
61 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
62 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
63 SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
64
65 SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
66 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
67 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
68 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
69 RSV_INTR_OFFSET, /* Bit 12 Reserved */
70 MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
71 MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
72 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
73
74 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
75 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
76 USBOTG_INTR_OFFSET, /* Bit 18 ID */
77 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
78 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
79 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
80 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
81 RSV_INTR_OFFSET, /* Bit 23 Reserved */
82};
83/*----------------------------------------------------------------------*/
84
85static unsigned twl6030_irq_base;
86
87static struct completion irq_event;
88
89/*
90 * This thread processes interrupts reported by the Primary Interrupt Handler.
91 */
92static int twl6030_irq_thread(void *data)
93{
94 long irq = (long)data;
95 static unsigned i2c_errors;
96 static const unsigned max_i2c_errors = 100;
97 int ret;
98
99 current->flags |= PF_NOFREEZE;
100
101 while (!kthread_should_stop()) {
102 int i;
103 union {
104 u8 bytes[4];
105 u32 int_sts;
106 } sts;
107
108 /* Wait for IRQ, then read PIH irq status (also blocking) */
109 wait_for_completion_interruptible(&irq_event);
110
111 /* read INT_STS_A, B and C in one shot using a burst read */
112 ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes,
113 REG_INT_STS_A, 3);
114 if (ret) {
115 pr_warning("twl6030: I2C error %d reading PIH ISR\n",
116 ret);
117 if (++i2c_errors >= max_i2c_errors) {
118 printk(KERN_ERR "Maximum I2C error count"
119 " exceeded. Terminating %s.\n",
120 __func__);
121 break;
122 }
123 complete(&irq_event);
124 continue;
125 }
126
127
128
129 sts.bytes[3] = 0; /* Only 24 bits are valid*/
130
131 /*
132 * Since VBUS status bit is not reliable for VBUS disconnect
133 * use CHARGER VBUS detection status bit instead.
134 */
135 if (sts.bytes[2] & 0x10)
136 sts.bytes[2] |= 0x08;
137
138 for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) {
139 local_irq_disable();
140 if (sts.int_sts & 0x1) {
141 int module_irq = twl6030_irq_base +
142 twl6030_interrupt_mapping[i];
143 generic_handle_irq(module_irq);
144
145 }
146 local_irq_enable();
147 }
148 ret = twl_i2c_write(TWL_MODULE_PIH, sts.bytes,
149 REG_INT_STS_A, 3); /* clear INT_STS_A */
150 if (ret)
151 pr_warning("twl6030: I2C error in clearing PIH ISR\n");
152
153 enable_irq(irq);
154 }
155
156 return 0;
157}
158
159/*
160 * handle_twl6030_int() is the desc->handle method for the twl6030 interrupt.
161 * This is a chained interrupt, so there is no desc->action method for it.
162 * Now we need to query the interrupt controller in the twl6030 to determine
163 * which module is generating the interrupt request. However, we can't do i2c
164 * transactions in interrupt context, so we must defer that work to a kernel
165 * thread. All we do here is acknowledge and mask the interrupt and wakeup
166 * the kernel thread.
167 */
168static irqreturn_t handle_twl6030_pih(int irq, void *devid)
169{
170 disable_irq_nosync(irq);
171 complete(devid);
172 return IRQ_HANDLED;
173}
174
175/*----------------------------------------------------------------------*/
176
177static inline void activate_irq(int irq)
178{
179#ifdef CONFIG_ARM
180 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
181 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
182 */
183 set_irq_flags(irq, IRQF_VALID);
184#else
185 /* same effect on other architectures */
186 irq_set_noprobe(irq);
187#endif
188}
189
190/*----------------------------------------------------------------------*/
191
192static unsigned twl6030_irq_next;
193
194/*----------------------------------------------------------------------*/
195int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
196{
197 int ret;
198 u8 unmask_value;
199 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
200 REG_INT_STS_A + offset);
201 unmask_value &= (~(bit_mask));
202 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
203 REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
204 return ret;
205}
206EXPORT_SYMBOL(twl6030_interrupt_unmask);
207
208int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
209{
210 int ret;
211 u8 mask_value;
212 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
213 REG_INT_STS_A + offset);
214 mask_value |= (bit_mask);
215 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
216 REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
217 return ret;
218}
219EXPORT_SYMBOL(twl6030_interrupt_mask);
220
221int twl6030_mmc_card_detect_config(void)
222{
223 int ret;
224 u8 reg_val = 0;
225
226 /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
227 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
228 REG_INT_MSK_LINE_B);
229 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
230 REG_INT_MSK_STS_B);
231 /*
232 * Initially Configuring MMC_CTRL for receiving interrupts &
233 * Card status on TWL6030 for MMC1
234 */
235 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
236 if (ret < 0) {
237 pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
238 return ret;
239 }
240 reg_val &= ~VMMC_AUTO_OFF;
241 reg_val |= SW_FC;
242 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
243 if (ret < 0) {
244 pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
245 return ret;
246 }
247
248 /* Configuring PullUp-PullDown register */
249 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
250 TWL6030_CFG_INPUT_PUPD3);
251 if (ret < 0) {
252 pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
253 ret);
254 return ret;
255 }
256 reg_val &= ~(MMC_PU | MMC_PD);
257 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
258 TWL6030_CFG_INPUT_PUPD3);
259 if (ret < 0) {
260 pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
261 ret);
262 return ret;
263 }
264 return 0;
265}
266EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
267
268int twl6030_mmc_card_detect(struct device *dev, int slot)
269{
270 int ret = -EIO;
271 u8 read_reg = 0;
272 struct platform_device *pdev = to_platform_device(dev);
273
274 if (pdev->id) {
275 /* TWL6030 provide's Card detect support for
276 * only MMC1 controller.
277 */
278 pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
279 return ret;
280 }
281 /*
282 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
283 * 0 - Card not present ,1 - Card present
284 */
285 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
286 TWL6030_MMCCTRL);
287 if (ret >= 0)
288 ret = read_reg & STS_MMC;
289 return ret;
290}
291EXPORT_SYMBOL(twl6030_mmc_card_detect);
292
293int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
294{
295
296 int status = 0;
297 int i;
298 struct task_struct *task;
299 int ret;
300 u8 mask[4];
301
302 static struct irq_chip twl6030_irq_chip;
303 mask[1] = 0xFF;
304 mask[2] = 0xFF;
305 mask[3] = 0xFF;
306 ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
307 REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
308 ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
309 REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
310 ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
311 REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
312
313 twl6030_irq_base = irq_base;
314
315 /* install an irq handler for each of the modules;
316 * clone dummy irq_chip since PIH can't *do* anything
317 */
318 twl6030_irq_chip = dummy_irq_chip;
319 twl6030_irq_chip.name = "twl6030";
320 twl6030_irq_chip.irq_set_type = NULL;
321
322 for (i = irq_base; i < irq_end; i++) {
323 irq_set_chip_and_handler(i, &twl6030_irq_chip,
324 handle_simple_irq);
325 activate_irq(i);
326 }
327
328 twl6030_irq_next = i;
329 pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
330 irq_num, irq_base, twl6030_irq_next - 1);
331
332 /* install an irq handler to demultiplex the TWL6030 interrupt */
333 init_completion(&irq_event);
334 task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
335 if (IS_ERR(task)) {
336 pr_err("twl6030: could not create irq %d thread!\n", irq_num);
337 status = PTR_ERR(task);
338 goto fail_kthread;
339 }
340
341 status = request_irq(irq_num, handle_twl6030_pih, IRQF_DISABLED,
342 "TWL6030-PIH", &irq_event);
343 if (status < 0) {
344 pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
345 goto fail_irq;
346 }
347 return status;
348fail_irq:
349 free_irq(irq_num, &irq_event);
350
351fail_kthread:
352 for (i = irq_base; i < irq_end; i++)
353 irq_set_chip_and_handler(i, NULL, NULL);
354 return status;
355}
356
357int twl6030_exit_irq(void)
358{
359
360 if (twl6030_irq_base) {
361 pr_err("twl6030: can't yet clean up IRQs?\n");
362 return -ENOSYS;
363 }
364 return 0;
365}
366
1/*
2 * twl6030-irq.c - TWL6030 irq support
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * TWL6030 specific code and IRQ handling changes by
16 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
17 * Balaji T K <balajitk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 */
33
34#include <linux/export.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/kthread.h>
38#include <linux/i2c/twl.h>
39#include <linux/platform_device.h>
40#include <linux/suspend.h>
41#include <linux/of.h>
42#include <linux/irqdomain.h>
43#include <linux/of_device.h>
44
45#include "twl-core.h"
46
47/*
48 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
49 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
50 * It exposes status bits saying who has raised an interrupt. There are
51 * three mask registers that corresponds to these status registers, that
52 * enables/disables these interrupts.
53 *
54 * We set up IRQs starting at a platform-specified base. An interrupt map table,
55 * specifies mapping between interrupt number and the associated module.
56 */
57#define TWL6030_NR_IRQS 20
58
59static int twl6030_interrupt_mapping[24] = {
60 PWR_INTR_OFFSET, /* Bit 0 PWRON */
61 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
62 PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
63 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
64 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
65 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
66 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
67 SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
68
69 SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
70 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
71 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
72 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
73 RSV_INTR_OFFSET, /* Bit 12 Reserved */
74 MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
75 MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
76 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
77
78 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
79 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
80 USBOTG_INTR_OFFSET, /* Bit 18 ID */
81 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
82 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
83 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
84 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
85 RSV_INTR_OFFSET, /* Bit 23 Reserved */
86};
87
88static int twl6032_interrupt_mapping[24] = {
89 PWR_INTR_OFFSET, /* Bit 0 PWRON */
90 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
91 PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
92 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
93 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
94 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
95 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
96 PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
97
98 PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
99 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
100 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
101 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
102 MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
103 MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
104 GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
105 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
106
107 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
108 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
109 USBOTG_INTR_OFFSET, /* Bit 18 ID */
110 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
111 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
112 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
113 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
114 RSV_INTR_OFFSET, /* Bit 23 Reserved */
115};
116
117/*----------------------------------------------------------------------*/
118
119struct twl6030_irq {
120 unsigned int irq_base;
121 int twl_irq;
122 bool irq_wake_enabled;
123 atomic_t wakeirqs;
124 struct notifier_block pm_nb;
125 struct irq_chip irq_chip;
126 struct irq_domain *irq_domain;
127 const int *irq_mapping_tbl;
128};
129
130static struct twl6030_irq *twl6030_irq;
131
132static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
133 unsigned long pm_event, void *unused)
134{
135 int chained_wakeups;
136 struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
137 pm_nb);
138
139 switch (pm_event) {
140 case PM_SUSPEND_PREPARE:
141 chained_wakeups = atomic_read(&pdata->wakeirqs);
142
143 if (chained_wakeups && !pdata->irq_wake_enabled) {
144 if (enable_irq_wake(pdata->twl_irq))
145 pr_err("twl6030 IRQ wake enable failed\n");
146 else
147 pdata->irq_wake_enabled = true;
148 } else if (!chained_wakeups && pdata->irq_wake_enabled) {
149 disable_irq_wake(pdata->twl_irq);
150 pdata->irq_wake_enabled = false;
151 }
152
153 disable_irq(pdata->twl_irq);
154 break;
155
156 case PM_POST_SUSPEND:
157 enable_irq(pdata->twl_irq);
158 break;
159
160 default:
161 break;
162 }
163
164 return NOTIFY_DONE;
165}
166
167/*
168* Threaded irq handler for the twl6030 interrupt.
169* We query the interrupt controller in the twl6030 to determine
170* which module is generating the interrupt request and call
171* handle_nested_irq for that module.
172*/
173static irqreturn_t twl6030_irq_thread(int irq, void *data)
174{
175 int i, ret;
176 union {
177 u8 bytes[4];
178 __le32 int_sts;
179 } sts;
180 u32 int_sts; /* sts.int_sts converted to CPU endianness */
181 struct twl6030_irq *pdata = data;
182
183 /* read INT_STS_A, B and C in one shot using a burst read */
184 ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
185 if (ret) {
186 pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
187 return IRQ_HANDLED;
188 }
189
190 sts.bytes[3] = 0; /* Only 24 bits are valid*/
191
192 /*
193 * Since VBUS status bit is not reliable for VBUS disconnect
194 * use CHARGER VBUS detection status bit instead.
195 */
196 if (sts.bytes[2] & 0x10)
197 sts.bytes[2] |= 0x08;
198
199 int_sts = le32_to_cpu(sts.int_sts);
200 for (i = 0; int_sts; int_sts >>= 1, i++)
201 if (int_sts & 0x1) {
202 int module_irq =
203 irq_find_mapping(pdata->irq_domain,
204 pdata->irq_mapping_tbl[i]);
205 if (module_irq)
206 handle_nested_irq(module_irq);
207 else
208 pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
209 i);
210 pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
211 i, module_irq);
212 }
213
214 /*
215 * NOTE:
216 * Simulation confirms that documentation is wrong w.r.t the
217 * interrupt status clear operation. A single *byte* write to
218 * any one of STS_A to STS_C register results in all three
219 * STS registers being reset. Since it does not matter which
220 * value is written, all three registers are cleared on a
221 * single byte write, so we just use 0x0 to clear.
222 */
223 ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
224 if (ret)
225 pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
226
227 return IRQ_HANDLED;
228}
229
230/*----------------------------------------------------------------------*/
231
232static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
233{
234 struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
235
236 if (on)
237 atomic_inc(&pdata->wakeirqs);
238 else
239 atomic_dec(&pdata->wakeirqs);
240
241 return 0;
242}
243
244int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
245{
246 int ret;
247 u8 unmask_value;
248
249 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
250 REG_INT_STS_A + offset);
251 unmask_value &= (~(bit_mask));
252 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
253 REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
254 return ret;
255}
256EXPORT_SYMBOL(twl6030_interrupt_unmask);
257
258int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
259{
260 int ret;
261 u8 mask_value;
262
263 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
264 REG_INT_STS_A + offset);
265 mask_value |= (bit_mask);
266 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
267 REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
268 return ret;
269}
270EXPORT_SYMBOL(twl6030_interrupt_mask);
271
272int twl6030_mmc_card_detect_config(void)
273{
274 int ret;
275 u8 reg_val = 0;
276
277 /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
278 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
279 REG_INT_MSK_LINE_B);
280 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
281 REG_INT_MSK_STS_B);
282 /*
283 * Initially Configuring MMC_CTRL for receiving interrupts &
284 * Card status on TWL6030 for MMC1
285 */
286 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
287 if (ret < 0) {
288 pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
289 return ret;
290 }
291 reg_val &= ~VMMC_AUTO_OFF;
292 reg_val |= SW_FC;
293 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
294 if (ret < 0) {
295 pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
296 return ret;
297 }
298
299 /* Configuring PullUp-PullDown register */
300 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
301 TWL6030_CFG_INPUT_PUPD3);
302 if (ret < 0) {
303 pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
304 ret);
305 return ret;
306 }
307 reg_val &= ~(MMC_PU | MMC_PD);
308 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
309 TWL6030_CFG_INPUT_PUPD3);
310 if (ret < 0) {
311 pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
312 ret);
313 return ret;
314 }
315
316 return irq_find_mapping(twl6030_irq->irq_domain,
317 MMCDETECT_INTR_OFFSET);
318}
319EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
320
321int twl6030_mmc_card_detect(struct device *dev, int slot)
322{
323 int ret = -EIO;
324 u8 read_reg = 0;
325 struct platform_device *pdev = to_platform_device(dev);
326
327 if (pdev->id) {
328 /* TWL6030 provide's Card detect support for
329 * only MMC1 controller.
330 */
331 pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
332 return ret;
333 }
334 /*
335 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
336 * 0 - Card not present ,1 - Card present
337 */
338 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
339 TWL6030_MMCCTRL);
340 if (ret >= 0)
341 ret = read_reg & STS_MMC;
342 return ret;
343}
344EXPORT_SYMBOL(twl6030_mmc_card_detect);
345
346static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
347 irq_hw_number_t hwirq)
348{
349 struct twl6030_irq *pdata = d->host_data;
350
351 irq_set_chip_data(virq, pdata);
352 irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
353 irq_set_nested_thread(virq, true);
354 irq_set_parent(virq, pdata->twl_irq);
355 irq_set_noprobe(virq);
356
357 return 0;
358}
359
360static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
361{
362 irq_set_chip_and_handler(virq, NULL, NULL);
363 irq_set_chip_data(virq, NULL);
364}
365
366static const struct irq_domain_ops twl6030_irq_domain_ops = {
367 .map = twl6030_irq_map,
368 .unmap = twl6030_irq_unmap,
369 .xlate = irq_domain_xlate_onetwocell,
370};
371
372static const struct of_device_id twl6030_of_match[] = {
373 {.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
374 {.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
375 { },
376};
377
378int twl6030_init_irq(struct device *dev, int irq_num)
379{
380 struct device_node *node = dev->of_node;
381 int nr_irqs;
382 int status;
383 u8 mask[3];
384 const struct of_device_id *of_id;
385
386 of_id = of_match_device(twl6030_of_match, dev);
387 if (!of_id || !of_id->data) {
388 dev_err(dev, "Unknown TWL device model\n");
389 return -EINVAL;
390 }
391
392 nr_irqs = TWL6030_NR_IRQS;
393
394 twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
395 if (!twl6030_irq) {
396 dev_err(dev, "twl6030_irq: Memory allocation failed\n");
397 return -ENOMEM;
398 }
399
400 mask[0] = 0xFF;
401 mask[1] = 0xFF;
402 mask[2] = 0xFF;
403
404 /* mask all int lines */
405 status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
406 /* mask all int sts */
407 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
408 /* clear INT_STS_A,B,C */
409 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
410
411 if (status < 0) {
412 dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
413 return status;
414 }
415
416 /*
417 * install an irq handler for each of the modules;
418 * clone dummy irq_chip since PIH can't *do* anything
419 */
420 twl6030_irq->irq_chip = dummy_irq_chip;
421 twl6030_irq->irq_chip.name = "twl6030";
422 twl6030_irq->irq_chip.irq_set_type = NULL;
423 twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
424
425 twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
426 atomic_set(&twl6030_irq->wakeirqs, 0);
427 twl6030_irq->irq_mapping_tbl = of_id->data;
428
429 twl6030_irq->irq_domain =
430 irq_domain_add_linear(node, nr_irqs,
431 &twl6030_irq_domain_ops, twl6030_irq);
432 if (!twl6030_irq->irq_domain) {
433 dev_err(dev, "Can't add irq_domain\n");
434 return -ENOMEM;
435 }
436
437 dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
438
439 /* install an irq handler to demultiplex the TWL6030 interrupt */
440 status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
441 IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
442 if (status < 0) {
443 dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
444 goto fail_irq;
445 }
446
447 twl6030_irq->twl_irq = irq_num;
448 register_pm_notifier(&twl6030_irq->pm_nb);
449 return 0;
450
451fail_irq:
452 irq_domain_remove(twl6030_irq->irq_domain);
453 return status;
454}
455
456int twl6030_exit_irq(void)
457{
458 if (twl6030_irq && twl6030_irq->twl_irq) {
459 unregister_pm_notifier(&twl6030_irq->pm_nb);
460 free_irq(twl6030_irq->twl_irq, NULL);
461 /*
462 * TODO: IRQ domain and allocated nested IRQ descriptors
463 * should be freed somehow here. Now It can't be done, because
464 * child devices will not be deleted during removing of
465 * TWL Core driver and they will still contain allocated
466 * virt IRQs in their Resources tables.
467 * The same prevents us from using devm_request_threaded_irq()
468 * in this module.
469 */
470 }
471 return 0;
472}
473