1/* Driver for Realtek PCI-Express card reader
  2 *
  3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License as published by the
  7 * Free Software Foundation; either version 2, or (at your option) any
  8 * later version.
  9 *
 10 * This program is distributed in the hope that it will be useful, but
 11 * WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 13 * General Public License for more details.
 14 *
 15 * You should have received a copy of the GNU General Public License along
 16 * with this program; if not, see <http://www.gnu.org/licenses/>.
 17 *
 18 * Author:
 19 *   Wei WANG <wei_wang@realsil.com.cn>
 20 */
 21
 22#include <linux/module.h>
 23#include <linux/delay.h>
 24#include <linux/mfd/rtsx_pci.h>
 25
 26#include "rtsx_pcr.h"
 27
 28static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
 29{
 30	u8 val;
 31
 32	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
 33	return val & 0x0F;
 34}
 35
 36static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
 37{
 38	u32 reg;
 39
 40	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
 41	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 42
 43	if (!rtsx_vendor_setting_valid(reg))
 44		return;
 45
 46	pcr->aspm_en = rtsx_reg_to_aspm(reg);
 47	pcr->sd30_drive_sel_1v8 =
 48		map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
 49	pcr->card_drive_sel &= 0x3F;
 50	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
 51
 52	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
 53	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
 54	pcr->sd30_drive_sel_3v3 =
 55		map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg));
 56}
 57
 58static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
 59{
 60	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
 61}
 62
 63static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
 64{
 65	rtsx_pci_init_cmd(pcr);
 66
 67	/* Configure GPIO as output */
 68	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 69	/* Reset ASPM state to default value */
 70	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 71	/* Force CLKREQ# PIN to drive 0 to request clock */
 72	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 73	/* Switch LDO3318 source from DV33 to card_3v3 */
 74	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 75	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 76	/* LED shine disabled, set initial shine cycle period */
 77	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 78	/* Configure driving */
 79	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 80			0xFF, pcr->sd30_drive_sel_3v3);
 81
 82	return rtsx_pci_send_cmd(pcr, 100);
 83}
 84
 85static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
 86{
 87	/* Optimize RX sensitivity */
 88	return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
 89}
 90
 91static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
 92{
 93	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 94}
 95
 96static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
 97{
 98	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 99}
100
101static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
102{
103	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
104}
105
106static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
107{
108	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
109}
110
111static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card)
112{
113	int err;
114
115	rtsx_pci_init_cmd(pcr);
116	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
117			SD_POWER_MASK, SD_PARTIAL_POWER_ON);
118	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
119			LDO3318_PWR_MASK, 0x02);
120	err = rtsx_pci_send_cmd(pcr, 100);
121	if (err < 0)
122		return err;
123
124	/* To avoid too large in-rush current */
125	udelay(150);
126
127	rtsx_pci_init_cmd(pcr);
128	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
129			SD_POWER_MASK, SD_POWER_ON);
130	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
131			LDO3318_PWR_MASK, 0x06);
132	return rtsx_pci_send_cmd(pcr, 100);
133}
134
135static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card)
136{
137	rtsx_pci_init_cmd(pcr);
138	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
139			SD_POWER_MASK | PMOS_STRG_MASK,
140			SD_POWER_OFF | PMOS_STRG_400mA);
141	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
142			LDO3318_PWR_MASK, 0x00);
143	return rtsx_pci_send_cmd(pcr, 100);
144}
145
146static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
147{
148	int err;
149
150	if (voltage == OUTPUT_3V3) {
151		err = rtsx_pci_write_register(pcr,
152				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
153		if (err < 0)
154			return err;
155		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
156		if (err < 0)
157			return err;
158	} else if (voltage == OUTPUT_1V8) {
159		err = rtsx_pci_write_register(pcr,
160				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
161		if (err < 0)
162			return err;
163		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
164		if (err < 0)
165			return err;
166	} else {
167		return -EINVAL;
168	}
169
170	return 0;
171}
172
173static const struct pcr_ops rts5229_pcr_ops = {
174	.fetch_vendor_settings = rts5229_fetch_vendor_settings,
175	.extra_init_hw = rts5229_extra_init_hw,
176	.optimize_phy = rts5229_optimize_phy,
177	.turn_on_led = rts5229_turn_on_led,
178	.turn_off_led = rts5229_turn_off_led,
179	.enable_auto_blink = rts5229_enable_auto_blink,
180	.disable_auto_blink = rts5229_disable_auto_blink,
181	.card_power_on = rts5229_card_power_on,
182	.card_power_off = rts5229_card_power_off,
183	.switch_output_voltage = rts5229_switch_output_voltage,
184	.cd_deglitch = NULL,
185	.conv_clk_and_div_n = NULL,
186	.force_power_down = rts5229_force_power_down,
187};
188
189/* SD Pull Control Enable:
190 *     SD_DAT[3:0] ==> pull up
191 *     SD_CD       ==> pull up
192 *     SD_WP       ==> pull up
193 *     SD_CMD      ==> pull up
194 *     SD_CLK      ==> pull down
195 */
196static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = {
197	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
198	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
199	0,
200};
201
202/* For RTS5229 version C */
203static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = {
204	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
205	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9),
206	0,
207};
208
209/* SD Pull Control Disable:
210 *     SD_DAT[3:0] ==> pull down
211 *     SD_CD       ==> pull up
212 *     SD_WP       ==> pull down
213 *     SD_CMD      ==> pull down
214 *     SD_CLK      ==> pull down
215 */
216static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = {
217	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
218	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
219	0,
220};
221
222/* For RTS5229 version C */
223static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = {
224	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
225	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5),
226	0,
227};
228
229/* MS Pull Control Enable:
230 *     MS CD       ==> pull up
231 *     others      ==> pull down
232 */
233static const u32 rts5229_ms_pull_ctl_enable_tbl[] = {
234	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
235	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
236	0,
237};
238
239/* MS Pull Control Disable:
240 *     MS CD       ==> pull up
241 *     others      ==> pull down
242 */
243static const u32 rts5229_ms_pull_ctl_disable_tbl[] = {
244	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
245	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
246	0,
247};
248
249void rts5229_init_params(struct rtsx_pcr *pcr)
250{
251	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
252	pcr->num_slots = 2;
253	pcr->ops = &rts5229_pcr_ops;
254
255	pcr->flags = 0;
256	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
257	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
258	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
259	pcr->aspm_en = ASPM_L1_EN;
260	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
261	pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);
262
263	pcr->ic_version = rts5229_get_ic_version(pcr);
264	if (pcr->ic_version == IC_VER_C) {
265		pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2;
266		pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2;
267	} else {
268		pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1;
269		pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1;
270	}
271	pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl;
272	pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl;
273}