1/*
  2 * Copyright (c) 2014 MediaTek Inc.
  3 * Author: Flora Fu, MediaTek
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 */
 14
 15#include <linux/interrupt.h>
 16#include <linux/module.h>
 17#include <linux/of_device.h>
 18#include <linux/of_irq.h>
 19#include <linux/regmap.h>
 20#include <linux/mfd/core.h>
 21#include <linux/mfd/mt6397/core.h>
 22#include <linux/mfd/mt6323/core.h>
 23#include <linux/mfd/mt6397/registers.h>
 24#include <linux/mfd/mt6323/registers.h>
 25
 26#define MT6397_RTC_BASE		0xe000
 27#define MT6397_RTC_SIZE		0x3e
 28
 29#define MT6323_CID_CODE		0x23
 30#define MT6391_CID_CODE		0x91
 31#define MT6397_CID_CODE		0x97
 32
 33static const struct resource mt6397_rtc_resources[] = {
 34	{
 35		.start = MT6397_RTC_BASE,
 36		.end   = MT6397_RTC_BASE + MT6397_RTC_SIZE,
 37		.flags = IORESOURCE_MEM,
 38	},
 39	{
 40		.start = MT6397_IRQ_RTC,
 41		.end   = MT6397_IRQ_RTC,
 42		.flags = IORESOURCE_IRQ,
 43	},
 44};
 45
 46static const struct mfd_cell mt6323_devs[] = {
 47	{
 48		.name = "mt6323-regulator",
 49		.of_compatible = "mediatek,mt6323-regulator"
 50	},
 51};
 52
 53static const struct mfd_cell mt6397_devs[] = {
 54	{
 55		.name = "mt6397-rtc",
 56		.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
 57		.resources = mt6397_rtc_resources,
 58		.of_compatible = "mediatek,mt6397-rtc",
 59	}, {
 60		.name = "mt6397-regulator",
 61		.of_compatible = "mediatek,mt6397-regulator",
 62	}, {
 63		.name = "mt6397-codec",
 64		.of_compatible = "mediatek,mt6397-codec",
 65	}, {
 66		.name = "mt6397-clk",
 67		.of_compatible = "mediatek,mt6397-clk",
 68	}, {
 69		.name = "mt6397-pinctrl",
 70		.of_compatible = "mediatek,mt6397-pinctrl",
 71	},
 72};
 73
 74static void mt6397_irq_lock(struct irq_data *data)
 75{
 76	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
 77
 78	mutex_lock(&mt6397->irqlock);
 79}
 80
 81static void mt6397_irq_sync_unlock(struct irq_data *data)
 82{
 83	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
 84
 85	regmap_write(mt6397->regmap, mt6397->int_con[0],
 86		     mt6397->irq_masks_cur[0]);
 87	regmap_write(mt6397->regmap, mt6397->int_con[1],
 88		     mt6397->irq_masks_cur[1]);
 89
 90	mutex_unlock(&mt6397->irqlock);
 91}
 92
 93static void mt6397_irq_disable(struct irq_data *data)
 94{
 95	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
 96	int shift = data->hwirq & 0xf;
 97	int reg = data->hwirq >> 4;
 98
 99	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
100}
101
102static void mt6397_irq_enable(struct irq_data *data)
103{
104	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
105	int shift = data->hwirq & 0xf;
106	int reg = data->hwirq >> 4;
107
108	mt6397->irq_masks_cur[reg] |= BIT(shift);
109}
110
111#ifdef CONFIG_PM_SLEEP
112static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
113{
114	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
115	int shift = irq_data->hwirq & 0xf;
116	int reg = irq_data->hwirq >> 4;
117
118	if (on)
119		mt6397->wake_mask[reg] |= BIT(shift);
120	else
121		mt6397->wake_mask[reg] &= ~BIT(shift);
122
123	return 0;
124}
125#else
126#define mt6397_irq_set_wake NULL
127#endif
128
129static struct irq_chip mt6397_irq_chip = {
130	.name = "mt6397-irq",
131	.irq_bus_lock = mt6397_irq_lock,
132	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
133	.irq_enable = mt6397_irq_enable,
134	.irq_disable = mt6397_irq_disable,
135	.irq_set_wake = mt6397_irq_set_wake,
136};
137
138static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
139		int irqbase)
140{
141	unsigned int status;
142	int i, irq, ret;
143
144	ret = regmap_read(mt6397->regmap, reg, &status);
145	if (ret) {
146		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
147		return;
148	}
149
150	for (i = 0; i < 16; i++) {
151		if (status & BIT(i)) {
152			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
153			if (irq)
154				handle_nested_irq(irq);
155		}
156	}
157
158	regmap_write(mt6397->regmap, reg, status);
159}
160
161static irqreturn_t mt6397_irq_thread(int irq, void *data)
162{
163	struct mt6397_chip *mt6397 = data;
164
165	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
166	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
167
168	return IRQ_HANDLED;
169}
170
171static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
172					irq_hw_number_t hw)
173{
174	struct mt6397_chip *mt6397 = d->host_data;
175
176	irq_set_chip_data(irq, mt6397);
177	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
178	irq_set_nested_thread(irq, 1);
179	irq_set_noprobe(irq);
180
181	return 0;
182}
183
184static const struct irq_domain_ops mt6397_irq_domain_ops = {
185	.map = mt6397_irq_domain_map,
186};
187
188static int mt6397_irq_init(struct mt6397_chip *mt6397)
189{
190	int ret;
191
192	mutex_init(&mt6397->irqlock);
193
194	/* Mask all interrupt sources */
195	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
196	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
197
198	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
199		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
200	if (!mt6397->irq_domain) {
201		dev_err(mt6397->dev, "could not create irq domain\n");
202		return -ENOMEM;
203	}
204
205	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
206		mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
207	if (ret) {
208		dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
209			mt6397->irq, ret);
210		return ret;
211	}
212
213	return 0;
214}
215
216#ifdef CONFIG_PM_SLEEP
217static int mt6397_irq_suspend(struct device *dev)
218{
219	struct mt6397_chip *chip = dev_get_drvdata(dev);
220
221	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
222	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
223
224	enable_irq_wake(chip->irq);
225
226	return 0;
227}
228
229static int mt6397_irq_resume(struct device *dev)
230{
231	struct mt6397_chip *chip = dev_get_drvdata(dev);
232
233	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
234	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
235
236	disable_irq_wake(chip->irq);
237
238	return 0;
239}
240#endif
241
242static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
243			mt6397_irq_resume);
244
245static int mt6397_probe(struct platform_device *pdev)
246{
247	int ret;
248	unsigned int id;
249	struct mt6397_chip *pmic;
250
251	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
252	if (!pmic)
253		return -ENOMEM;
254
255	pmic->dev = &pdev->dev;
256
257	/*
258	 * mt6397 MFD is child device of soc pmic wrapper.
259	 * Regmap is set from its parent.
260	 */
261	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
262	if (!pmic->regmap)
263		return -ENODEV;
264
265	platform_set_drvdata(pdev, pmic);
266
267	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
268	if (ret) {
269		dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
270		return ret;
271	}
272
273	pmic->irq = platform_get_irq(pdev, 0);
274	if (pmic->irq <= 0)
275		return pmic->irq;
276
277	switch (id & 0xff) {
278	case MT6323_CID_CODE:
279		pmic->int_con[0] = MT6323_INT_CON0;
280		pmic->int_con[1] = MT6323_INT_CON1;
281		pmic->int_status[0] = MT6323_INT_STATUS0;
282		pmic->int_status[1] = MT6323_INT_STATUS1;
283		ret = mt6397_irq_init(pmic);
284		if (ret)
285			return ret;
286
287		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
288					   ARRAY_SIZE(mt6323_devs), NULL,
289					   0, NULL);
290		break;
291
292	case MT6397_CID_CODE:
293	case MT6391_CID_CODE:
294		pmic->int_con[0] = MT6397_INT_CON0;
295		pmic->int_con[1] = MT6397_INT_CON1;
296		pmic->int_status[0] = MT6397_INT_STATUS0;
297		pmic->int_status[1] = MT6397_INT_STATUS1;
298		ret = mt6397_irq_init(pmic);
299		if (ret)
300			return ret;
301
302		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
303					   ARRAY_SIZE(mt6397_devs), NULL,
304					   0, NULL);
305		break;
306
307	default:
308		dev_err(&pdev->dev, "unsupported chip: %d\n", id);
309		ret = -ENODEV;
310		break;
311	}
312
313	if (ret) {
314		irq_domain_remove(pmic->irq_domain);
315		dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
316	}
317
318	return ret;
319}
320
321static const struct of_device_id mt6397_of_match[] = {
322	{ .compatible = "mediatek,mt6397" },
323	{ .compatible = "mediatek,mt6323" },
324	{ }
325};
326MODULE_DEVICE_TABLE(of, mt6397_of_match);
327
328static const struct platform_device_id mt6397_id[] = {
329	{ "mt6397", 0 },
330	{ },
331};
332MODULE_DEVICE_TABLE(platform, mt6397_id);
333
334static struct platform_driver mt6397_driver = {
335	.probe = mt6397_probe,
336	.driver = {
337		.name = "mt6397",
338		.of_match_table = of_match_ptr(mt6397_of_match),
339		.pm = &mt6397_pm_ops,
340	},
341	.id_table = mt6397_id,
342};
343
344module_platform_driver(mt6397_driver);
345
346MODULE_AUTHOR("Flora Fu, MediaTek");
347MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
348MODULE_LICENSE("GPL");