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1/* linux/drivers/i2c/busses/i2c-s3c2410.c
2 *
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 I2C Controller
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25
26#include <linux/i2c.h>
27#include <linux/init.h>
28#include <linux/time.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/err.h>
33#include <linux/platform_device.h>
34#include <linux/clk.h>
35#include <linux/cpufreq.h>
36#include <linux/slab.h>
37#include <linux/io.h>
38
39#include <asm/irq.h>
40
41#include <plat/regs-iic.h>
42#include <plat/iic.h>
43
44/* i2c controller state */
45
46enum s3c24xx_i2c_state {
47 STATE_IDLE,
48 STATE_START,
49 STATE_READ,
50 STATE_WRITE,
51 STATE_STOP
52};
53
54enum s3c24xx_i2c_type {
55 TYPE_S3C2410,
56 TYPE_S3C2440,
57};
58
59struct s3c24xx_i2c {
60 spinlock_t lock;
61 wait_queue_head_t wait;
62 unsigned int suspended:1;
63
64 struct i2c_msg *msg;
65 unsigned int msg_num;
66 unsigned int msg_idx;
67 unsigned int msg_ptr;
68
69 unsigned int tx_setup;
70 unsigned int irq;
71
72 enum s3c24xx_i2c_state state;
73 unsigned long clkrate;
74
75 void __iomem *regs;
76 struct clk *clk;
77 struct device *dev;
78 struct resource *ioarea;
79 struct i2c_adapter adap;
80
81#ifdef CONFIG_CPU_FREQ
82 struct notifier_block freq_transition;
83#endif
84};
85
86/* default platform data removed, dev should always carry data. */
87
88/* s3c24xx_i2c_is2440()
89 *
90 * return true is this is an s3c2440
91*/
92
93static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
94{
95 struct platform_device *pdev = to_platform_device(i2c->dev);
96 enum s3c24xx_i2c_type type;
97
98 type = platform_get_device_id(pdev)->driver_data;
99 return type == TYPE_S3C2440;
100}
101
102/* s3c24xx_i2c_master_complete
103 *
104 * complete the message and wake up the caller, using the given return code,
105 * or zero to mean ok.
106*/
107
108static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
109{
110 dev_dbg(i2c->dev, "master_complete %d\n", ret);
111
112 i2c->msg_ptr = 0;
113 i2c->msg = NULL;
114 i2c->msg_idx++;
115 i2c->msg_num = 0;
116 if (ret)
117 i2c->msg_idx = ret;
118
119 wake_up(&i2c->wait);
120}
121
122static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
123{
124 unsigned long tmp;
125
126 tmp = readl(i2c->regs + S3C2410_IICCON);
127 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
128}
129
130static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
131{
132 unsigned long tmp;
133
134 tmp = readl(i2c->regs + S3C2410_IICCON);
135 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
136}
137
138/* irq enable/disable functions */
139
140static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
141{
142 unsigned long tmp;
143
144 tmp = readl(i2c->regs + S3C2410_IICCON);
145 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
146}
147
148static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
149{
150 unsigned long tmp;
151
152 tmp = readl(i2c->regs + S3C2410_IICCON);
153 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
154}
155
156
157/* s3c24xx_i2c_message_start
158 *
159 * put the start of a message onto the bus
160*/
161
162static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
163 struct i2c_msg *msg)
164{
165 unsigned int addr = (msg->addr & 0x7f) << 1;
166 unsigned long stat;
167 unsigned long iiccon;
168
169 stat = 0;
170 stat |= S3C2410_IICSTAT_TXRXEN;
171
172 if (msg->flags & I2C_M_RD) {
173 stat |= S3C2410_IICSTAT_MASTER_RX;
174 addr |= 1;
175 } else
176 stat |= S3C2410_IICSTAT_MASTER_TX;
177
178 if (msg->flags & I2C_M_REV_DIR_ADDR)
179 addr ^= 1;
180
181 /* todo - check for wether ack wanted or not */
182 s3c24xx_i2c_enable_ack(i2c);
183
184 iiccon = readl(i2c->regs + S3C2410_IICCON);
185 writel(stat, i2c->regs + S3C2410_IICSTAT);
186
187 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
188 writeb(addr, i2c->regs + S3C2410_IICDS);
189
190 /* delay here to ensure the data byte has gotten onto the bus
191 * before the transaction is started */
192
193 ndelay(i2c->tx_setup);
194
195 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
196 writel(iiccon, i2c->regs + S3C2410_IICCON);
197
198 stat |= S3C2410_IICSTAT_START;
199 writel(stat, i2c->regs + S3C2410_IICSTAT);
200}
201
202static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
203{
204 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
205
206 dev_dbg(i2c->dev, "STOP\n");
207
208 /* stop the transfer */
209 iicstat &= ~S3C2410_IICSTAT_START;
210 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
211
212 i2c->state = STATE_STOP;
213
214 s3c24xx_i2c_master_complete(i2c, ret);
215 s3c24xx_i2c_disable_irq(i2c);
216}
217
218/* helper functions to determine the current state in the set of
219 * messages we are sending */
220
221/* is_lastmsg()
222 *
223 * returns TRUE if the current message is the last in the set
224*/
225
226static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
227{
228 return i2c->msg_idx >= (i2c->msg_num - 1);
229}
230
231/* is_msglast
232 *
233 * returns TRUE if we this is the last byte in the current message
234*/
235
236static inline int is_msglast(struct s3c24xx_i2c *i2c)
237{
238 return i2c->msg_ptr == i2c->msg->len-1;
239}
240
241/* is_msgend
242 *
243 * returns TRUE if we reached the end of the current message
244*/
245
246static inline int is_msgend(struct s3c24xx_i2c *i2c)
247{
248 return i2c->msg_ptr >= i2c->msg->len;
249}
250
251/* i2c_s3c_irq_nextbyte
252 *
253 * process an interrupt and work out what to do
254 */
255
256static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
257{
258 unsigned long tmp;
259 unsigned char byte;
260 int ret = 0;
261
262 switch (i2c->state) {
263
264 case STATE_IDLE:
265 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
266 goto out;
267
268 case STATE_STOP:
269 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
270 s3c24xx_i2c_disable_irq(i2c);
271 goto out_ack;
272
273 case STATE_START:
274 /* last thing we did was send a start condition on the
275 * bus, or started a new i2c message
276 */
277
278 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
279 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
280 /* ack was not received... */
281
282 dev_dbg(i2c->dev, "ack was not received\n");
283 s3c24xx_i2c_stop(i2c, -ENXIO);
284 goto out_ack;
285 }
286
287 if (i2c->msg->flags & I2C_M_RD)
288 i2c->state = STATE_READ;
289 else
290 i2c->state = STATE_WRITE;
291
292 /* terminate the transfer if there is nothing to do
293 * as this is used by the i2c probe to find devices. */
294
295 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
296 s3c24xx_i2c_stop(i2c, 0);
297 goto out_ack;
298 }
299
300 if (i2c->state == STATE_READ)
301 goto prepare_read;
302
303 /* fall through to the write state, as we will need to
304 * send a byte as well */
305
306 case STATE_WRITE:
307 /* we are writing data to the device... check for the
308 * end of the message, and if so, work out what to do
309 */
310
311 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
312 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
313 dev_dbg(i2c->dev, "WRITE: No Ack\n");
314
315 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
316 goto out_ack;
317 }
318 }
319
320 retry_write:
321
322 if (!is_msgend(i2c)) {
323 byte = i2c->msg->buf[i2c->msg_ptr++];
324 writeb(byte, i2c->regs + S3C2410_IICDS);
325
326 /* delay after writing the byte to allow the
327 * data setup time on the bus, as writing the
328 * data to the register causes the first bit
329 * to appear on SDA, and SCL will change as
330 * soon as the interrupt is acknowledged */
331
332 ndelay(i2c->tx_setup);
333
334 } else if (!is_lastmsg(i2c)) {
335 /* we need to go to the next i2c message */
336
337 dev_dbg(i2c->dev, "WRITE: Next Message\n");
338
339 i2c->msg_ptr = 0;
340 i2c->msg_idx++;
341 i2c->msg++;
342
343 /* check to see if we need to do another message */
344 if (i2c->msg->flags & I2C_M_NOSTART) {
345
346 if (i2c->msg->flags & I2C_M_RD) {
347 /* cannot do this, the controller
348 * forces us to send a new START
349 * when we change direction */
350
351 s3c24xx_i2c_stop(i2c, -EINVAL);
352 }
353
354 goto retry_write;
355 } else {
356 /* send the new start */
357 s3c24xx_i2c_message_start(i2c, i2c->msg);
358 i2c->state = STATE_START;
359 }
360
361 } else {
362 /* send stop */
363
364 s3c24xx_i2c_stop(i2c, 0);
365 }
366 break;
367
368 case STATE_READ:
369 /* we have a byte of data in the data register, do
370 * something with it, and then work out wether we are
371 * going to do any more read/write
372 */
373
374 byte = readb(i2c->regs + S3C2410_IICDS);
375 i2c->msg->buf[i2c->msg_ptr++] = byte;
376
377 prepare_read:
378 if (is_msglast(i2c)) {
379 /* last byte of buffer */
380
381 if (is_lastmsg(i2c))
382 s3c24xx_i2c_disable_ack(i2c);
383
384 } else if (is_msgend(i2c)) {
385 /* ok, we've read the entire buffer, see if there
386 * is anything else we need to do */
387
388 if (is_lastmsg(i2c)) {
389 /* last message, send stop and complete */
390 dev_dbg(i2c->dev, "READ: Send Stop\n");
391
392 s3c24xx_i2c_stop(i2c, 0);
393 } else {
394 /* go to the next transfer */
395 dev_dbg(i2c->dev, "READ: Next Transfer\n");
396
397 i2c->msg_ptr = 0;
398 i2c->msg_idx++;
399 i2c->msg++;
400 }
401 }
402
403 break;
404 }
405
406 /* acknowlegde the IRQ and get back on with the work */
407
408 out_ack:
409 tmp = readl(i2c->regs + S3C2410_IICCON);
410 tmp &= ~S3C2410_IICCON_IRQPEND;
411 writel(tmp, i2c->regs + S3C2410_IICCON);
412 out:
413 return ret;
414}
415
416/* s3c24xx_i2c_irq
417 *
418 * top level IRQ servicing routine
419*/
420
421static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
422{
423 struct s3c24xx_i2c *i2c = dev_id;
424 unsigned long status;
425 unsigned long tmp;
426
427 status = readl(i2c->regs + S3C2410_IICSTAT);
428
429 if (status & S3C2410_IICSTAT_ARBITR) {
430 /* deal with arbitration loss */
431 dev_err(i2c->dev, "deal with arbitration loss\n");
432 }
433
434 if (i2c->state == STATE_IDLE) {
435 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
436
437 tmp = readl(i2c->regs + S3C2410_IICCON);
438 tmp &= ~S3C2410_IICCON_IRQPEND;
439 writel(tmp, i2c->regs + S3C2410_IICCON);
440 goto out;
441 }
442
443 /* pretty much this leaves us with the fact that we've
444 * transmitted or received whatever byte we last sent */
445
446 i2c_s3c_irq_nextbyte(i2c, status);
447
448 out:
449 return IRQ_HANDLED;
450}
451
452
453/* s3c24xx_i2c_set_master
454 *
455 * get the i2c bus for a master transaction
456*/
457
458static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
459{
460 unsigned long iicstat;
461 int timeout = 400;
462
463 while (timeout-- > 0) {
464 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
465
466 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
467 return 0;
468
469 msleep(1);
470 }
471
472 return -ETIMEDOUT;
473}
474
475/* s3c24xx_i2c_doxfer
476 *
477 * this starts an i2c transfer
478*/
479
480static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
481 struct i2c_msg *msgs, int num)
482{
483 unsigned long iicstat, timeout;
484 int spins = 20;
485 int ret;
486
487 if (i2c->suspended)
488 return -EIO;
489
490 ret = s3c24xx_i2c_set_master(i2c);
491 if (ret != 0) {
492 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
493 ret = -EAGAIN;
494 goto out;
495 }
496
497 spin_lock_irq(&i2c->lock);
498
499 i2c->msg = msgs;
500 i2c->msg_num = num;
501 i2c->msg_ptr = 0;
502 i2c->msg_idx = 0;
503 i2c->state = STATE_START;
504
505 s3c24xx_i2c_enable_irq(i2c);
506 s3c24xx_i2c_message_start(i2c, msgs);
507 spin_unlock_irq(&i2c->lock);
508
509 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
510
511 ret = i2c->msg_idx;
512
513 /* having these next two as dev_err() makes life very
514 * noisy when doing an i2cdetect */
515
516 if (timeout == 0)
517 dev_dbg(i2c->dev, "timeout\n");
518 else if (ret != num)
519 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
520
521 /* ensure the stop has been through the bus */
522
523 dev_dbg(i2c->dev, "waiting for bus idle\n");
524
525 /* first, try busy waiting briefly */
526 do {
527 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
528 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
529
530 /* if that timed out sleep */
531 if (!spins) {
532 msleep(1);
533 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
534 }
535
536 if (iicstat & S3C2410_IICSTAT_START)
537 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
538
539 out:
540 return ret;
541}
542
543/* s3c24xx_i2c_xfer
544 *
545 * first port of call from the i2c bus code when an message needs
546 * transferring across the i2c bus.
547*/
548
549static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
550 struct i2c_msg *msgs, int num)
551{
552 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
553 int retry;
554 int ret;
555
556 clk_enable(i2c->clk);
557
558 for (retry = 0; retry < adap->retries; retry++) {
559
560 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
561
562 if (ret != -EAGAIN) {
563 clk_disable(i2c->clk);
564 return ret;
565 }
566
567 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
568
569 udelay(100);
570 }
571
572 clk_disable(i2c->clk);
573 return -EREMOTEIO;
574}
575
576/* declare our i2c functionality */
577static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
578{
579 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
580}
581
582/* i2c bus registration info */
583
584static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
585 .master_xfer = s3c24xx_i2c_xfer,
586 .functionality = s3c24xx_i2c_func,
587};
588
589/* s3c24xx_i2c_calcdivisor
590 *
591 * return the divisor settings for a given frequency
592*/
593
594static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
595 unsigned int *div1, unsigned int *divs)
596{
597 unsigned int calc_divs = clkin / wanted;
598 unsigned int calc_div1;
599
600 if (calc_divs > (16*16))
601 calc_div1 = 512;
602 else
603 calc_div1 = 16;
604
605 calc_divs += calc_div1-1;
606 calc_divs /= calc_div1;
607
608 if (calc_divs == 0)
609 calc_divs = 1;
610 if (calc_divs > 17)
611 calc_divs = 17;
612
613 *divs = calc_divs;
614 *div1 = calc_div1;
615
616 return clkin / (calc_divs * calc_div1);
617}
618
619/* s3c24xx_i2c_clockrate
620 *
621 * work out a divisor for the user requested frequency setting,
622 * either by the requested frequency, or scanning the acceptable
623 * range of frequencies until something is found
624*/
625
626static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
627{
628 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
629 unsigned long clkin = clk_get_rate(i2c->clk);
630 unsigned int divs, div1;
631 unsigned long target_frequency;
632 u32 iiccon;
633 int freq;
634
635 i2c->clkrate = clkin;
636 clkin /= 1000; /* clkin now in KHz */
637
638 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
639
640 target_frequency = pdata->frequency ? pdata->frequency : 100000;
641
642 target_frequency /= 1000; /* Target frequency now in KHz */
643
644 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
645
646 if (freq > target_frequency) {
647 dev_err(i2c->dev,
648 "Unable to achieve desired frequency %luKHz." \
649 " Lowest achievable %dKHz\n", target_frequency, freq);
650 return -EINVAL;
651 }
652
653 *got = freq;
654
655 iiccon = readl(i2c->regs + S3C2410_IICCON);
656 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
657 iiccon |= (divs-1);
658
659 if (div1 == 512)
660 iiccon |= S3C2410_IICCON_TXDIV_512;
661
662 writel(iiccon, i2c->regs + S3C2410_IICCON);
663
664 if (s3c24xx_i2c_is2440(i2c)) {
665 unsigned long sda_delay;
666
667 if (pdata->sda_delay) {
668 sda_delay = clkin * pdata->sda_delay;
669 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
670 sda_delay = DIV_ROUND_UP(sda_delay, 5);
671 if (sda_delay > 3)
672 sda_delay = 3;
673 sda_delay |= S3C2410_IICLC_FILTER_ON;
674 } else
675 sda_delay = 0;
676
677 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
678 writel(sda_delay, i2c->regs + S3C2440_IICLC);
679 }
680
681 return 0;
682}
683
684#ifdef CONFIG_CPU_FREQ
685
686#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
687
688static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
689 unsigned long val, void *data)
690{
691 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
692 unsigned long flags;
693 unsigned int got;
694 int delta_f;
695 int ret;
696
697 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
698
699 /* if we're post-change and the input clock has slowed down
700 * or at pre-change and the clock is about to speed up, then
701 * adjust our clock rate. <0 is slow, >0 speedup.
702 */
703
704 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
705 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
706 spin_lock_irqsave(&i2c->lock, flags);
707 ret = s3c24xx_i2c_clockrate(i2c, &got);
708 spin_unlock_irqrestore(&i2c->lock, flags);
709
710 if (ret < 0)
711 dev_err(i2c->dev, "cannot find frequency\n");
712 else
713 dev_info(i2c->dev, "setting freq %d\n", got);
714 }
715
716 return 0;
717}
718
719static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
720{
721 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
722
723 return cpufreq_register_notifier(&i2c->freq_transition,
724 CPUFREQ_TRANSITION_NOTIFIER);
725}
726
727static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
728{
729 cpufreq_unregister_notifier(&i2c->freq_transition,
730 CPUFREQ_TRANSITION_NOTIFIER);
731}
732
733#else
734static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
735{
736 return 0;
737}
738
739static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
740{
741}
742#endif
743
744/* s3c24xx_i2c_init
745 *
746 * initialise the controller, set the IO lines and frequency
747*/
748
749static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
750{
751 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
752 struct s3c2410_platform_i2c *pdata;
753 unsigned int freq;
754
755 /* get the plafrom data */
756
757 pdata = i2c->dev->platform_data;
758
759 /* inititalise the gpio */
760
761 if (pdata->cfg_gpio)
762 pdata->cfg_gpio(to_platform_device(i2c->dev));
763
764 /* write slave address */
765
766 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
767
768 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
769
770 writel(iicon, i2c->regs + S3C2410_IICCON);
771
772 /* we need to work out the divisors for the clock... */
773
774 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
775 writel(0, i2c->regs + S3C2410_IICCON);
776 dev_err(i2c->dev, "cannot meet bus frequency required\n");
777 return -EINVAL;
778 }
779
780 /* todo - check that the i2c lines aren't being dragged anywhere */
781
782 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
783 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
784
785 return 0;
786}
787
788/* s3c24xx_i2c_probe
789 *
790 * called by the bus driver when a suitable device is found
791*/
792
793static int s3c24xx_i2c_probe(struct platform_device *pdev)
794{
795 struct s3c24xx_i2c *i2c;
796 struct s3c2410_platform_i2c *pdata;
797 struct resource *res;
798 int ret;
799
800 pdata = pdev->dev.platform_data;
801 if (!pdata) {
802 dev_err(&pdev->dev, "no platform data\n");
803 return -EINVAL;
804 }
805
806 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
807 if (!i2c) {
808 dev_err(&pdev->dev, "no memory for state\n");
809 return -ENOMEM;
810 }
811
812 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
813 i2c->adap.owner = THIS_MODULE;
814 i2c->adap.algo = &s3c24xx_i2c_algorithm;
815 i2c->adap.retries = 2;
816 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
817 i2c->tx_setup = 50;
818
819 spin_lock_init(&i2c->lock);
820 init_waitqueue_head(&i2c->wait);
821
822 /* find the clock and enable it */
823
824 i2c->dev = &pdev->dev;
825 i2c->clk = clk_get(&pdev->dev, "i2c");
826 if (IS_ERR(i2c->clk)) {
827 dev_err(&pdev->dev, "cannot get clock\n");
828 ret = -ENOENT;
829 goto err_noclk;
830 }
831
832 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
833
834 clk_enable(i2c->clk);
835
836 /* map the registers */
837
838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
839 if (res == NULL) {
840 dev_err(&pdev->dev, "cannot find IO resource\n");
841 ret = -ENOENT;
842 goto err_clk;
843 }
844
845 i2c->ioarea = request_mem_region(res->start, resource_size(res),
846 pdev->name);
847
848 if (i2c->ioarea == NULL) {
849 dev_err(&pdev->dev, "cannot request IO\n");
850 ret = -ENXIO;
851 goto err_clk;
852 }
853
854 i2c->regs = ioremap(res->start, resource_size(res));
855
856 if (i2c->regs == NULL) {
857 dev_err(&pdev->dev, "cannot map IO\n");
858 ret = -ENXIO;
859 goto err_ioarea;
860 }
861
862 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
863 i2c->regs, i2c->ioarea, res);
864
865 /* setup info block for the i2c core */
866
867 i2c->adap.algo_data = i2c;
868 i2c->adap.dev.parent = &pdev->dev;
869
870 /* initialise the i2c controller */
871
872 ret = s3c24xx_i2c_init(i2c);
873 if (ret != 0)
874 goto err_iomap;
875
876 /* find the IRQ for this unit (note, this relies on the init call to
877 * ensure no current IRQs pending
878 */
879
880 i2c->irq = ret = platform_get_irq(pdev, 0);
881 if (ret <= 0) {
882 dev_err(&pdev->dev, "cannot find IRQ\n");
883 goto err_iomap;
884 }
885
886 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
887 dev_name(&pdev->dev), i2c);
888
889 if (ret != 0) {
890 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
891 goto err_iomap;
892 }
893
894 ret = s3c24xx_i2c_register_cpufreq(i2c);
895 if (ret < 0) {
896 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
897 goto err_irq;
898 }
899
900 /* Note, previous versions of the driver used i2c_add_adapter()
901 * to add the bus at any number. We now pass the bus number via
902 * the platform data, so if unset it will now default to always
903 * being bus 0.
904 */
905
906 i2c->adap.nr = pdata->bus_num;
907
908 ret = i2c_add_numbered_adapter(&i2c->adap);
909 if (ret < 0) {
910 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
911 goto err_cpufreq;
912 }
913
914 platform_set_drvdata(pdev, i2c);
915
916 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
917 clk_disable(i2c->clk);
918 return 0;
919
920 err_cpufreq:
921 s3c24xx_i2c_deregister_cpufreq(i2c);
922
923 err_irq:
924 free_irq(i2c->irq, i2c);
925
926 err_iomap:
927 iounmap(i2c->regs);
928
929 err_ioarea:
930 release_resource(i2c->ioarea);
931 kfree(i2c->ioarea);
932
933 err_clk:
934 clk_disable(i2c->clk);
935 clk_put(i2c->clk);
936
937 err_noclk:
938 kfree(i2c);
939 return ret;
940}
941
942/* s3c24xx_i2c_remove
943 *
944 * called when device is removed from the bus
945*/
946
947static int s3c24xx_i2c_remove(struct platform_device *pdev)
948{
949 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
950
951 s3c24xx_i2c_deregister_cpufreq(i2c);
952
953 i2c_del_adapter(&i2c->adap);
954 free_irq(i2c->irq, i2c);
955
956 clk_disable(i2c->clk);
957 clk_put(i2c->clk);
958
959 iounmap(i2c->regs);
960
961 release_resource(i2c->ioarea);
962 kfree(i2c->ioarea);
963 kfree(i2c);
964
965 return 0;
966}
967
968#ifdef CONFIG_PM
969static int s3c24xx_i2c_suspend_noirq(struct device *dev)
970{
971 struct platform_device *pdev = to_platform_device(dev);
972 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
973
974 i2c->suspended = 1;
975
976 return 0;
977}
978
979static int s3c24xx_i2c_resume(struct device *dev)
980{
981 struct platform_device *pdev = to_platform_device(dev);
982 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
983
984 i2c->suspended = 0;
985 clk_enable(i2c->clk);
986 s3c24xx_i2c_init(i2c);
987 clk_disable(i2c->clk);
988
989 return 0;
990}
991
992static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
993 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
994 .resume = s3c24xx_i2c_resume,
995};
996
997#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
998#else
999#define S3C24XX_DEV_PM_OPS NULL
1000#endif
1001
1002/* device driver for platform bus bits */
1003
1004static struct platform_device_id s3c24xx_driver_ids[] = {
1005 {
1006 .name = "s3c2410-i2c",
1007 .driver_data = TYPE_S3C2410,
1008 }, {
1009 .name = "s3c2440-i2c",
1010 .driver_data = TYPE_S3C2440,
1011 }, { },
1012};
1013MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1014
1015static struct platform_driver s3c24xx_i2c_driver = {
1016 .probe = s3c24xx_i2c_probe,
1017 .remove = s3c24xx_i2c_remove,
1018 .id_table = s3c24xx_driver_ids,
1019 .driver = {
1020 .owner = THIS_MODULE,
1021 .name = "s3c-i2c",
1022 .pm = S3C24XX_DEV_PM_OPS,
1023 },
1024};
1025
1026static int __init i2c_adap_s3c_init(void)
1027{
1028 return platform_driver_register(&s3c24xx_i2c_driver);
1029}
1030subsys_initcall(i2c_adap_s3c_init);
1031
1032static void __exit i2c_adap_s3c_exit(void)
1033{
1034 platform_driver_unregister(&s3c24xx_i2c_driver);
1035}
1036module_exit(i2c_adap_s3c_exit);
1037
1038MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1039MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1040MODULE_LICENSE("GPL");
1/* linux/drivers/i2c/busses/i2c-s3c2410.c
2 *
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 I2C Controller
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17*/
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21
22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/time.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/clk.h>
32#include <linux/cpufreq.h>
33#include <linux/slab.h>
34#include <linux/io.h>
35#include <linux/of.h>
36#include <linux/of_gpio.h>
37#include <linux/pinctrl/consumer.h>
38#include <linux/mfd/syscon.h>
39#include <linux/regmap.h>
40
41#include <asm/irq.h>
42
43#include <linux/platform_data/i2c-s3c2410.h>
44
45/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
46
47#define S3C2410_IICCON 0x00
48#define S3C2410_IICSTAT 0x04
49#define S3C2410_IICADD 0x08
50#define S3C2410_IICDS 0x0C
51#define S3C2440_IICLC 0x10
52
53#define S3C2410_IICCON_ACKEN (1 << 7)
54#define S3C2410_IICCON_TXDIV_16 (0 << 6)
55#define S3C2410_IICCON_TXDIV_512 (1 << 6)
56#define S3C2410_IICCON_IRQEN (1 << 5)
57#define S3C2410_IICCON_IRQPEND (1 << 4)
58#define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
59#define S3C2410_IICCON_SCALEMASK (0xf)
60
61#define S3C2410_IICSTAT_MASTER_RX (2 << 6)
62#define S3C2410_IICSTAT_MASTER_TX (3 << 6)
63#define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
64#define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
65#define S3C2410_IICSTAT_MODEMASK (3 << 6)
66
67#define S3C2410_IICSTAT_START (1 << 5)
68#define S3C2410_IICSTAT_BUSBUSY (1 << 5)
69#define S3C2410_IICSTAT_TXRXEN (1 << 4)
70#define S3C2410_IICSTAT_ARBITR (1 << 3)
71#define S3C2410_IICSTAT_ASSLAVE (1 << 2)
72#define S3C2410_IICSTAT_ADDR0 (1 << 1)
73#define S3C2410_IICSTAT_LASTBIT (1 << 0)
74
75#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
76#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
77#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
78#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
79#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
80
81#define S3C2410_IICLC_FILTER_ON (1 << 2)
82
83/* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
84#define QUIRK_S3C2440 (1 << 0)
85#define QUIRK_HDMIPHY (1 << 1)
86#define QUIRK_NO_GPIO (1 << 2)
87#define QUIRK_POLL (1 << 3)
88
89/* Max time to wait for bus to become idle after a xfer (in us) */
90#define S3C2410_IDLE_TIMEOUT 5000
91
92/* Exynos5 Sysreg offset */
93#define EXYNOS5_SYS_I2C_CFG 0x0234
94
95/* i2c controller state */
96enum s3c24xx_i2c_state {
97 STATE_IDLE,
98 STATE_START,
99 STATE_READ,
100 STATE_WRITE,
101 STATE_STOP
102};
103
104struct s3c24xx_i2c {
105 wait_queue_head_t wait;
106 kernel_ulong_t quirks;
107 unsigned int suspended:1;
108
109 struct i2c_msg *msg;
110 unsigned int msg_num;
111 unsigned int msg_idx;
112 unsigned int msg_ptr;
113
114 unsigned int tx_setup;
115 unsigned int irq;
116
117 enum s3c24xx_i2c_state state;
118 unsigned long clkrate;
119
120 void __iomem *regs;
121 struct clk *clk;
122 struct device *dev;
123 struct i2c_adapter adap;
124
125 struct s3c2410_platform_i2c *pdata;
126 int gpios[2];
127 struct pinctrl *pctrl;
128#if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
129 struct notifier_block freq_transition;
130#endif
131 struct regmap *sysreg;
132 unsigned int sys_i2c_cfg;
133};
134
135static const struct platform_device_id s3c24xx_driver_ids[] = {
136 {
137 .name = "s3c2410-i2c",
138 .driver_data = 0,
139 }, {
140 .name = "s3c2440-i2c",
141 .driver_data = QUIRK_S3C2440,
142 }, {
143 .name = "s3c2440-hdmiphy-i2c",
144 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
145 }, { },
146};
147MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
148
149static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
150
151#ifdef CONFIG_OF
152static const struct of_device_id s3c24xx_i2c_match[] = {
153 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
154 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
155 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
156 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
157 { .compatible = "samsung,exynos5440-i2c",
158 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
159 { .compatible = "samsung,exynos5-sata-phy-i2c",
160 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
161 {},
162};
163MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
164#endif
165
166/*
167 * Get controller type either from device tree or platform device variant.
168 */
169static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
170{
171 if (pdev->dev.of_node) {
172 const struct of_device_id *match;
173
174 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
175 return (kernel_ulong_t)match->data;
176 }
177
178 return platform_get_device_id(pdev)->driver_data;
179}
180
181/*
182 * Complete the message and wake up the caller, using the given return code,
183 * or zero to mean ok.
184 */
185static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
186{
187 dev_dbg(i2c->dev, "master_complete %d\n", ret);
188
189 i2c->msg_ptr = 0;
190 i2c->msg = NULL;
191 i2c->msg_idx++;
192 i2c->msg_num = 0;
193 if (ret)
194 i2c->msg_idx = ret;
195
196 if (!(i2c->quirks & QUIRK_POLL))
197 wake_up(&i2c->wait);
198}
199
200static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
201{
202 unsigned long tmp;
203
204 tmp = readl(i2c->regs + S3C2410_IICCON);
205 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
206}
207
208static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
209{
210 unsigned long tmp;
211
212 tmp = readl(i2c->regs + S3C2410_IICCON);
213 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
214}
215
216/* irq enable/disable functions */
217static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
218{
219 unsigned long tmp;
220
221 tmp = readl(i2c->regs + S3C2410_IICCON);
222 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
223}
224
225static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
226{
227 unsigned long tmp;
228
229 tmp = readl(i2c->regs + S3C2410_IICCON);
230 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
231}
232
233static bool is_ack(struct s3c24xx_i2c *i2c)
234{
235 int tries;
236
237 for (tries = 50; tries; --tries) {
238 if (readl(i2c->regs + S3C2410_IICCON)
239 & S3C2410_IICCON_IRQPEND) {
240 if (!(readl(i2c->regs + S3C2410_IICSTAT)
241 & S3C2410_IICSTAT_LASTBIT))
242 return true;
243 }
244 usleep_range(1000, 2000);
245 }
246 dev_err(i2c->dev, "ack was not received\n");
247 return false;
248}
249
250/*
251 * put the start of a message onto the bus
252 */
253static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
254 struct i2c_msg *msg)
255{
256 unsigned int addr = (msg->addr & 0x7f) << 1;
257 unsigned long stat;
258 unsigned long iiccon;
259
260 stat = 0;
261 stat |= S3C2410_IICSTAT_TXRXEN;
262
263 if (msg->flags & I2C_M_RD) {
264 stat |= S3C2410_IICSTAT_MASTER_RX;
265 addr |= 1;
266 } else
267 stat |= S3C2410_IICSTAT_MASTER_TX;
268
269 if (msg->flags & I2C_M_REV_DIR_ADDR)
270 addr ^= 1;
271
272 /* todo - check for whether ack wanted or not */
273 s3c24xx_i2c_enable_ack(i2c);
274
275 iiccon = readl(i2c->regs + S3C2410_IICCON);
276 writel(stat, i2c->regs + S3C2410_IICSTAT);
277
278 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
279 writeb(addr, i2c->regs + S3C2410_IICDS);
280
281 /*
282 * delay here to ensure the data byte has gotten onto the bus
283 * before the transaction is started
284 */
285 ndelay(i2c->tx_setup);
286
287 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
288 writel(iiccon, i2c->regs + S3C2410_IICCON);
289
290 stat |= S3C2410_IICSTAT_START;
291 writel(stat, i2c->regs + S3C2410_IICSTAT);
292
293 if (i2c->quirks & QUIRK_POLL) {
294 while ((i2c->msg_num != 0) && is_ack(i2c)) {
295 i2c_s3c_irq_nextbyte(i2c, stat);
296 stat = readl(i2c->regs + S3C2410_IICSTAT);
297
298 if (stat & S3C2410_IICSTAT_ARBITR)
299 dev_err(i2c->dev, "deal with arbitration loss\n");
300 }
301 }
302}
303
304static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
305{
306 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
307
308 dev_dbg(i2c->dev, "STOP\n");
309
310 /*
311 * The datasheet says that the STOP sequence should be:
312 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
313 * 2) I2CCON.4 = 0 - Clear IRQPEND
314 * 3) Wait until the stop condition takes effect.
315 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
316 *
317 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
318 *
319 * However, after much experimentation, it appears that:
320 * a) normal buses automatically clear BUSY and transition from
321 * Master->Slave when they complete generating a STOP condition.
322 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
323 * after starting the STOP generation here.
324 * b) HDMIPHY bus does neither, so there is no way to do step 3.
325 * There is no indication when this bus has finished generating
326 * STOP.
327 *
328 * In fact, we have found that as soon as the IRQPEND bit is cleared in
329 * step 2, the HDMIPHY bus generates the STOP condition, and then
330 * immediately starts transferring another data byte, even though the
331 * bus is supposedly stopped. This is presumably because the bus is
332 * still in "Master" mode, and its BUSY bit is still set.
333 *
334 * To avoid these extra post-STOP transactions on HDMI phy devices, we
335 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
336 * instead of first generating a proper STOP condition. This should
337 * float SDA & SCK terminating the transfer. Subsequent transfers
338 * start with a proper START condition, and proceed normally.
339 *
340 * The HDMIPHY bus is an internal bus that always has exactly two
341 * devices, the host as Master and the HDMIPHY device as the slave.
342 * Skipping the STOP condition has been tested on this bus and works.
343 */
344 if (i2c->quirks & QUIRK_HDMIPHY) {
345 /* Stop driving the I2C pins */
346 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
347 } else {
348 /* stop the transfer */
349 iicstat &= ~S3C2410_IICSTAT_START;
350 }
351 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
352
353 i2c->state = STATE_STOP;
354
355 s3c24xx_i2c_master_complete(i2c, ret);
356 s3c24xx_i2c_disable_irq(i2c);
357}
358
359/*
360 * helper functions to determine the current state in the set of
361 * messages we are sending
362 */
363
364/*
365 * returns TRUE if the current message is the last in the set
366 */
367static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
368{
369 return i2c->msg_idx >= (i2c->msg_num - 1);
370}
371
372/*
373 * returns TRUE if we this is the last byte in the current message
374 */
375static inline int is_msglast(struct s3c24xx_i2c *i2c)
376{
377 /*
378 * msg->len is always 1 for the first byte of smbus block read.
379 * Actual length will be read from slave. More bytes will be
380 * read according to the length then.
381 */
382 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
383 return 0;
384
385 return i2c->msg_ptr == i2c->msg->len-1;
386}
387
388/*
389 * returns TRUE if we reached the end of the current message
390 */
391static inline int is_msgend(struct s3c24xx_i2c *i2c)
392{
393 return i2c->msg_ptr >= i2c->msg->len;
394}
395
396/*
397 * process an interrupt and work out what to do
398 */
399static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
400{
401 unsigned long tmp;
402 unsigned char byte;
403 int ret = 0;
404
405 switch (i2c->state) {
406
407 case STATE_IDLE:
408 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
409 goto out;
410
411 case STATE_STOP:
412 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
413 s3c24xx_i2c_disable_irq(i2c);
414 goto out_ack;
415
416 case STATE_START:
417 /*
418 * last thing we did was send a start condition on the
419 * bus, or started a new i2c message
420 */
421 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
422 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
423 /* ack was not received... */
424 dev_dbg(i2c->dev, "ack was not received\n");
425 s3c24xx_i2c_stop(i2c, -ENXIO);
426 goto out_ack;
427 }
428
429 if (i2c->msg->flags & I2C_M_RD)
430 i2c->state = STATE_READ;
431 else
432 i2c->state = STATE_WRITE;
433
434 /*
435 * Terminate the transfer if there is nothing to do
436 * as this is used by the i2c probe to find devices.
437 */
438 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
439 s3c24xx_i2c_stop(i2c, 0);
440 goto out_ack;
441 }
442
443 if (i2c->state == STATE_READ)
444 goto prepare_read;
445
446 /*
447 * fall through to the write state, as we will need to
448 * send a byte as well
449 */
450
451 case STATE_WRITE:
452 /*
453 * we are writing data to the device... check for the
454 * end of the message, and if so, work out what to do
455 */
456 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
457 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
458 dev_dbg(i2c->dev, "WRITE: No Ack\n");
459
460 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
461 goto out_ack;
462 }
463 }
464
465 retry_write:
466
467 if (!is_msgend(i2c)) {
468 byte = i2c->msg->buf[i2c->msg_ptr++];
469 writeb(byte, i2c->regs + S3C2410_IICDS);
470
471 /*
472 * delay after writing the byte to allow the
473 * data setup time on the bus, as writing the
474 * data to the register causes the first bit
475 * to appear on SDA, and SCL will change as
476 * soon as the interrupt is acknowledged
477 */
478 ndelay(i2c->tx_setup);
479
480 } else if (!is_lastmsg(i2c)) {
481 /* we need to go to the next i2c message */
482
483 dev_dbg(i2c->dev, "WRITE: Next Message\n");
484
485 i2c->msg_ptr = 0;
486 i2c->msg_idx++;
487 i2c->msg++;
488
489 /* check to see if we need to do another message */
490 if (i2c->msg->flags & I2C_M_NOSTART) {
491
492 if (i2c->msg->flags & I2C_M_RD) {
493 /*
494 * cannot do this, the controller
495 * forces us to send a new START
496 * when we change direction
497 */
498 s3c24xx_i2c_stop(i2c, -EINVAL);
499 }
500
501 goto retry_write;
502 } else {
503 /* send the new start */
504 s3c24xx_i2c_message_start(i2c, i2c->msg);
505 i2c->state = STATE_START;
506 }
507
508 } else {
509 /* send stop */
510 s3c24xx_i2c_stop(i2c, 0);
511 }
512 break;
513
514 case STATE_READ:
515 /*
516 * we have a byte of data in the data register, do
517 * something with it, and then work out whether we are
518 * going to do any more read/write
519 */
520 byte = readb(i2c->regs + S3C2410_IICDS);
521 i2c->msg->buf[i2c->msg_ptr++] = byte;
522
523 /* Add actual length to read for smbus block read */
524 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
525 i2c->msg->len += byte;
526 prepare_read:
527 if (is_msglast(i2c)) {
528 /* last byte of buffer */
529
530 if (is_lastmsg(i2c))
531 s3c24xx_i2c_disable_ack(i2c);
532
533 } else if (is_msgend(i2c)) {
534 /*
535 * ok, we've read the entire buffer, see if there
536 * is anything else we need to do
537 */
538 if (is_lastmsg(i2c)) {
539 /* last message, send stop and complete */
540 dev_dbg(i2c->dev, "READ: Send Stop\n");
541
542 s3c24xx_i2c_stop(i2c, 0);
543 } else {
544 /* go to the next transfer */
545 dev_dbg(i2c->dev, "READ: Next Transfer\n");
546
547 i2c->msg_ptr = 0;
548 i2c->msg_idx++;
549 i2c->msg++;
550 }
551 }
552
553 break;
554 }
555
556 /* acknowlegde the IRQ and get back on with the work */
557
558 out_ack:
559 tmp = readl(i2c->regs + S3C2410_IICCON);
560 tmp &= ~S3C2410_IICCON_IRQPEND;
561 writel(tmp, i2c->regs + S3C2410_IICCON);
562 out:
563 return ret;
564}
565
566/*
567 * top level IRQ servicing routine
568 */
569static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
570{
571 struct s3c24xx_i2c *i2c = dev_id;
572 unsigned long status;
573 unsigned long tmp;
574
575 status = readl(i2c->regs + S3C2410_IICSTAT);
576
577 if (status & S3C2410_IICSTAT_ARBITR) {
578 /* deal with arbitration loss */
579 dev_err(i2c->dev, "deal with arbitration loss\n");
580 }
581
582 if (i2c->state == STATE_IDLE) {
583 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
584
585 tmp = readl(i2c->regs + S3C2410_IICCON);
586 tmp &= ~S3C2410_IICCON_IRQPEND;
587 writel(tmp, i2c->regs + S3C2410_IICCON);
588 goto out;
589 }
590
591 /*
592 * pretty much this leaves us with the fact that we've
593 * transmitted or received whatever byte we last sent
594 */
595 i2c_s3c_irq_nextbyte(i2c, status);
596
597 out:
598 return IRQ_HANDLED;
599}
600
601/*
602 * Disable the bus so that we won't get any interrupts from now on, or try
603 * to drive any lines. This is the default state when we don't have
604 * anything to send/receive.
605 *
606 * If there is an event on the bus, or we have a pre-existing event at
607 * kernel boot time, we may not notice the event and the I2C controller
608 * will lock the bus with the I2C clock line low indefinitely.
609 */
610static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
611{
612 unsigned long tmp;
613
614 /* Stop driving the I2C pins */
615 tmp = readl(i2c->regs + S3C2410_IICSTAT);
616 tmp &= ~S3C2410_IICSTAT_TXRXEN;
617 writel(tmp, i2c->regs + S3C2410_IICSTAT);
618
619 /* We don't expect any interrupts now, and don't want send acks */
620 tmp = readl(i2c->regs + S3C2410_IICCON);
621 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
622 S3C2410_IICCON_ACKEN);
623 writel(tmp, i2c->regs + S3C2410_IICCON);
624}
625
626
627/*
628 * get the i2c bus for a master transaction
629 */
630static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
631{
632 unsigned long iicstat;
633 int timeout = 400;
634
635 while (timeout-- > 0) {
636 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
637
638 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
639 return 0;
640
641 msleep(1);
642 }
643
644 return -ETIMEDOUT;
645}
646
647/*
648 * wait for the i2c bus to become idle.
649 */
650static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
651{
652 unsigned long iicstat;
653 ktime_t start, now;
654 unsigned long delay;
655 int spins;
656
657 /* ensure the stop has been through the bus */
658
659 dev_dbg(i2c->dev, "waiting for bus idle\n");
660
661 start = now = ktime_get();
662
663 /*
664 * Most of the time, the bus is already idle within a few usec of the
665 * end of a transaction. However, really slow i2c devices can stretch
666 * the clock, delaying STOP generation.
667 *
668 * On slower SoCs this typically happens within a very small number of
669 * instructions so busy wait briefly to avoid scheduling overhead.
670 */
671 spins = 3;
672 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
673 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
674 cpu_relax();
675 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
676 }
677
678 /*
679 * If we do get an appreciable delay as a compromise between idle
680 * detection latency for the normal, fast case, and system load in the
681 * slow device case, use an exponential back off in the polling loop,
682 * up to 1/10th of the total timeout, then continue to poll at a
683 * constant rate up to the timeout.
684 */
685 delay = 1;
686 while ((iicstat & S3C2410_IICSTAT_START) &&
687 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
688 usleep_range(delay, 2 * delay);
689 if (delay < S3C2410_IDLE_TIMEOUT / 10)
690 delay <<= 1;
691 now = ktime_get();
692 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
693 }
694
695 if (iicstat & S3C2410_IICSTAT_START)
696 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
697}
698
699/*
700 * this starts an i2c transfer
701 */
702static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
703 struct i2c_msg *msgs, int num)
704{
705 unsigned long timeout;
706 int ret;
707
708 if (i2c->suspended)
709 return -EIO;
710
711 ret = s3c24xx_i2c_set_master(i2c);
712 if (ret != 0) {
713 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
714 ret = -EAGAIN;
715 goto out;
716 }
717
718 i2c->msg = msgs;
719 i2c->msg_num = num;
720 i2c->msg_ptr = 0;
721 i2c->msg_idx = 0;
722 i2c->state = STATE_START;
723
724 s3c24xx_i2c_enable_irq(i2c);
725 s3c24xx_i2c_message_start(i2c, msgs);
726
727 if (i2c->quirks & QUIRK_POLL) {
728 ret = i2c->msg_idx;
729
730 if (ret != num)
731 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
732
733 goto out;
734 }
735
736 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
737
738 ret = i2c->msg_idx;
739
740 /*
741 * Having these next two as dev_err() makes life very
742 * noisy when doing an i2cdetect
743 */
744 if (timeout == 0)
745 dev_dbg(i2c->dev, "timeout\n");
746 else if (ret != num)
747 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
748
749 /* For QUIRK_HDMIPHY, bus is already disabled */
750 if (i2c->quirks & QUIRK_HDMIPHY)
751 goto out;
752
753 s3c24xx_i2c_wait_idle(i2c);
754
755 s3c24xx_i2c_disable_bus(i2c);
756
757 out:
758 i2c->state = STATE_IDLE;
759
760 return ret;
761}
762
763/*
764 * first port of call from the i2c bus code when an message needs
765 * transferring across the i2c bus.
766 */
767static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
768 struct i2c_msg *msgs, int num)
769{
770 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
771 int retry;
772 int ret;
773
774 ret = clk_enable(i2c->clk);
775 if (ret)
776 return ret;
777
778 for (retry = 0; retry < adap->retries; retry++) {
779
780 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
781
782 if (ret != -EAGAIN) {
783 clk_disable(i2c->clk);
784 return ret;
785 }
786
787 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
788
789 udelay(100);
790 }
791
792 clk_disable(i2c->clk);
793 return -EREMOTEIO;
794}
795
796/* declare our i2c functionality */
797static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
798{
799 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
800 I2C_FUNC_PROTOCOL_MANGLING;
801}
802
803/* i2c bus registration info */
804static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
805 .master_xfer = s3c24xx_i2c_xfer,
806 .functionality = s3c24xx_i2c_func,
807};
808
809/*
810 * return the divisor settings for a given frequency
811 */
812static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
813 unsigned int *div1, unsigned int *divs)
814{
815 unsigned int calc_divs = clkin / wanted;
816 unsigned int calc_div1;
817
818 if (calc_divs > (16*16))
819 calc_div1 = 512;
820 else
821 calc_div1 = 16;
822
823 calc_divs += calc_div1-1;
824 calc_divs /= calc_div1;
825
826 if (calc_divs == 0)
827 calc_divs = 1;
828 if (calc_divs > 17)
829 calc_divs = 17;
830
831 *divs = calc_divs;
832 *div1 = calc_div1;
833
834 return clkin / (calc_divs * calc_div1);
835}
836
837/*
838 * work out a divisor for the user requested frequency setting,
839 * either by the requested frequency, or scanning the acceptable
840 * range of frequencies until something is found
841 */
842static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
843{
844 struct s3c2410_platform_i2c *pdata = i2c->pdata;
845 unsigned long clkin = clk_get_rate(i2c->clk);
846 unsigned int divs, div1;
847 unsigned long target_frequency;
848 u32 iiccon;
849 int freq;
850
851 i2c->clkrate = clkin;
852 clkin /= 1000; /* clkin now in KHz */
853
854 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
855
856 target_frequency = pdata->frequency ? pdata->frequency : 100000;
857
858 target_frequency /= 1000; /* Target frequency now in KHz */
859
860 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
861
862 if (freq > target_frequency) {
863 dev_err(i2c->dev,
864 "Unable to achieve desired frequency %luKHz." \
865 " Lowest achievable %dKHz\n", target_frequency, freq);
866 return -EINVAL;
867 }
868
869 *got = freq;
870
871 iiccon = readl(i2c->regs + S3C2410_IICCON);
872 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
873 iiccon |= (divs-1);
874
875 if (div1 == 512)
876 iiccon |= S3C2410_IICCON_TXDIV_512;
877
878 if (i2c->quirks & QUIRK_POLL)
879 iiccon |= S3C2410_IICCON_SCALE(2);
880
881 writel(iiccon, i2c->regs + S3C2410_IICCON);
882
883 if (i2c->quirks & QUIRK_S3C2440) {
884 unsigned long sda_delay;
885
886 if (pdata->sda_delay) {
887 sda_delay = clkin * pdata->sda_delay;
888 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
889 sda_delay = DIV_ROUND_UP(sda_delay, 5);
890 if (sda_delay > 3)
891 sda_delay = 3;
892 sda_delay |= S3C2410_IICLC_FILTER_ON;
893 } else
894 sda_delay = 0;
895
896 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
897 writel(sda_delay, i2c->regs + S3C2440_IICLC);
898 }
899
900 return 0;
901}
902
903#if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
904
905#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
906
907static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
908 unsigned long val, void *data)
909{
910 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
911 unsigned int got;
912 int delta_f;
913 int ret;
914
915 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
916
917 /* if we're post-change and the input clock has slowed down
918 * or at pre-change and the clock is about to speed up, then
919 * adjust our clock rate. <0 is slow, >0 speedup.
920 */
921
922 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
923 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
924 i2c_lock_adapter(&i2c->adap);
925 ret = s3c24xx_i2c_clockrate(i2c, &got);
926 i2c_unlock_adapter(&i2c->adap);
927
928 if (ret < 0)
929 dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
930 else
931 dev_info(i2c->dev, "setting freq %d\n", got);
932 }
933
934 return 0;
935}
936
937static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
938{
939 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
940
941 return cpufreq_register_notifier(&i2c->freq_transition,
942 CPUFREQ_TRANSITION_NOTIFIER);
943}
944
945static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
946{
947 cpufreq_unregister_notifier(&i2c->freq_transition,
948 CPUFREQ_TRANSITION_NOTIFIER);
949}
950
951#else
952static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
953{
954 return 0;
955}
956
957static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
958{
959}
960#endif
961
962#ifdef CONFIG_OF
963static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
964{
965 int idx, gpio, ret;
966
967 if (i2c->quirks & QUIRK_NO_GPIO)
968 return 0;
969
970 for (idx = 0; idx < 2; idx++) {
971 gpio = of_get_gpio(i2c->dev->of_node, idx);
972 if (!gpio_is_valid(gpio)) {
973 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
974 goto free_gpio;
975 }
976 i2c->gpios[idx] = gpio;
977
978 ret = gpio_request(gpio, "i2c-bus");
979 if (ret) {
980 dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
981 gpio, ret);
982 goto free_gpio;
983 }
984 }
985 return 0;
986
987free_gpio:
988 while (--idx >= 0)
989 gpio_free(i2c->gpios[idx]);
990 return -EINVAL;
991}
992
993static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
994{
995 unsigned int idx;
996
997 if (i2c->quirks & QUIRK_NO_GPIO)
998 return;
999
1000 for (idx = 0; idx < 2; idx++)
1001 gpio_free(i2c->gpios[idx]);
1002}
1003#else
1004static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
1005{
1006 return 0;
1007}
1008
1009static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1010{
1011}
1012#endif
1013
1014/*
1015 * initialise the controller, set the IO lines and frequency
1016 */
1017static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1018{
1019 struct s3c2410_platform_i2c *pdata;
1020 unsigned int freq;
1021
1022 /* get the plafrom data */
1023
1024 pdata = i2c->pdata;
1025
1026 /* write slave address */
1027
1028 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1029
1030 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1031
1032 writel(0, i2c->regs + S3C2410_IICCON);
1033 writel(0, i2c->regs + S3C2410_IICSTAT);
1034
1035 /* we need to work out the divisors for the clock... */
1036
1037 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1038 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1039 return -EINVAL;
1040 }
1041
1042 /* todo - check that the i2c lines aren't being dragged anywhere */
1043
1044 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1045 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1046 readl(i2c->regs + S3C2410_IICCON));
1047
1048 return 0;
1049}
1050
1051#ifdef CONFIG_OF
1052/*
1053 * Parse the device tree node and retreive the platform data.
1054 */
1055static void
1056s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1057{
1058 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1059 int id;
1060
1061 if (!np)
1062 return;
1063
1064 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1065 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1066 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1067 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1068 (u32 *)&pdata->frequency);
1069 /*
1070 * Exynos5's legacy i2c controller and new high speed i2c
1071 * controller have muxed interrupt sources. By default the
1072 * interrupts for 4-channel HS-I2C controller are enabled.
1073 * If nodes for first four channels of legacy i2c controller
1074 * are available then re-configure the interrupts via the
1075 * system register.
1076 */
1077 id = of_alias_get_id(np, "i2c");
1078 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1079 "samsung,sysreg-phandle");
1080 if (IS_ERR(i2c->sysreg))
1081 return;
1082
1083 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1084}
1085#else
1086static void
1087s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1088#endif
1089
1090static int s3c24xx_i2c_probe(struct platform_device *pdev)
1091{
1092 struct s3c24xx_i2c *i2c;
1093 struct s3c2410_platform_i2c *pdata = NULL;
1094 struct resource *res;
1095 int ret;
1096
1097 if (!pdev->dev.of_node) {
1098 pdata = dev_get_platdata(&pdev->dev);
1099 if (!pdata) {
1100 dev_err(&pdev->dev, "no platform data\n");
1101 return -EINVAL;
1102 }
1103 }
1104
1105 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1106 if (!i2c)
1107 return -ENOMEM;
1108
1109 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1110 if (!i2c->pdata)
1111 return -ENOMEM;
1112
1113 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1114 i2c->sysreg = ERR_PTR(-ENOENT);
1115 if (pdata)
1116 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1117 else
1118 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1119
1120 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1121 i2c->adap.owner = THIS_MODULE;
1122 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1123 i2c->adap.retries = 2;
1124 i2c->adap.class = I2C_CLASS_DEPRECATED;
1125 i2c->tx_setup = 50;
1126
1127 init_waitqueue_head(&i2c->wait);
1128
1129 /* find the clock and enable it */
1130 i2c->dev = &pdev->dev;
1131 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1132 if (IS_ERR(i2c->clk)) {
1133 dev_err(&pdev->dev, "cannot get clock\n");
1134 return -ENOENT;
1135 }
1136
1137 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1138
1139 /* map the registers */
1140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1141 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1142
1143 if (IS_ERR(i2c->regs))
1144 return PTR_ERR(i2c->regs);
1145
1146 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1147 i2c->regs, res);
1148
1149 /* setup info block for the i2c core */
1150 i2c->adap.algo_data = i2c;
1151 i2c->adap.dev.parent = &pdev->dev;
1152 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1153
1154 /* inititalise the i2c gpio lines */
1155 if (i2c->pdata->cfg_gpio)
1156 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1157 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1158 return -EINVAL;
1159
1160 /* initialise the i2c controller */
1161 ret = clk_prepare_enable(i2c->clk);
1162 if (ret) {
1163 dev_err(&pdev->dev, "I2C clock enable failed\n");
1164 return ret;
1165 }
1166
1167 ret = s3c24xx_i2c_init(i2c);
1168 clk_disable(i2c->clk);
1169 if (ret != 0) {
1170 dev_err(&pdev->dev, "I2C controller init failed\n");
1171 clk_unprepare(i2c->clk);
1172 return ret;
1173 }
1174
1175 /*
1176 * find the IRQ for this unit (note, this relies on the init call to
1177 * ensure no current IRQs pending
1178 */
1179 if (!(i2c->quirks & QUIRK_POLL)) {
1180 i2c->irq = ret = platform_get_irq(pdev, 0);
1181 if (ret <= 0) {
1182 dev_err(&pdev->dev, "cannot find IRQ\n");
1183 clk_unprepare(i2c->clk);
1184 return ret;
1185 }
1186
1187 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1188 0, dev_name(&pdev->dev), i2c);
1189 if (ret != 0) {
1190 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1191 clk_unprepare(i2c->clk);
1192 return ret;
1193 }
1194 }
1195
1196 ret = s3c24xx_i2c_register_cpufreq(i2c);
1197 if (ret < 0) {
1198 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1199 clk_unprepare(i2c->clk);
1200 return ret;
1201 }
1202
1203 /*
1204 * Note, previous versions of the driver used i2c_add_adapter()
1205 * to add the bus at any number. We now pass the bus number via
1206 * the platform data, so if unset it will now default to always
1207 * being bus 0.
1208 */
1209 i2c->adap.nr = i2c->pdata->bus_num;
1210 i2c->adap.dev.of_node = pdev->dev.of_node;
1211
1212 platform_set_drvdata(pdev, i2c);
1213
1214 pm_runtime_enable(&pdev->dev);
1215
1216 ret = i2c_add_numbered_adapter(&i2c->adap);
1217 if (ret < 0) {
1218 pm_runtime_disable(&pdev->dev);
1219 s3c24xx_i2c_deregister_cpufreq(i2c);
1220 clk_unprepare(i2c->clk);
1221 return ret;
1222 }
1223
1224 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1225 return 0;
1226}
1227
1228static int s3c24xx_i2c_remove(struct platform_device *pdev)
1229{
1230 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1231
1232 clk_unprepare(i2c->clk);
1233
1234 pm_runtime_disable(&pdev->dev);
1235
1236 s3c24xx_i2c_deregister_cpufreq(i2c);
1237
1238 i2c_del_adapter(&i2c->adap);
1239
1240 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1241 s3c24xx_i2c_dt_gpio_free(i2c);
1242
1243 return 0;
1244}
1245
1246#ifdef CONFIG_PM_SLEEP
1247static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1248{
1249 struct platform_device *pdev = to_platform_device(dev);
1250 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1251
1252 i2c->suspended = 1;
1253
1254 if (!IS_ERR(i2c->sysreg))
1255 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1256
1257 return 0;
1258}
1259
1260static int s3c24xx_i2c_resume_noirq(struct device *dev)
1261{
1262 struct platform_device *pdev = to_platform_device(dev);
1263 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1264 int ret;
1265
1266 if (!IS_ERR(i2c->sysreg))
1267 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1268
1269 ret = clk_enable(i2c->clk);
1270 if (ret)
1271 return ret;
1272 s3c24xx_i2c_init(i2c);
1273 clk_disable(i2c->clk);
1274 i2c->suspended = 0;
1275
1276 return 0;
1277}
1278#endif
1279
1280#ifdef CONFIG_PM
1281static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1282 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1283 s3c24xx_i2c_resume_noirq)
1284};
1285
1286#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1287#else
1288#define S3C24XX_DEV_PM_OPS NULL
1289#endif
1290
1291static struct platform_driver s3c24xx_i2c_driver = {
1292 .probe = s3c24xx_i2c_probe,
1293 .remove = s3c24xx_i2c_remove,
1294 .id_table = s3c24xx_driver_ids,
1295 .driver = {
1296 .name = "s3c-i2c",
1297 .pm = S3C24XX_DEV_PM_OPS,
1298 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1299 },
1300};
1301
1302static int __init i2c_adap_s3c_init(void)
1303{
1304 return platform_driver_register(&s3c24xx_i2c_driver);
1305}
1306subsys_initcall(i2c_adap_s3c_init);
1307
1308static void __exit i2c_adap_s3c_exit(void)
1309{
1310 platform_driver_unregister(&s3c24xx_i2c_driver);
1311}
1312module_exit(i2c_adap_s3c_exit);
1313
1314MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1315MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1316MODULE_LICENSE("GPL");