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1/*
2 * Driver for I2C adapter in Rockchip RK3xxx SoC
3 *
4 * Max Schwarz <max.schwarz@online.de>
5 * based on the patches by Rockchip Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/i2c.h>
15#include <linux/interrupt.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/spinlock.h>
23#include <linux/clk.h>
24#include <linux/wait.h>
25#include <linux/mfd/syscon.h>
26#include <linux/regmap.h>
27#include <linux/math64.h>
28
29
30/* Register Map */
31#define REG_CON 0x00 /* control register */
32#define REG_CLKDIV 0x04 /* clock divisor register */
33#define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
34#define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
35#define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
36#define REG_MRXCNT 0x14 /* number of bytes to be received */
37#define REG_IEN 0x18 /* interrupt enable */
38#define REG_IPD 0x1c /* interrupt pending */
39#define REG_FCNT 0x20 /* finished count */
40
41/* Data buffer offsets */
42#define TXBUFFER_BASE 0x100
43#define RXBUFFER_BASE 0x200
44
45/* REG_CON bits */
46#define REG_CON_EN BIT(0)
47enum {
48 REG_CON_MOD_TX = 0, /* transmit data */
49 REG_CON_MOD_REGISTER_TX, /* select register and restart */
50 REG_CON_MOD_RX, /* receive data */
51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
52 * register addr */
53};
54#define REG_CON_MOD(mod) ((mod) << 1)
55#define REG_CON_MOD_MASK (BIT(1) | BIT(2))
56#define REG_CON_START BIT(3)
57#define REG_CON_STOP BIT(4)
58#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
59#define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
60
61#define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
62
63#define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
64#define REG_CON_STA_CFG(cfg) ((cfg) << 12)
65#define REG_CON_STO_CFG(cfg) ((cfg) << 14)
66
67/* REG_MRXADDR bits */
68#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
69
70/* REG_IEN/REG_IPD bits */
71#define REG_INT_BTF BIT(0) /* a byte was transmitted */
72#define REG_INT_BRF BIT(1) /* a byte was received */
73#define REG_INT_MBTF BIT(2) /* master data transmit finished */
74#define REG_INT_MBRF BIT(3) /* master data receive finished */
75#define REG_INT_START BIT(4) /* START condition generated */
76#define REG_INT_STOP BIT(5) /* STOP condition generated */
77#define REG_INT_NAKRCV BIT(6) /* NACK received */
78#define REG_INT_ALL 0x7f
79
80/* Constants */
81#define WAIT_TIMEOUT 1000 /* ms */
82#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
83
84/**
85 * struct i2c_spec_values:
86 * @min_hold_start_ns: min hold time (repeated) START condition
87 * @min_low_ns: min LOW period of the SCL clock
88 * @min_high_ns: min HIGH period of the SCL cloc
89 * @min_setup_start_ns: min set-up time for a repeated START conditio
90 * @max_data_hold_ns: max data hold time
91 * @min_data_setup_ns: min data set-up time
92 * @min_setup_stop_ns: min set-up time for STOP condition
93 * @min_hold_buffer_ns: min bus free time between a STOP and
94 * START condition
95 */
96struct i2c_spec_values {
97 unsigned long min_hold_start_ns;
98 unsigned long min_low_ns;
99 unsigned long min_high_ns;
100 unsigned long min_setup_start_ns;
101 unsigned long max_data_hold_ns;
102 unsigned long min_data_setup_ns;
103 unsigned long min_setup_stop_ns;
104 unsigned long min_hold_buffer_ns;
105};
106
107static const struct i2c_spec_values standard_mode_spec = {
108 .min_hold_start_ns = 4000,
109 .min_low_ns = 4700,
110 .min_high_ns = 4000,
111 .min_setup_start_ns = 4700,
112 .max_data_hold_ns = 3450,
113 .min_data_setup_ns = 250,
114 .min_setup_stop_ns = 4000,
115 .min_hold_buffer_ns = 4700,
116};
117
118static const struct i2c_spec_values fast_mode_spec = {
119 .min_hold_start_ns = 600,
120 .min_low_ns = 1300,
121 .min_high_ns = 600,
122 .min_setup_start_ns = 600,
123 .max_data_hold_ns = 900,
124 .min_data_setup_ns = 100,
125 .min_setup_stop_ns = 600,
126 .min_hold_buffer_ns = 1300,
127};
128
129static const struct i2c_spec_values fast_mode_plus_spec = {
130 .min_hold_start_ns = 260,
131 .min_low_ns = 500,
132 .min_high_ns = 260,
133 .min_setup_start_ns = 260,
134 .max_data_hold_ns = 400,
135 .min_data_setup_ns = 50,
136 .min_setup_stop_ns = 260,
137 .min_hold_buffer_ns = 500,
138};
139
140/**
141 * struct rk3x_i2c_calced_timings:
142 * @div_low: Divider output for low
143 * @div_high: Divider output for high
144 * @tuning: Used to adjust setup/hold data time,
145 * setup/hold start time and setup stop time for
146 * v1's calc_timings, the tuning should all be 0
147 * for old hardware anyone using v0's calc_timings.
148 */
149struct rk3x_i2c_calced_timings {
150 unsigned long div_low;
151 unsigned long div_high;
152 unsigned int tuning;
153};
154
155enum rk3x_i2c_state {
156 STATE_IDLE,
157 STATE_START,
158 STATE_READ,
159 STATE_WRITE,
160 STATE_STOP
161};
162
163/**
164 * @grf_offset: offset inside the grf regmap for setting the i2c type
165 * @calc_timings: Callback function for i2c timing information calculated
166 */
167struct rk3x_i2c_soc_data {
168 int grf_offset;
169 int (*calc_timings)(unsigned long, struct i2c_timings *,
170 struct rk3x_i2c_calced_timings *);
171};
172
173/**
174 * struct rk3x_i2c - private data of the controller
175 * @adap: corresponding I2C adapter
176 * @dev: device for this controller
177 * @soc_data: related soc data struct
178 * @regs: virtual memory area
179 * @clk: function clk for rk3399 or function & Bus clks for others
180 * @pclk: Bus clk for rk3399
181 * @clk_rate_nb: i2c clk rate change notify
182 * @t: I2C known timing information
183 * @lock: spinlock for the i2c bus
184 * @wait: the waitqueue to wait for i2c transfer
185 * @busy: the condition for the event to wait for
186 * @msg: current i2c message
187 * @addr: addr of i2c slave device
188 * @mode: mode of i2c transfer
189 * @is_last_msg: flag determines whether it is the last msg in this transfer
190 * @state: state of i2c transfer
191 * @processed: byte length which has been send or received
192 * @error: error code for i2c transfer
193 */
194struct rk3x_i2c {
195 struct i2c_adapter adap;
196 struct device *dev;
197 struct rk3x_i2c_soc_data *soc_data;
198
199 /* Hardware resources */
200 void __iomem *regs;
201 struct clk *clk;
202 struct clk *pclk;
203 struct notifier_block clk_rate_nb;
204
205 /* Settings */
206 struct i2c_timings t;
207
208 /* Synchronization & notification */
209 spinlock_t lock;
210 wait_queue_head_t wait;
211 bool busy;
212
213 /* Current message */
214 struct i2c_msg *msg;
215 u8 addr;
216 unsigned int mode;
217 bool is_last_msg;
218
219 /* I2C state machine */
220 enum rk3x_i2c_state state;
221 unsigned int processed;
222 int error;
223};
224
225static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
226 unsigned int offset)
227{
228 writel(value, i2c->regs + offset);
229}
230
231static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
232{
233 return readl(i2c->regs + offset);
234}
235
236/* Reset all interrupt pending bits */
237static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
238{
239 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
240}
241
242/**
243 * Generate a START condition, which triggers a REG_INT_START interrupt.
244 */
245static void rk3x_i2c_start(struct rk3x_i2c *i2c)
246{
247 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
248
249 i2c_writel(i2c, REG_INT_START, REG_IEN);
250
251 /* enable adapter with correct mode, send START condition */
252 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
253
254 /* if we want to react to NACK, set ACTACK bit */
255 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
256 val |= REG_CON_ACTACK;
257
258 i2c_writel(i2c, val, REG_CON);
259}
260
261/**
262 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
263 *
264 * @error: Error code to return in rk3x_i2c_xfer
265 */
266static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
267{
268 unsigned int ctrl;
269
270 i2c->processed = 0;
271 i2c->msg = NULL;
272 i2c->error = error;
273
274 if (i2c->is_last_msg) {
275 /* Enable stop interrupt */
276 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
277
278 i2c->state = STATE_STOP;
279
280 ctrl = i2c_readl(i2c, REG_CON);
281 ctrl |= REG_CON_STOP;
282 i2c_writel(i2c, ctrl, REG_CON);
283 } else {
284 /* Signal rk3x_i2c_xfer to start the next message. */
285 i2c->busy = false;
286 i2c->state = STATE_IDLE;
287
288 /*
289 * The HW is actually not capable of REPEATED START. But we can
290 * get the intended effect by resetting its internal state
291 * and issuing an ordinary START.
292 */
293 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
294 i2c_writel(i2c, ctrl, REG_CON);
295
296 /* signal that we are finished with the current msg */
297 wake_up(&i2c->wait);
298 }
299}
300
301/**
302 * Setup a read according to i2c->msg
303 */
304static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
305{
306 unsigned int len = i2c->msg->len - i2c->processed;
307 u32 con;
308
309 con = i2c_readl(i2c, REG_CON);
310
311 /*
312 * The hw can read up to 32 bytes at a time. If we need more than one
313 * chunk, send an ACK after the last byte of the current chunk.
314 */
315 if (len > 32) {
316 len = 32;
317 con &= ~REG_CON_LASTACK;
318 } else {
319 con |= REG_CON_LASTACK;
320 }
321
322 /* make sure we are in plain RX mode if we read a second chunk */
323 if (i2c->processed != 0) {
324 con &= ~REG_CON_MOD_MASK;
325 con |= REG_CON_MOD(REG_CON_MOD_RX);
326 }
327
328 i2c_writel(i2c, con, REG_CON);
329 i2c_writel(i2c, len, REG_MRXCNT);
330}
331
332/**
333 * Fill the transmit buffer with data from i2c->msg
334 */
335static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
336{
337 unsigned int i, j;
338 u32 cnt = 0;
339 u32 val;
340 u8 byte;
341
342 for (i = 0; i < 8; ++i) {
343 val = 0;
344 for (j = 0; j < 4; ++j) {
345 if ((i2c->processed == i2c->msg->len) && (cnt != 0))
346 break;
347
348 if (i2c->processed == 0 && cnt == 0)
349 byte = (i2c->addr & 0x7f) << 1;
350 else
351 byte = i2c->msg->buf[i2c->processed++];
352
353 val |= byte << (j * 8);
354 cnt++;
355 }
356
357 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
358
359 if (i2c->processed == i2c->msg->len)
360 break;
361 }
362
363 i2c_writel(i2c, cnt, REG_MTXCNT);
364}
365
366
367/* IRQ handlers for individual states */
368
369static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
370{
371 if (!(ipd & REG_INT_START)) {
372 rk3x_i2c_stop(i2c, -EIO);
373 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
374 rk3x_i2c_clean_ipd(i2c);
375 return;
376 }
377
378 /* ack interrupt */
379 i2c_writel(i2c, REG_INT_START, REG_IPD);
380
381 /* disable start bit */
382 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
383
384 /* enable appropriate interrupts and transition */
385 if (i2c->mode == REG_CON_MOD_TX) {
386 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
387 i2c->state = STATE_WRITE;
388 rk3x_i2c_fill_transmit_buf(i2c);
389 } else {
390 /* in any other case, we are going to be reading. */
391 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
392 i2c->state = STATE_READ;
393 rk3x_i2c_prepare_read(i2c);
394 }
395}
396
397static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
398{
399 if (!(ipd & REG_INT_MBTF)) {
400 rk3x_i2c_stop(i2c, -EIO);
401 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
402 rk3x_i2c_clean_ipd(i2c);
403 return;
404 }
405
406 /* ack interrupt */
407 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
408
409 /* are we finished? */
410 if (i2c->processed == i2c->msg->len)
411 rk3x_i2c_stop(i2c, i2c->error);
412 else
413 rk3x_i2c_fill_transmit_buf(i2c);
414}
415
416static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
417{
418 unsigned int i;
419 unsigned int len = i2c->msg->len - i2c->processed;
420 u32 uninitialized_var(val);
421 u8 byte;
422
423 /* we only care for MBRF here. */
424 if (!(ipd & REG_INT_MBRF))
425 return;
426
427 /* ack interrupt */
428 i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
429
430 /* Can only handle a maximum of 32 bytes at a time */
431 if (len > 32)
432 len = 32;
433
434 /* read the data from receive buffer */
435 for (i = 0; i < len; ++i) {
436 if (i % 4 == 0)
437 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
438
439 byte = (val >> ((i % 4) * 8)) & 0xff;
440 i2c->msg->buf[i2c->processed++] = byte;
441 }
442
443 /* are we finished? */
444 if (i2c->processed == i2c->msg->len)
445 rk3x_i2c_stop(i2c, i2c->error);
446 else
447 rk3x_i2c_prepare_read(i2c);
448}
449
450static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
451{
452 unsigned int con;
453
454 if (!(ipd & REG_INT_STOP)) {
455 rk3x_i2c_stop(i2c, -EIO);
456 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
457 rk3x_i2c_clean_ipd(i2c);
458 return;
459 }
460
461 /* ack interrupt */
462 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
463
464 /* disable STOP bit */
465 con = i2c_readl(i2c, REG_CON);
466 con &= ~REG_CON_STOP;
467 i2c_writel(i2c, con, REG_CON);
468
469 i2c->busy = false;
470 i2c->state = STATE_IDLE;
471
472 /* signal rk3x_i2c_xfer that we are finished */
473 wake_up(&i2c->wait);
474}
475
476static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
477{
478 struct rk3x_i2c *i2c = dev_id;
479 unsigned int ipd;
480
481 spin_lock(&i2c->lock);
482
483 ipd = i2c_readl(i2c, REG_IPD);
484 if (i2c->state == STATE_IDLE) {
485 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
486 rk3x_i2c_clean_ipd(i2c);
487 goto out;
488 }
489
490 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
491
492 /* Clean interrupt bits we don't care about */
493 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
494
495 if (ipd & REG_INT_NAKRCV) {
496 /*
497 * We got a NACK in the last operation. Depending on whether
498 * IGNORE_NAK is set, we have to stop the operation and report
499 * an error.
500 */
501 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
502
503 ipd &= ~REG_INT_NAKRCV;
504
505 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
506 rk3x_i2c_stop(i2c, -ENXIO);
507 }
508
509 /* is there anything left to handle? */
510 if ((ipd & REG_INT_ALL) == 0)
511 goto out;
512
513 switch (i2c->state) {
514 case STATE_START:
515 rk3x_i2c_handle_start(i2c, ipd);
516 break;
517 case STATE_WRITE:
518 rk3x_i2c_handle_write(i2c, ipd);
519 break;
520 case STATE_READ:
521 rk3x_i2c_handle_read(i2c, ipd);
522 break;
523 case STATE_STOP:
524 rk3x_i2c_handle_stop(i2c, ipd);
525 break;
526 case STATE_IDLE:
527 break;
528 }
529
530out:
531 spin_unlock(&i2c->lock);
532 return IRQ_HANDLED;
533}
534
535/**
536 * Get timing values of I2C specification
537 *
538 * @speed: Desired SCL frequency
539 *
540 * Returns: Matched i2c spec values.
541 */
542static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
543{
544 if (speed <= 100000)
545 return &standard_mode_spec;
546 else if (speed <= 400000)
547 return &fast_mode_spec;
548 else
549 return &fast_mode_plus_spec;
550}
551
552/**
553 * Calculate divider values for desired SCL frequency
554 *
555 * @clk_rate: I2C input clock rate
556 * @t: Known I2C timing information
557 * @t_calc: Caculated rk3x private timings that would be written into regs
558 *
559 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
560 * a best-effort divider value is returned in divs. If the target rate is
561 * too high, we silently use the highest possible rate.
562 */
563static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
564 struct i2c_timings *t,
565 struct rk3x_i2c_calced_timings *t_calc)
566{
567 unsigned long min_low_ns, min_high_ns;
568 unsigned long max_low_ns, min_total_ns;
569
570 unsigned long clk_rate_khz, scl_rate_khz;
571
572 unsigned long min_low_div, min_high_div;
573 unsigned long max_low_div;
574
575 unsigned long min_div_for_hold, min_total_div;
576 unsigned long extra_div, extra_low_div, ideal_low_div;
577
578 unsigned long data_hold_buffer_ns = 50;
579 const struct i2c_spec_values *spec;
580 int ret = 0;
581
582 /* Only support standard-mode and fast-mode */
583 if (WARN_ON(t->bus_freq_hz > 400000))
584 t->bus_freq_hz = 400000;
585
586 /* prevent scl_rate_khz from becoming 0 */
587 if (WARN_ON(t->bus_freq_hz < 1000))
588 t->bus_freq_hz = 1000;
589
590 /*
591 * min_low_ns: The minimum number of ns we need to hold low to
592 * meet I2C specification, should include fall time.
593 * min_high_ns: The minimum number of ns we need to hold high to
594 * meet I2C specification, should include rise time.
595 * max_low_ns: The maximum number of ns we can hold low to meet
596 * I2C specification.
597 *
598 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
599 * This is because the i2c host on Rockchip holds the data line
600 * for half the low time.
601 */
602 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
603 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
604
605 /*
606 * Timings for repeated start:
607 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
608 * - controller appears to keep SCL high for 2x programmed clk high.
609 *
610 * We need to account for those rules in picking our "high" time so
611 * we meet tSU;STA and tHD;STA times.
612 */
613 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
614 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
615 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
616 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
617 spec->min_high_ns), 2));
618
619 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
620 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
621 min_total_ns = min_low_ns + min_high_ns;
622
623 /* Adjust to avoid overflow */
624 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
625 scl_rate_khz = t->bus_freq_hz / 1000;
626
627 /*
628 * We need the total div to be >= this number
629 * so we don't clock too fast.
630 */
631 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
632
633 /* These are the min dividers needed for min hold times. */
634 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
635 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
636 min_div_for_hold = (min_low_div + min_high_div);
637
638 /*
639 * This is the maximum divider so we don't go over the maximum.
640 * We don't round up here (we round down) since this is a maximum.
641 */
642 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
643
644 if (min_low_div > max_low_div) {
645 WARN_ONCE(true,
646 "Conflicting, min_low_div %lu, max_low_div %lu\n",
647 min_low_div, max_low_div);
648 max_low_div = min_low_div;
649 }
650
651 if (min_div_for_hold > min_total_div) {
652 /*
653 * Time needed to meet hold requirements is important.
654 * Just use that.
655 */
656 t_calc->div_low = min_low_div;
657 t_calc->div_high = min_high_div;
658 } else {
659 /*
660 * We've got to distribute some time among the low and high
661 * so we don't run too fast.
662 */
663 extra_div = min_total_div - min_div_for_hold;
664
665 /*
666 * We'll try to split things up perfectly evenly,
667 * biasing slightly towards having a higher div
668 * for low (spend more time low).
669 */
670 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
671 scl_rate_khz * 8 * min_total_ns);
672
673 /* Don't allow it to go over the maximum */
674 if (ideal_low_div > max_low_div)
675 ideal_low_div = max_low_div;
676
677 /*
678 * Handle when the ideal low div is going to take up
679 * more than we have.
680 */
681 if (ideal_low_div > min_low_div + extra_div)
682 ideal_low_div = min_low_div + extra_div;
683
684 /* Give low the "ideal" and give high whatever extra is left */
685 extra_low_div = ideal_low_div - min_low_div;
686 t_calc->div_low = ideal_low_div;
687 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
688 }
689
690 /*
691 * Adjust to the fact that the hardware has an implicit "+1".
692 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
693 */
694 t_calc->div_low--;
695 t_calc->div_high--;
696
697 /* Give the tuning value 0, that would not update con register */
698 t_calc->tuning = 0;
699 /* Maximum divider supported by hw is 0xffff */
700 if (t_calc->div_low > 0xffff) {
701 t_calc->div_low = 0xffff;
702 ret = -EINVAL;
703 }
704
705 if (t_calc->div_high > 0xffff) {
706 t_calc->div_high = 0xffff;
707 ret = -EINVAL;
708 }
709
710 return ret;
711}
712
713/**
714 * Calculate timing values for desired SCL frequency
715 *
716 * @clk_rate: I2C input clock rate
717 * @t: Known I2C timing information
718 * @t_calc: Caculated rk3x private timings that would be written into regs
719 *
720 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
721 * a best-effort divider value is returned in divs. If the target rate is
722 * too high, we silently use the highest possible rate.
723 * The following formulas are v1's method to calculate timings.
724 *
725 * l = divl + 1;
726 * h = divh + 1;
727 * s = sda_update_config + 1;
728 * u = start_setup_config + 1;
729 * p = stop_setup_config + 1;
730 * T = Tclk_i2c;
731 *
732 * tHigh = 8 * h * T;
733 * tLow = 8 * l * T;
734 *
735 * tHD;sda = (l * s + 1) * T;
736 * tSU;sda = [(8 - s) * l + 1] * T;
737 * tI2C = 8 * (l + h) * T;
738 *
739 * tSU;sta = (8h * u + 1) * T;
740 * tHD;sta = [8h * (u + 1) - 1] * T;
741 * tSU;sto = (8h * p + 1) * T;
742 */
743static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
744 struct i2c_timings *t,
745 struct rk3x_i2c_calced_timings *t_calc)
746{
747 unsigned long min_low_ns, min_high_ns;
748 unsigned long min_setup_start_ns, min_setup_data_ns;
749 unsigned long min_setup_stop_ns, max_hold_data_ns;
750
751 unsigned long clk_rate_khz, scl_rate_khz;
752
753 unsigned long min_low_div, min_high_div;
754
755 unsigned long min_div_for_hold, min_total_div;
756 unsigned long extra_div, extra_low_div;
757 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
758
759 const struct i2c_spec_values *spec;
760 int ret = 0;
761
762 /* Support standard-mode, fast-mode and fast-mode plus */
763 if (WARN_ON(t->bus_freq_hz > 1000000))
764 t->bus_freq_hz = 1000000;
765
766 /* prevent scl_rate_khz from becoming 0 */
767 if (WARN_ON(t->bus_freq_hz < 1000))
768 t->bus_freq_hz = 1000;
769
770 /*
771 * min_low_ns: The minimum number of ns we need to hold low to
772 * meet I2C specification, should include fall time.
773 * min_high_ns: The minimum number of ns we need to hold high to
774 * meet I2C specification, should include rise time.
775 */
776 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
777
778 /* calculate min-divh and min-divl */
779 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
780 scl_rate_khz = t->bus_freq_hz / 1000;
781 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
782
783 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
784 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
785
786 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
787 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
788
789 /*
790 * Final divh and divl must be greater than 0, otherwise the
791 * hardware would not output the i2c clk.
792 */
793 min_high_div = (min_high_div < 1) ? 2 : min_high_div;
794 min_low_div = (min_low_div < 1) ? 2 : min_low_div;
795
796 /* These are the min dividers needed for min hold times. */
797 min_div_for_hold = (min_low_div + min_high_div);
798
799 /*
800 * This is the maximum divider so we don't go over the maximum.
801 * We don't round up here (we round down) since this is a maximum.
802 */
803 if (min_div_for_hold >= min_total_div) {
804 /*
805 * Time needed to meet hold requirements is important.
806 * Just use that.
807 */
808 t_calc->div_low = min_low_div;
809 t_calc->div_high = min_high_div;
810 } else {
811 /*
812 * We've got to distribute some time among the low and high
813 * so we don't run too fast.
814 * We'll try to split things up by the scale of min_low_div and
815 * min_high_div, biasing slightly towards having a higher div
816 * for low (spend more time low).
817 */
818 extra_div = min_total_div - min_div_for_hold;
819 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
820 min_div_for_hold);
821
822 t_calc->div_low = min_low_div + extra_low_div;
823 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
824 }
825
826 /*
827 * calculate sda data hold count by the rules, data_upd_st:3
828 * is a appropriate value to reduce calculated times.
829 */
830 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
831 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
832 * (t_calc->div_low) + 1)
833 * 1000000, clk_rate_khz);
834 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
835 * (t_calc->div_low) + 1)
836 * 1000000, clk_rate_khz);
837 if ((max_hold_data_ns < spec->max_data_hold_ns) &&
838 (min_setup_data_ns > spec->min_data_setup_ns))
839 break;
840 }
841
842 /* calculate setup start config */
843 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
844 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
845 - 1000000, 8 * 1000000 * (t_calc->div_high));
846
847 /* calculate setup stop config */
848 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
849 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
850 - 1000000, 8 * 1000000 * (t_calc->div_high));
851
852 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
853 REG_CON_STA_CFG(--stp_sta_cfg) |
854 REG_CON_STO_CFG(--stp_sto_cfg);
855
856 t_calc->div_low--;
857 t_calc->div_high--;
858
859 /* Maximum divider supported by hw is 0xffff */
860 if (t_calc->div_low > 0xffff) {
861 t_calc->div_low = 0xffff;
862 ret = -EINVAL;
863 }
864
865 if (t_calc->div_high > 0xffff) {
866 t_calc->div_high = 0xffff;
867 ret = -EINVAL;
868 }
869
870 return ret;
871}
872
873static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
874{
875 struct i2c_timings *t = &i2c->t;
876 struct rk3x_i2c_calced_timings calc;
877 u64 t_low_ns, t_high_ns;
878 unsigned long flags;
879 u32 val;
880 int ret;
881
882 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
883 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
884
885 clk_enable(i2c->pclk);
886
887 spin_lock_irqsave(&i2c->lock, flags);
888 val = i2c_readl(i2c, REG_CON);
889 val &= ~REG_CON_TUNING_MASK;
890 val |= calc.tuning;
891 i2c_writel(i2c, val, REG_CON);
892 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
893 REG_CLKDIV);
894 spin_unlock_irqrestore(&i2c->lock, flags);
895
896 clk_disable(i2c->pclk);
897
898 t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
899 t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
900 clk_rate);
901 dev_dbg(i2c->dev,
902 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
903 clk_rate / 1000,
904 1000000000 / t->bus_freq_hz,
905 t_low_ns, t_high_ns);
906}
907
908/**
909 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
910 * @nb: Pointer to notifier block
911 * @event: Notification reason
912 * @data: Pointer to notification data object
913 *
914 * The callback checks whether a valid bus frequency can be generated after the
915 * change. If so, the change is acknowledged, otherwise the change is aborted.
916 * New dividers are written to the HW in the pre- or post change notification
917 * depending on the scaling direction.
918 *
919 * Code adapted from i2c-cadence.c.
920 *
921 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
922 * to acknowledge the change, NOTIFY_DONE if the notification is
923 * considered irrelevant.
924 */
925static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
926 event, void *data)
927{
928 struct clk_notifier_data *ndata = data;
929 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
930 struct rk3x_i2c_calced_timings calc;
931
932 switch (event) {
933 case PRE_RATE_CHANGE:
934 /*
935 * Try the calculation (but don't store the result) ahead of
936 * time to see if we need to block the clock change. Timings
937 * shouldn't actually take effect until rk3x_i2c_adapt_div().
938 */
939 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
940 &calc) != 0)
941 return NOTIFY_STOP;
942
943 /* scale up */
944 if (ndata->new_rate > ndata->old_rate)
945 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
946
947 return NOTIFY_OK;
948 case POST_RATE_CHANGE:
949 /* scale down */
950 if (ndata->new_rate < ndata->old_rate)
951 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
952 return NOTIFY_OK;
953 case ABORT_RATE_CHANGE:
954 /* scale up */
955 if (ndata->new_rate > ndata->old_rate)
956 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
957 return NOTIFY_OK;
958 default:
959 return NOTIFY_DONE;
960 }
961}
962
963/**
964 * Setup I2C registers for an I2C operation specified by msgs, num.
965 *
966 * Must be called with i2c->lock held.
967 *
968 * @msgs: I2C msgs to process
969 * @num: Number of msgs
970 *
971 * returns: Number of I2C msgs processed or negative in case of error
972 */
973static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
974{
975 u32 addr = (msgs[0].addr & 0x7f) << 1;
976 int ret = 0;
977
978 /*
979 * The I2C adapter can issue a small (len < 4) write packet before
980 * reading. This speeds up SMBus-style register reads.
981 * The MRXADDR/MRXRADDR hold the slave address and the slave register
982 * address in this case.
983 */
984
985 if (num >= 2 && msgs[0].len < 4 &&
986 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
987 u32 reg_addr = 0;
988 int i;
989
990 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
991 addr >> 1);
992
993 /* Fill MRXRADDR with the register address(es) */
994 for (i = 0; i < msgs[0].len; ++i) {
995 reg_addr |= msgs[0].buf[i] << (i * 8);
996 reg_addr |= REG_MRXADDR_VALID(i);
997 }
998
999 /* msgs[0] is handled by hw. */
1000 i2c->msg = &msgs[1];
1001
1002 i2c->mode = REG_CON_MOD_REGISTER_TX;
1003
1004 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1005 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1006
1007 ret = 2;
1008 } else {
1009 /*
1010 * We'll have to do it the boring way and process the msgs
1011 * one-by-one.
1012 */
1013
1014 if (msgs[0].flags & I2C_M_RD) {
1015 addr |= 1; /* set read bit */
1016
1017 /*
1018 * We have to transmit the slave addr first. Use
1019 * MOD_REGISTER_TX for that purpose.
1020 */
1021 i2c->mode = REG_CON_MOD_REGISTER_TX;
1022 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
1023 REG_MRXADDR);
1024 i2c_writel(i2c, 0, REG_MRXRADDR);
1025 } else {
1026 i2c->mode = REG_CON_MOD_TX;
1027 }
1028
1029 i2c->msg = &msgs[0];
1030
1031 ret = 1;
1032 }
1033
1034 i2c->addr = msgs[0].addr;
1035 i2c->busy = true;
1036 i2c->state = STATE_START;
1037 i2c->processed = 0;
1038 i2c->error = 0;
1039
1040 rk3x_i2c_clean_ipd(i2c);
1041
1042 return ret;
1043}
1044
1045static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1046 struct i2c_msg *msgs, int num)
1047{
1048 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1049 unsigned long timeout, flags;
1050 u32 val;
1051 int ret = 0;
1052 int i;
1053
1054 spin_lock_irqsave(&i2c->lock, flags);
1055
1056 clk_enable(i2c->clk);
1057 clk_enable(i2c->pclk);
1058
1059 i2c->is_last_msg = false;
1060
1061 /*
1062 * Process msgs. We can handle more than one message at once (see
1063 * rk3x_i2c_setup()).
1064 */
1065 for (i = 0; i < num; i += ret) {
1066 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1067
1068 if (ret < 0) {
1069 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1070 break;
1071 }
1072
1073 if (i + ret >= num)
1074 i2c->is_last_msg = true;
1075
1076 spin_unlock_irqrestore(&i2c->lock, flags);
1077
1078 rk3x_i2c_start(i2c);
1079
1080 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
1081 msecs_to_jiffies(WAIT_TIMEOUT));
1082
1083 spin_lock_irqsave(&i2c->lock, flags);
1084
1085 if (timeout == 0) {
1086 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1087 i2c_readl(i2c, REG_IPD), i2c->state);
1088
1089 /* Force a STOP condition without interrupt */
1090 i2c_writel(i2c, 0, REG_IEN);
1091 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1092 val |= REG_CON_EN | REG_CON_STOP;
1093 i2c_writel(i2c, val, REG_CON);
1094
1095 i2c->state = STATE_IDLE;
1096
1097 ret = -ETIMEDOUT;
1098 break;
1099 }
1100
1101 if (i2c->error) {
1102 ret = i2c->error;
1103 break;
1104 }
1105 }
1106
1107 clk_disable(i2c->pclk);
1108 clk_disable(i2c->clk);
1109
1110 spin_unlock_irqrestore(&i2c->lock, flags);
1111
1112 return ret < 0 ? ret : num;
1113}
1114
1115static __maybe_unused int rk3x_i2c_resume(struct device *dev)
1116{
1117 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1118
1119 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1120
1121 return 0;
1122}
1123
1124static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1125{
1126 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1127}
1128
1129static const struct i2c_algorithm rk3x_i2c_algorithm = {
1130 .master_xfer = rk3x_i2c_xfer,
1131 .functionality = rk3x_i2c_func,
1132};
1133
1134static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1135 .grf_offset = 0x154,
1136 .calc_timings = rk3x_i2c_v0_calc_timings,
1137};
1138
1139static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1140 .grf_offset = 0x0a4,
1141 .calc_timings = rk3x_i2c_v0_calc_timings,
1142};
1143
1144static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1145 .grf_offset = -1,
1146 .calc_timings = rk3x_i2c_v0_calc_timings,
1147};
1148
1149static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1150 .grf_offset = -1,
1151 .calc_timings = rk3x_i2c_v0_calc_timings,
1152};
1153
1154static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1155 .grf_offset = -1,
1156 .calc_timings = rk3x_i2c_v1_calc_timings,
1157};
1158
1159static const struct of_device_id rk3x_i2c_match[] = {
1160 {
1161 .compatible = "rockchip,rk3066-i2c",
1162 .data = (void *)&rk3066_soc_data
1163 },
1164 {
1165 .compatible = "rockchip,rk3188-i2c",
1166 .data = (void *)&rk3188_soc_data
1167 },
1168 {
1169 .compatible = "rockchip,rk3228-i2c",
1170 .data = (void *)&rk3228_soc_data
1171 },
1172 {
1173 .compatible = "rockchip,rk3288-i2c",
1174 .data = (void *)&rk3288_soc_data
1175 },
1176 {
1177 .compatible = "rockchip,rk3399-i2c",
1178 .data = (void *)&rk3399_soc_data
1179 },
1180 {},
1181};
1182MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1183
1184static int rk3x_i2c_probe(struct platform_device *pdev)
1185{
1186 struct device_node *np = pdev->dev.of_node;
1187 const struct of_device_id *match;
1188 struct rk3x_i2c *i2c;
1189 struct resource *mem;
1190 int ret = 0;
1191 int bus_nr;
1192 u32 value;
1193 int irq;
1194 unsigned long clk_rate;
1195
1196 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1197 if (!i2c)
1198 return -ENOMEM;
1199
1200 match = of_match_node(rk3x_i2c_match, np);
1201 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
1202
1203 /* use common interface to get I2C timing properties */
1204 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1205
1206 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1207 i2c->adap.owner = THIS_MODULE;
1208 i2c->adap.algo = &rk3x_i2c_algorithm;
1209 i2c->adap.retries = 3;
1210 i2c->adap.dev.of_node = np;
1211 i2c->adap.algo_data = i2c;
1212 i2c->adap.dev.parent = &pdev->dev;
1213
1214 i2c->dev = &pdev->dev;
1215
1216 spin_lock_init(&i2c->lock);
1217 init_waitqueue_head(&i2c->wait);
1218
1219 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
1221 if (IS_ERR(i2c->regs))
1222 return PTR_ERR(i2c->regs);
1223
1224 /* Try to set the I2C adapter number from dt */
1225 bus_nr = of_alias_get_id(np, "i2c");
1226
1227 /*
1228 * Switch to new interface if the SoC also offers the old one.
1229 * The control bit is located in the GRF register space.
1230 */
1231 if (i2c->soc_data->grf_offset >= 0) {
1232 struct regmap *grf;
1233
1234 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1235 if (IS_ERR(grf)) {
1236 dev_err(&pdev->dev,
1237 "rk3x-i2c needs 'rockchip,grf' property\n");
1238 return PTR_ERR(grf);
1239 }
1240
1241 if (bus_nr < 0) {
1242 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1243 return -EINVAL;
1244 }
1245
1246 /* 27+i: write mask, 11+i: value */
1247 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1248
1249 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1250 if (ret != 0) {
1251 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1252 return ret;
1253 }
1254 }
1255
1256 /* IRQ setup */
1257 irq = platform_get_irq(pdev, 0);
1258 if (irq < 0) {
1259 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
1260 return irq;
1261 }
1262
1263 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1264 0, dev_name(&pdev->dev), i2c);
1265 if (ret < 0) {
1266 dev_err(&pdev->dev, "cannot request IRQ\n");
1267 return ret;
1268 }
1269
1270 platform_set_drvdata(pdev, i2c);
1271
1272 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1273 /* Only one clock to use for bus clock and peripheral clock */
1274 i2c->clk = devm_clk_get(&pdev->dev, NULL);
1275 i2c->pclk = i2c->clk;
1276 } else {
1277 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1278 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1279 }
1280
1281 if (IS_ERR(i2c->clk)) {
1282 ret = PTR_ERR(i2c->clk);
1283 if (ret != -EPROBE_DEFER)
1284 dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret);
1285 return ret;
1286 }
1287 if (IS_ERR(i2c->pclk)) {
1288 ret = PTR_ERR(i2c->pclk);
1289 if (ret != -EPROBE_DEFER)
1290 dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret);
1291 return ret;
1292 }
1293
1294 ret = clk_prepare(i2c->clk);
1295 if (ret < 0) {
1296 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1297 return ret;
1298 }
1299 ret = clk_prepare(i2c->pclk);
1300 if (ret < 0) {
1301 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1302 goto err_clk;
1303 }
1304
1305 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1306 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1307 if (ret != 0) {
1308 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1309 goto err_pclk;
1310 }
1311
1312 clk_rate = clk_get_rate(i2c->clk);
1313 rk3x_i2c_adapt_div(i2c, clk_rate);
1314
1315 ret = i2c_add_adapter(&i2c->adap);
1316 if (ret < 0)
1317 goto err_clk_notifier;
1318
1319 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
1320
1321 return 0;
1322
1323err_clk_notifier:
1324 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1325err_pclk:
1326 clk_unprepare(i2c->pclk);
1327err_clk:
1328 clk_unprepare(i2c->clk);
1329 return ret;
1330}
1331
1332static int rk3x_i2c_remove(struct platform_device *pdev)
1333{
1334 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1335
1336 i2c_del_adapter(&i2c->adap);
1337
1338 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1339 clk_unprepare(i2c->pclk);
1340 clk_unprepare(i2c->clk);
1341
1342 return 0;
1343}
1344
1345static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume);
1346
1347static struct platform_driver rk3x_i2c_driver = {
1348 .probe = rk3x_i2c_probe,
1349 .remove = rk3x_i2c_remove,
1350 .driver = {
1351 .name = "rk3x-i2c",
1352 .of_match_table = rk3x_i2c_match,
1353 .pm = &rk3x_i2c_pm_ops,
1354 },
1355};
1356
1357module_platform_driver(rk3x_i2c_driver);
1358
1359MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1360MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1361MODULE_LICENSE("GPL v2");