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1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/version.h>
26
27#define N_DATA_REGS 8
28
29/*
30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
31 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
32 * data register whereas STB SoCs use 4 byte per data register transfer,
33 * account for this difference in total count per transaction and mask to
34 * use.
35 */
36#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
37#define BSC_CNT_REG1_SHIFT 0
38
39/* BSC CTL register field definitions */
40#define BSC_CTL_REG_DTF_MASK 0x00000003
41#define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
42#define BSC_CTL_REG_SCL_SEL_SHIFT 4
43#define BSC_CTL_REG_INT_EN_MASK 0x00000040
44#define BSC_CTL_REG_INT_EN_SHIFT 6
45#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
46
47/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
48#define BSC_IIC_EN_RESTART_MASK 0x00000040
49#define BSC_IIC_EN_NOSTART_MASK 0x00000020
50#define BSC_IIC_EN_NOSTOP_MASK 0x00000010
51#define BSC_IIC_EN_NOACK_MASK 0x00000004
52#define BSC_IIC_EN_INTRP_MASK 0x00000002
53#define BSC_IIC_EN_ENABLE_MASK 0x00000001
54
55/* BSC_CTLHI control register field definitions */
56#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
57#define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
58#define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
59#define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
60
61#define I2C_TIMEOUT 100 /* msecs */
62
63/* Condition mask used for non combined transfer */
64#define COND_RESTART BSC_IIC_EN_RESTART_MASK
65#define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
66#define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
67#define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
68
69/* BSC data transfer direction */
70#define DTF_WR_MASK 0x00000000
71#define DTF_RD_MASK 0x00000001
72/* BSC data transfer direction combined format */
73#define DTF_RD_WR_MASK 0x00000002
74#define DTF_WR_RD_MASK 0x00000003
75
76#define INT_ENABLE true
77#define INT_DISABLE false
78
79/* BSC block register map structure to cache fields to be written */
80struct bsc_regs {
81 u32 chip_address; /* slave address */
82 u32 data_in[N_DATA_REGS]; /* tx data buffer*/
83 u32 cnt_reg; /* rx/tx data length */
84 u32 ctl_reg; /* control register */
85 u32 iic_enable; /* xfer enable and status */
86 u32 data_out[N_DATA_REGS]; /* rx data buffer */
87 u32 ctlhi_reg; /* more control fields */
88 u32 scl_param; /* reserved */
89};
90
91struct bsc_clk_param {
92 u32 hz;
93 u32 scl_mask;
94 u32 div_mask;
95};
96
97enum bsc_xfer_cmd {
98 CMD_WR,
99 CMD_RD,
100 CMD_WR_NOACK,
101 CMD_RD_NOACK,
102};
103
104static char const *cmd_string[] = {
105 [CMD_WR] = "WR",
106 [CMD_RD] = "RD",
107 [CMD_WR_NOACK] = "WR NOACK",
108 [CMD_RD_NOACK] = "RD NOACK",
109};
110
111enum bus_speeds {
112 SPD_375K,
113 SPD_390K,
114 SPD_187K,
115 SPD_200K,
116 SPD_93K,
117 SPD_97K,
118 SPD_46K,
119 SPD_50K
120};
121
122static const struct bsc_clk_param bsc_clk[] = {
123 [SPD_375K] = {
124 .hz = 375000,
125 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
126 .div_mask = 0
127 },
128 [SPD_390K] = {
129 .hz = 390000,
130 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
131 .div_mask = 0
132 },
133 [SPD_187K] = {
134 .hz = 187500,
135 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
136 .div_mask = 0
137 },
138 [SPD_200K] = {
139 .hz = 200000,
140 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
141 .div_mask = 0
142 },
143 [SPD_93K] = {
144 .hz = 93750,
145 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
147 },
148 [SPD_97K] = {
149 .hz = 97500,
150 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
152 },
153 [SPD_46K] = {
154 .hz = 46875,
155 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
157 },
158 [SPD_50K] = {
159 .hz = 50000,
160 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
162 }
163};
164
165struct brcmstb_i2c_dev {
166 struct device *device;
167 void __iomem *base;
168 void __iomem *irq_base;
169 int irq;
170 struct bsc_regs *bsc_regmap;
171 struct i2c_adapter adapter;
172 struct completion done;
173 bool is_suspended;
174 u32 clk_freq_hz;
175 int data_regsz;
176};
177
178/* register accessors for both be and le cpu arch */
179#ifdef CONFIG_CPU_BIG_ENDIAN
180#define __bsc_readl(_reg) ioread32be(_reg)
181#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
182#else
183#define __bsc_readl(_reg) ioread32(_reg)
184#define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
185#endif
186
187#define bsc_readl(_dev, _reg) \
188 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
189
190#define bsc_writel(_dev, _val, _reg) \
191 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
192
193static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
194{
195 return (N_DATA_REGS * dev->data_regsz);
196}
197
198static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
199{
200 return dev->data_regsz;
201}
202
203static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
204 bool int_en)
205{
206
207 if (int_en)
208 /* Enable BSC CTL interrupt line */
209 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
210 else
211 /* Disable BSC CTL interrupt line */
212 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
213
214 barrier();
215 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
216}
217
218static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
219{
220 struct brcmstb_i2c_dev *dev = devid;
221 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
222 u32 status_iic_intrp = bsc_readl(dev, iic_enable);
223
224 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
225 status_bsc_ctl, status_iic_intrp);
226
227 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
228 return IRQ_NONE;
229
230 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
231 complete(&dev->done);
232
233 dev_dbg(dev->device, "isr handled");
234 return IRQ_HANDLED;
235}
236
237/* Wait for device to be ready */
238static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
239{
240 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
241
242 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
243 if (time_after(jiffies, timeout))
244 return -ETIMEDOUT;
245 cpu_relax();
246 }
247 return 0;
248}
249
250/* i2c xfer completion function, handles both irq and polling mode */
251static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
252{
253 int ret = 0;
254 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
255
256 if (dev->irq >= 0) {
257 if (!wait_for_completion_timeout(&dev->done, timeout))
258 ret = -ETIMEDOUT;
259 } else {
260 /* we are in polling mode */
261 u32 bsc_intrp;
262 unsigned long time_left = jiffies + timeout;
263
264 do {
265 bsc_intrp = bsc_readl(dev, iic_enable) &
266 BSC_IIC_EN_INTRP_MASK;
267 if (time_after(jiffies, time_left)) {
268 ret = -ETIMEDOUT;
269 break;
270 }
271 cpu_relax();
272 } while (!bsc_intrp);
273 }
274
275 if (dev->irq < 0 || ret == -ETIMEDOUT)
276 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
277
278 return ret;
279}
280
281/* Set xfer START/STOP conditions for subsequent transfer */
282static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
283 u32 cond_flag)
284{
285 u32 regval = dev->bsc_regmap->iic_enable;
286
287 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
288}
289
290/* Send I2C request check completion */
291static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
292 enum bsc_xfer_cmd cmd)
293{
294 int rc = 0;
295 struct bsc_regs *pi2creg = dev->bsc_regmap;
296
297 /* Make sure the hardware is ready */
298 rc = brcmstb_i2c_wait_if_busy(dev);
299 if (rc < 0)
300 return rc;
301
302 /* only if we are in interrupt mode */
303 if (dev->irq >= 0)
304 reinit_completion(&dev->done);
305
306 /* enable BSC CTL interrupt line */
307 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
308
309 /* initiate transfer by setting iic_enable */
310 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
311 bsc_writel(dev, pi2creg->iic_enable, iic_enable);
312
313 /* Wait for transaction to finish or timeout */
314 rc = brcmstb_i2c_wait_for_completion(dev);
315 if (rc) {
316 dev_dbg(dev->device, "intr timeout for cmd %s\n",
317 cmd_string[cmd]);
318 goto cmd_out;
319 }
320
321 if ((CMD_RD || CMD_WR) &&
322 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
323 rc = -EREMOTEIO;
324 dev_dbg(dev->device, "controller received NOACK intr for %s\n",
325 cmd_string[cmd]);
326 }
327
328cmd_out:
329 bsc_writel(dev, 0, cnt_reg);
330 bsc_writel(dev, 0, iic_enable);
331
332 return rc;
333}
334
335/* Actual data transfer through the BSC master */
336static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
337 u8 *buf, unsigned int len,
338 struct i2c_msg *pmsg)
339{
340 int cnt, byte, i, rc;
341 enum bsc_xfer_cmd cmd;
342 u32 ctl_reg;
343 struct bsc_regs *pi2creg = dev->bsc_regmap;
344 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
345 int data_regsz = brcmstb_i2c_get_data_regsz(dev);
346
347 /* see if the transaction needs to check NACK conditions */
348 if (no_ack) {
349 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
350 : CMD_WR_NOACK;
351 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
352 } else {
353 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
354 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
355 }
356 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
357
358 /* set data transfer direction */
359 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
360 if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
361 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
362 else
363 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
364
365 /* set the read/write length */
366 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
367 (len << BSC_CNT_REG1_SHIFT), cnt_reg);
368
369 /* Write data into data_in register */
370
371 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
372 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
373 u32 word = 0;
374
375 for (byte = 0; byte < data_regsz; byte++) {
376 word >>= BITS_PER_BYTE;
377 if ((cnt + byte) < len)
378 word |= buf[cnt + byte] <<
379 (BITS_PER_BYTE * (data_regsz - 1));
380 }
381 bsc_writel(dev, word, data_in[i]);
382 }
383 }
384
385 /* Initiate xfer, the function will return on completion */
386 rc = brcmstb_send_i2c_cmd(dev, cmd);
387
388 if (rc != 0) {
389 dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
390 return rc;
391 }
392
393 /* Read data from data_out register */
394 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
395 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
396 u32 data = bsc_readl(dev, data_out[i]);
397
398 for (byte = 0; byte < data_regsz &&
399 (byte + cnt) < len; byte++) {
400 buf[cnt + byte] = data & 0xff;
401 data >>= BITS_PER_BYTE;
402 }
403 }
404 }
405
406 return 0;
407}
408
409/* Write a single byte of data to the i2c bus */
410static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
411 u8 *buf, unsigned int nak_expected)
412{
413 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
414
415 bsc_writel(dev, 1, cnt_reg);
416 bsc_writel(dev, *buf, data_in);
417
418 return brcmstb_send_i2c_cmd(dev, cmd);
419}
420
421/* Send i2c address */
422static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
423 struct i2c_msg *msg)
424{
425 unsigned char addr;
426
427 if (msg->flags & I2C_M_TEN) {
428 /* First byte is 11110XX0 where XX is upper 2 bits */
429 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
430 bsc_writel(dev, addr, chip_address);
431
432 /* Second byte is the remaining 8 bits */
433 addr = msg->addr & 0xFF;
434 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
435 return -EREMOTEIO;
436
437 if (msg->flags & I2C_M_RD) {
438 /* For read, send restart without stop condition */
439 brcmstb_set_i2c_start_stop(dev, COND_RESTART
440 | COND_NOSTOP);
441 /* Then re-send the first byte with the read bit set */
442 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
443 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
444 return -EREMOTEIO;
445
446 }
447 } else {
448 addr = i2c_8bit_addr_from_msg(msg);
449
450 bsc_writel(dev, addr, chip_address);
451 }
452
453 return 0;
454}
455
456/* Master transfer function */
457static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
458 struct i2c_msg msgs[], int num)
459{
460 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
461 struct i2c_msg *pmsg;
462 int rc = 0;
463 int i;
464 int bytes_to_xfer;
465 u8 *tmp_buf;
466 int len = 0;
467 int xfersz = brcmstb_i2c_get_xfersz(dev);
468
469 if (dev->is_suspended)
470 return -EBUSY;
471
472 /* Loop through all messages */
473 for (i = 0; i < num; i++) {
474 pmsg = &msgs[i];
475 len = pmsg->len;
476 tmp_buf = pmsg->buf;
477
478 dev_dbg(dev->device,
479 "msg# %d/%d flg %x buf %x len %d\n", i,
480 num - 1, pmsg->flags,
481 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
482
483 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
484 brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP));
485 else
486 brcmstb_set_i2c_start_stop(dev,
487 COND_RESTART | COND_NOSTOP);
488
489 /* Send slave address */
490 if (!(pmsg->flags & I2C_M_NOSTART)) {
491 rc = brcmstb_i2c_do_addr(dev, pmsg);
492 if (rc < 0) {
493 dev_dbg(dev->device,
494 "NACK for addr %2.2x msg#%d rc = %d\n",
495 pmsg->addr, i, rc);
496 goto out;
497 }
498 }
499
500 /* Perform data transfer */
501 while (len) {
502 bytes_to_xfer = min(len, xfersz);
503
504 if (len <= xfersz && i == (num - 1))
505 brcmstb_set_i2c_start_stop(dev,
506 ~(COND_START_STOP));
507
508 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
509 bytes_to_xfer, pmsg);
510 if (rc < 0)
511 goto out;
512
513 len -= bytes_to_xfer;
514 tmp_buf += bytes_to_xfer;
515 }
516 }
517
518 rc = num;
519out:
520 return rc;
521
522}
523
524static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
525{
526 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
527 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
528}
529
530static const struct i2c_algorithm brcmstb_i2c_algo = {
531 .master_xfer = brcmstb_i2c_xfer,
532 .functionality = brcmstb_i2c_functionality,
533};
534
535static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
536{
537 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
538 u32 clk_freq_hz = dev->clk_freq_hz;
539
540 for (i = 0; i < num_speeds; i++) {
541 if (bsc_clk[i].hz == clk_freq_hz) {
542 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
543 | BSC_CTL_REG_DIV_CLK_MASK);
544 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
545 bsc_clk[i].div_mask);
546 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
547 break;
548 }
549 }
550
551 /* in case we did not get find a valid speed */
552 if (i == num_speeds) {
553 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
554 BSC_CTL_REG_SCL_SEL_SHIFT;
555 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
556 bsc_clk[i].hz);
557 }
558}
559
560static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
561{
562 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
563 /* set 4 byte data in/out xfers */
564 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
565 else
566 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
567
568 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
569 /* set bus speed */
570 brcmstb_i2c_set_bus_speed(dev);
571}
572
573static int brcmstb_i2c_probe(struct platform_device *pdev)
574{
575 int rc = 0;
576 struct brcmstb_i2c_dev *dev;
577 struct i2c_adapter *adap;
578 struct resource *iomem;
579 const char *int_name;
580
581 /* Allocate memory for private data structure */
582 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
583 if (!dev)
584 return -ENOMEM;
585
586 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
587 if (!dev->bsc_regmap)
588 return -ENOMEM;
589
590 platform_set_drvdata(pdev, dev);
591 dev->device = &pdev->dev;
592 init_completion(&dev->done);
593
594 /* Map hardware registers */
595 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
596 dev->base = devm_ioremap_resource(dev->device, iomem);
597 if (IS_ERR(dev->base)) {
598 rc = -ENOMEM;
599 goto probe_errorout;
600 }
601
602 rc = of_property_read_string(dev->device->of_node, "interrupt-names",
603 &int_name);
604 if (rc < 0)
605 int_name = NULL;
606
607 /* Get the interrupt number */
608 dev->irq = platform_get_irq(pdev, 0);
609
610 /* disable the bsc interrupt line */
611 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
612
613 /* register the ISR handler */
614 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
615 IRQF_SHARED,
616 int_name ? int_name : pdev->name,
617 dev);
618
619 if (rc) {
620 dev_dbg(dev->device, "falling back to polling mode");
621 dev->irq = -1;
622 }
623
624 if (of_property_read_u32(dev->device->of_node,
625 "clock-frequency", &dev->clk_freq_hz)) {
626 dev_warn(dev->device, "setting clock-frequency@%dHz\n",
627 bsc_clk[0].hz);
628 dev->clk_freq_hz = bsc_clk[0].hz;
629 }
630
631 /* set the data in/out register size for compatible SoCs */
632 if (of_device_is_compatible(dev->device->of_node,
633 "brcmstb,brcmper-i2c"))
634 dev->data_regsz = sizeof(u8);
635 else
636 dev->data_regsz = sizeof(u32);
637
638 brcmstb_i2c_set_bsc_reg_defaults(dev);
639
640 /* Add the i2c adapter */
641 adap = &dev->adapter;
642 i2c_set_adapdata(adap, dev);
643 adap->owner = THIS_MODULE;
644 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
645 if (int_name)
646 strlcat(adap->name, int_name, sizeof(adap->name));
647 adap->algo = &brcmstb_i2c_algo;
648 adap->dev.parent = &pdev->dev;
649 adap->dev.of_node = pdev->dev.of_node;
650 rc = i2c_add_adapter(adap);
651 if (rc)
652 goto probe_errorout;
653
654 dev_info(dev->device, "%s@%dhz registered in %s mode\n",
655 int_name ? int_name : " ", dev->clk_freq_hz,
656 (dev->irq >= 0) ? "interrupt" : "polling");
657
658 return 0;
659
660probe_errorout:
661 return rc;
662}
663
664static int brcmstb_i2c_remove(struct platform_device *pdev)
665{
666 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
667
668 i2c_del_adapter(&dev->adapter);
669 return 0;
670}
671
672#ifdef CONFIG_PM_SLEEP
673static int brcmstb_i2c_suspend(struct device *dev)
674{
675 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
676
677 i2c_lock_adapter(&i2c_dev->adapter);
678 i2c_dev->is_suspended = true;
679 i2c_unlock_adapter(&i2c_dev->adapter);
680
681 return 0;
682}
683
684static int brcmstb_i2c_resume(struct device *dev)
685{
686 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
687
688 i2c_lock_adapter(&i2c_dev->adapter);
689 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
690 i2c_dev->is_suspended = false;
691 i2c_unlock_adapter(&i2c_dev->adapter);
692
693 return 0;
694}
695#endif
696
697static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
698 brcmstb_i2c_resume);
699
700static const struct of_device_id brcmstb_i2c_of_match[] = {
701 {.compatible = "brcm,brcmstb-i2c"},
702 {.compatible = "brcm,brcmper-i2c"},
703 {},
704};
705MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
706
707static struct platform_driver brcmstb_i2c_driver = {
708 .driver = {
709 .name = "brcmstb-i2c",
710 .of_match_table = brcmstb_i2c_of_match,
711 .pm = &brcmstb_i2c_pm,
712 },
713 .probe = brcmstb_i2c_probe,
714 .remove = brcmstb_i2c_remove,
715};
716module_platform_driver(brcmstb_i2c_driver);
717
718MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
719MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
720MODULE_LICENSE("GPL v2");