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1/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * Description: CoreSight Embedded Trace Buffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <asm/local.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/device.h>
20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/uaccess.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/pm_runtime.h>
28#include <linux/seq_file.h>
29#include <linux/coresight.h>
30#include <linux/amba/bus.h>
31#include <linux/clk.h>
32#include <linux/circ_buf.h>
33#include <linux/mm.h>
34#include <linux/perf_event.h>
35
36#include <asm/local.h>
37
38#include "coresight-priv.h"
39
40#define ETB_RAM_DEPTH_REG 0x004
41#define ETB_STATUS_REG 0x00c
42#define ETB_RAM_READ_DATA_REG 0x010
43#define ETB_RAM_READ_POINTER 0x014
44#define ETB_RAM_WRITE_POINTER 0x018
45#define ETB_TRG 0x01c
46#define ETB_CTL_REG 0x020
47#define ETB_RWD_REG 0x024
48#define ETB_FFSR 0x300
49#define ETB_FFCR 0x304
50#define ETB_ITMISCOP0 0xee0
51#define ETB_ITTRFLINACK 0xee4
52#define ETB_ITTRFLIN 0xee8
53#define ETB_ITATBDATA0 0xeeC
54#define ETB_ITATBCTR2 0xef0
55#define ETB_ITATBCTR1 0xef4
56#define ETB_ITATBCTR0 0xef8
57
58/* register description */
59/* STS - 0x00C */
60#define ETB_STATUS_RAM_FULL BIT(0)
61/* CTL - 0x020 */
62#define ETB_CTL_CAPT_EN BIT(0)
63/* FFCR - 0x304 */
64#define ETB_FFCR_EN_FTC BIT(0)
65#define ETB_FFCR_FON_MAN BIT(6)
66#define ETB_FFCR_STOP_FI BIT(12)
67#define ETB_FFCR_STOP_TRIGGER BIT(13)
68
69#define ETB_FFCR_BIT 6
70#define ETB_FFSR_BIT 1
71#define ETB_FRAME_SIZE_WORDS 4
72
73/**
74 * struct etb_drvdata - specifics associated to an ETB component
75 * @base: memory mapped base address for this component.
76 * @dev: the device entity associated to this component.
77 * @atclk: optional clock for the core parts of the ETB.
78 * @csdev: component vitals needed by the framework.
79 * @miscdev: specifics to handle "/dev/xyz.etb" entry.
80 * @spinlock: only one at a time pls.
81 * @reading: synchronise user space access to etb buffer.
82 * @mode: this ETB is being used.
83 * @buf: area of memory where ETB buffer content gets sent.
84 * @buffer_depth: size of @buf.
85 * @trigger_cntr: amount of words to store after a trigger.
86 */
87struct etb_drvdata {
88 void __iomem *base;
89 struct device *dev;
90 struct clk *atclk;
91 struct coresight_device *csdev;
92 struct miscdevice miscdev;
93 spinlock_t spinlock;
94 local_t reading;
95 local_t mode;
96 u8 *buf;
97 u32 buffer_depth;
98 u32 trigger_cntr;
99};
100
101static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
102{
103 u32 depth = 0;
104
105 pm_runtime_get_sync(drvdata->dev);
106
107 /* RO registers don't need locking */
108 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
109
110 pm_runtime_put(drvdata->dev);
111 return depth;
112}
113
114static void etb_enable_hw(struct etb_drvdata *drvdata)
115{
116 int i;
117 u32 depth;
118
119 CS_UNLOCK(drvdata->base);
120
121 depth = drvdata->buffer_depth;
122 /* reset write RAM pointer address */
123 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
124 /* clear entire RAM buffer */
125 for (i = 0; i < depth; i++)
126 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
127
128 /* reset write RAM pointer address */
129 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
130 /* reset read RAM pointer address */
131 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
132
133 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
134 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
135 drvdata->base + ETB_FFCR);
136 /* ETB trace capture enable */
137 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
138
139 CS_LOCK(drvdata->base);
140}
141
142static int etb_enable(struct coresight_device *csdev, u32 mode)
143{
144 u32 val;
145 unsigned long flags;
146 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
147
148 val = local_cmpxchg(&drvdata->mode,
149 CS_MODE_DISABLED, mode);
150 /*
151 * When accessing from Perf, a HW buffer can be handled
152 * by a single trace entity. In sysFS mode many tracers
153 * can be logging to the same HW buffer.
154 */
155 if (val == CS_MODE_PERF)
156 return -EBUSY;
157
158 /* Nothing to do, the tracer is already enabled. */
159 if (val == CS_MODE_SYSFS)
160 goto out;
161
162 spin_lock_irqsave(&drvdata->spinlock, flags);
163 etb_enable_hw(drvdata);
164 spin_unlock_irqrestore(&drvdata->spinlock, flags);
165
166out:
167 dev_info(drvdata->dev, "ETB enabled\n");
168 return 0;
169}
170
171static void etb_disable_hw(struct etb_drvdata *drvdata)
172{
173 u32 ffcr;
174
175 CS_UNLOCK(drvdata->base);
176
177 ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
178 /* stop formatter when a stop has completed */
179 ffcr |= ETB_FFCR_STOP_FI;
180 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
181 /* manually generate a flush of the system */
182 ffcr |= ETB_FFCR_FON_MAN;
183 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
184
185 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
186 dev_err(drvdata->dev,
187 "timeout while waiting for completion of Manual Flush\n");
188 }
189
190 /* disable trace capture */
191 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
192
193 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
194 dev_err(drvdata->dev,
195 "timeout while waiting for Formatter to Stop\n");
196 }
197
198 CS_LOCK(drvdata->base);
199}
200
201static void etb_dump_hw(struct etb_drvdata *drvdata)
202{
203 int i;
204 u8 *buf_ptr;
205 u32 read_data, depth;
206 u32 read_ptr, write_ptr;
207 u32 frame_off, frame_endoff;
208
209 CS_UNLOCK(drvdata->base);
210
211 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
212 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
213
214 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
215 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
216 if (frame_off) {
217 dev_err(drvdata->dev,
218 "write_ptr: %lu not aligned to formatter frame size\n",
219 (unsigned long)write_ptr);
220 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
221 (unsigned long)frame_off, (unsigned long)frame_endoff);
222 write_ptr += frame_endoff;
223 }
224
225 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
226 & ETB_STATUS_RAM_FULL) == 0)
227 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
228 else
229 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
230
231 depth = drvdata->buffer_depth;
232 buf_ptr = drvdata->buf;
233 for (i = 0; i < depth; i++) {
234 read_data = readl_relaxed(drvdata->base +
235 ETB_RAM_READ_DATA_REG);
236 *buf_ptr++ = read_data >> 0;
237 *buf_ptr++ = read_data >> 8;
238 *buf_ptr++ = read_data >> 16;
239 *buf_ptr++ = read_data >> 24;
240 }
241
242 if (frame_off) {
243 buf_ptr -= (frame_endoff * 4);
244 for (i = 0; i < frame_endoff; i++) {
245 *buf_ptr++ = 0x0;
246 *buf_ptr++ = 0x0;
247 *buf_ptr++ = 0x0;
248 *buf_ptr++ = 0x0;
249 }
250 }
251
252 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
253
254 CS_LOCK(drvdata->base);
255}
256
257static void etb_disable(struct coresight_device *csdev)
258{
259 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
260 unsigned long flags;
261
262 spin_lock_irqsave(&drvdata->spinlock, flags);
263 etb_disable_hw(drvdata);
264 etb_dump_hw(drvdata);
265 spin_unlock_irqrestore(&drvdata->spinlock, flags);
266
267 local_set(&drvdata->mode, CS_MODE_DISABLED);
268
269 dev_info(drvdata->dev, "ETB disabled\n");
270}
271
272static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
273 void **pages, int nr_pages, bool overwrite)
274{
275 int node;
276 struct cs_buffers *buf;
277
278 if (cpu == -1)
279 cpu = smp_processor_id();
280 node = cpu_to_node(cpu);
281
282 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
283 if (!buf)
284 return NULL;
285
286 buf->snapshot = overwrite;
287 buf->nr_pages = nr_pages;
288 buf->data_pages = pages;
289
290 return buf;
291}
292
293static void etb_free_buffer(void *config)
294{
295 struct cs_buffers *buf = config;
296
297 kfree(buf);
298}
299
300static int etb_set_buffer(struct coresight_device *csdev,
301 struct perf_output_handle *handle,
302 void *sink_config)
303{
304 int ret = 0;
305 unsigned long head;
306 struct cs_buffers *buf = sink_config;
307
308 /* wrap head around to the amount of space we have */
309 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
310
311 /* find the page to write to */
312 buf->cur = head / PAGE_SIZE;
313
314 /* and offset within that page */
315 buf->offset = head % PAGE_SIZE;
316
317 local_set(&buf->data_size, 0);
318
319 return ret;
320}
321
322static unsigned long etb_reset_buffer(struct coresight_device *csdev,
323 struct perf_output_handle *handle,
324 void *sink_config, bool *lost)
325{
326 unsigned long size = 0;
327 struct cs_buffers *buf = sink_config;
328
329 if (buf) {
330 /*
331 * In snapshot mode ->data_size holds the new address of the
332 * ring buffer's head. The size itself is the whole address
333 * range since we want the latest information.
334 */
335 if (buf->snapshot)
336 handle->head = local_xchg(&buf->data_size,
337 buf->nr_pages << PAGE_SHIFT);
338
339 /*
340 * Tell the tracer PMU how much we got in this run and if
341 * something went wrong along the way. Nobody else can use
342 * this cs_buffers instance until we are done. As such
343 * resetting parameters here and squaring off with the ring
344 * buffer API in the tracer PMU is fine.
345 */
346 *lost = !!local_xchg(&buf->lost, 0);
347 size = local_xchg(&buf->data_size, 0);
348 }
349
350 return size;
351}
352
353static void etb_update_buffer(struct coresight_device *csdev,
354 struct perf_output_handle *handle,
355 void *sink_config)
356{
357 int i, cur;
358 u8 *buf_ptr;
359 u32 read_ptr, write_ptr, capacity;
360 u32 status, read_data, to_read;
361 unsigned long offset;
362 struct cs_buffers *buf = sink_config;
363 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
364
365 if (!buf)
366 return;
367
368 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
369
370 CS_UNLOCK(drvdata->base);
371 etb_disable_hw(drvdata);
372
373 /* unit is in words, not bytes */
374 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
375 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
376
377 /*
378 * Entries should be aligned to the frame size. If they are not
379 * go back to the last alignement point to give decoding tools a
380 * chance to fix things.
381 */
382 if (write_ptr % ETB_FRAME_SIZE_WORDS) {
383 dev_err(drvdata->dev,
384 "write_ptr: %lu not aligned to formatter frame size\n",
385 (unsigned long)write_ptr);
386
387 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
388 local_inc(&buf->lost);
389 }
390
391 /*
392 * Get a hold of the status register and see if a wrap around
393 * has occurred. If so adjust things accordingly. Otherwise
394 * start at the beginning and go until the write pointer has
395 * been reached.
396 */
397 status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
398 if (status & ETB_STATUS_RAM_FULL) {
399 local_inc(&buf->lost);
400 to_read = capacity;
401 read_ptr = write_ptr;
402 } else {
403 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
404 to_read *= ETB_FRAME_SIZE_WORDS;
405 }
406
407 /*
408 * Make sure we don't overwrite data that hasn't been consumed yet.
409 * It is entirely possible that the HW buffer has more data than the
410 * ring buffer can currently handle. If so adjust the start address
411 * to take only the last traces.
412 *
413 * In snapshot mode we are looking to get the latest traces only and as
414 * such, we don't care about not overwriting data that hasn't been
415 * processed by user space.
416 */
417 if (!buf->snapshot && to_read > handle->size) {
418 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
419
420 /* The new read pointer must be frame size aligned */
421 to_read = handle->size & mask;
422 /*
423 * Move the RAM read pointer up, keeping in mind that
424 * everything is in frame size units.
425 */
426 read_ptr = (write_ptr + drvdata->buffer_depth) -
427 to_read / ETB_FRAME_SIZE_WORDS;
428 /* Wrap around if need be*/
429 if (read_ptr > (drvdata->buffer_depth - 1))
430 read_ptr -= drvdata->buffer_depth;
431 /* let the decoder know we've skipped ahead */
432 local_inc(&buf->lost);
433 }
434
435 /* finally tell HW where we want to start reading from */
436 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
437
438 cur = buf->cur;
439 offset = buf->offset;
440 for (i = 0; i < to_read; i += 4) {
441 buf_ptr = buf->data_pages[cur] + offset;
442 read_data = readl_relaxed(drvdata->base +
443 ETB_RAM_READ_DATA_REG);
444 *buf_ptr++ = read_data >> 0;
445 *buf_ptr++ = read_data >> 8;
446 *buf_ptr++ = read_data >> 16;
447 *buf_ptr++ = read_data >> 24;
448
449 offset += 4;
450 if (offset >= PAGE_SIZE) {
451 offset = 0;
452 cur++;
453 /* wrap around at the end of the buffer */
454 cur &= buf->nr_pages - 1;
455 }
456 }
457
458 /* reset ETB buffer for next run */
459 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
460 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
461
462 /*
463 * In snapshot mode all we have to do is communicate to
464 * perf_aux_output_end() the address of the current head. In full
465 * trace mode the same function expects a size to move rb->aux_head
466 * forward.
467 */
468 if (buf->snapshot)
469 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
470 else
471 local_add(to_read, &buf->data_size);
472
473 etb_enable_hw(drvdata);
474 CS_LOCK(drvdata->base);
475}
476
477static const struct coresight_ops_sink etb_sink_ops = {
478 .enable = etb_enable,
479 .disable = etb_disable,
480 .alloc_buffer = etb_alloc_buffer,
481 .free_buffer = etb_free_buffer,
482 .set_buffer = etb_set_buffer,
483 .reset_buffer = etb_reset_buffer,
484 .update_buffer = etb_update_buffer,
485};
486
487static const struct coresight_ops etb_cs_ops = {
488 .sink_ops = &etb_sink_ops,
489};
490
491static void etb_dump(struct etb_drvdata *drvdata)
492{
493 unsigned long flags;
494
495 spin_lock_irqsave(&drvdata->spinlock, flags);
496 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
497 etb_disable_hw(drvdata);
498 etb_dump_hw(drvdata);
499 etb_enable_hw(drvdata);
500 }
501 spin_unlock_irqrestore(&drvdata->spinlock, flags);
502
503 dev_info(drvdata->dev, "ETB dumped\n");
504}
505
506static int etb_open(struct inode *inode, struct file *file)
507{
508 struct etb_drvdata *drvdata = container_of(file->private_data,
509 struct etb_drvdata, miscdev);
510
511 if (local_cmpxchg(&drvdata->reading, 0, 1))
512 return -EBUSY;
513
514 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
515 return 0;
516}
517
518static ssize_t etb_read(struct file *file, char __user *data,
519 size_t len, loff_t *ppos)
520{
521 u32 depth;
522 struct etb_drvdata *drvdata = container_of(file->private_data,
523 struct etb_drvdata, miscdev);
524
525 etb_dump(drvdata);
526
527 depth = drvdata->buffer_depth;
528 if (*ppos + len > depth * 4)
529 len = depth * 4 - *ppos;
530
531 if (copy_to_user(data, drvdata->buf + *ppos, len)) {
532 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
533 return -EFAULT;
534 }
535
536 *ppos += len;
537
538 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
539 __func__, len, (int)(depth * 4 - *ppos));
540 return len;
541}
542
543static int etb_release(struct inode *inode, struct file *file)
544{
545 struct etb_drvdata *drvdata = container_of(file->private_data,
546 struct etb_drvdata, miscdev);
547 local_set(&drvdata->reading, 0);
548
549 dev_dbg(drvdata->dev, "%s: released\n", __func__);
550 return 0;
551}
552
553static const struct file_operations etb_fops = {
554 .owner = THIS_MODULE,
555 .open = etb_open,
556 .read = etb_read,
557 .release = etb_release,
558 .llseek = no_llseek,
559};
560
561#define coresight_etb10_simple_func(name, offset) \
562 coresight_simple_func(struct etb_drvdata, NULL, name, offset)
563
564coresight_etb10_simple_func(rdp, ETB_RAM_DEPTH_REG);
565coresight_etb10_simple_func(sts, ETB_STATUS_REG);
566coresight_etb10_simple_func(rrp, ETB_RAM_READ_POINTER);
567coresight_etb10_simple_func(rwp, ETB_RAM_WRITE_POINTER);
568coresight_etb10_simple_func(trg, ETB_TRG);
569coresight_etb10_simple_func(ctl, ETB_CTL_REG);
570coresight_etb10_simple_func(ffsr, ETB_FFSR);
571coresight_etb10_simple_func(ffcr, ETB_FFCR);
572
573static struct attribute *coresight_etb_mgmt_attrs[] = {
574 &dev_attr_rdp.attr,
575 &dev_attr_sts.attr,
576 &dev_attr_rrp.attr,
577 &dev_attr_rwp.attr,
578 &dev_attr_trg.attr,
579 &dev_attr_ctl.attr,
580 &dev_attr_ffsr.attr,
581 &dev_attr_ffcr.attr,
582 NULL,
583};
584
585static ssize_t trigger_cntr_show(struct device *dev,
586 struct device_attribute *attr, char *buf)
587{
588 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
589 unsigned long val = drvdata->trigger_cntr;
590
591 return sprintf(buf, "%#lx\n", val);
592}
593
594static ssize_t trigger_cntr_store(struct device *dev,
595 struct device_attribute *attr,
596 const char *buf, size_t size)
597{
598 int ret;
599 unsigned long val;
600 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
601
602 ret = kstrtoul(buf, 16, &val);
603 if (ret)
604 return ret;
605
606 drvdata->trigger_cntr = val;
607 return size;
608}
609static DEVICE_ATTR_RW(trigger_cntr);
610
611static struct attribute *coresight_etb_attrs[] = {
612 &dev_attr_trigger_cntr.attr,
613 NULL,
614};
615
616static const struct attribute_group coresight_etb_group = {
617 .attrs = coresight_etb_attrs,
618};
619
620static const struct attribute_group coresight_etb_mgmt_group = {
621 .attrs = coresight_etb_mgmt_attrs,
622 .name = "mgmt",
623};
624
625const struct attribute_group *coresight_etb_groups[] = {
626 &coresight_etb_group,
627 &coresight_etb_mgmt_group,
628 NULL,
629};
630
631static int etb_probe(struct amba_device *adev, const struct amba_id *id)
632{
633 int ret;
634 void __iomem *base;
635 struct device *dev = &adev->dev;
636 struct coresight_platform_data *pdata = NULL;
637 struct etb_drvdata *drvdata;
638 struct resource *res = &adev->res;
639 struct coresight_desc desc = { 0 };
640 struct device_node *np = adev->dev.of_node;
641
642 if (np) {
643 pdata = of_get_coresight_platform_data(dev, np);
644 if (IS_ERR(pdata))
645 return PTR_ERR(pdata);
646 adev->dev.platform_data = pdata;
647 }
648
649 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
650 if (!drvdata)
651 return -ENOMEM;
652
653 drvdata->dev = &adev->dev;
654 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
655 if (!IS_ERR(drvdata->atclk)) {
656 ret = clk_prepare_enable(drvdata->atclk);
657 if (ret)
658 return ret;
659 }
660 dev_set_drvdata(dev, drvdata);
661
662 /* validity for the resource is already checked by the AMBA core */
663 base = devm_ioremap_resource(dev, res);
664 if (IS_ERR(base))
665 return PTR_ERR(base);
666
667 drvdata->base = base;
668
669 spin_lock_init(&drvdata->spinlock);
670
671 drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
672 pm_runtime_put(&adev->dev);
673
674 if (drvdata->buffer_depth & 0x80000000)
675 return -EINVAL;
676
677 drvdata->buf = devm_kzalloc(dev,
678 drvdata->buffer_depth * 4, GFP_KERNEL);
679 if (!drvdata->buf) {
680 dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
681 drvdata->buffer_depth * 4);
682 return -ENOMEM;
683 }
684
685 desc.type = CORESIGHT_DEV_TYPE_SINK;
686 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
687 desc.ops = &etb_cs_ops;
688 desc.pdata = pdata;
689 desc.dev = dev;
690 desc.groups = coresight_etb_groups;
691 drvdata->csdev = coresight_register(&desc);
692 if (IS_ERR(drvdata->csdev))
693 return PTR_ERR(drvdata->csdev);
694
695 drvdata->miscdev.name = pdata->name;
696 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
697 drvdata->miscdev.fops = &etb_fops;
698 ret = misc_register(&drvdata->miscdev);
699 if (ret)
700 goto err_misc_register;
701
702 return 0;
703
704err_misc_register:
705 coresight_unregister(drvdata->csdev);
706 return ret;
707}
708
709#ifdef CONFIG_PM
710static int etb_runtime_suspend(struct device *dev)
711{
712 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
713
714 if (drvdata && !IS_ERR(drvdata->atclk))
715 clk_disable_unprepare(drvdata->atclk);
716
717 return 0;
718}
719
720static int etb_runtime_resume(struct device *dev)
721{
722 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
723
724 if (drvdata && !IS_ERR(drvdata->atclk))
725 clk_prepare_enable(drvdata->atclk);
726
727 return 0;
728}
729#endif
730
731static const struct dev_pm_ops etb_dev_pm_ops = {
732 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
733};
734
735static struct amba_id etb_ids[] = {
736 {
737 .id = 0x0003b907,
738 .mask = 0x0003ffff,
739 },
740 { 0, 0},
741};
742
743static struct amba_driver etb_driver = {
744 .drv = {
745 .name = "coresight-etb10",
746 .owner = THIS_MODULE,
747 .pm = &etb_dev_pm_ops,
748 .suppress_bind_attrs = true,
749
750 },
751 .probe = etb_probe,
752 .id_table = etb_ids,
753};
754builtin_amba_driver(etb_driver);