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1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/clk.h>
8#include <linux/io.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12
13#include <drm/drmP.h>
14
15#include "sti_drv.h"
16
17/* registers offset */
18#define VTAC_CONFIG 0x00
19#define VTAC_RX_FIFO_CONFIG 0x04
20#define VTAC_FIFO_CONFIG_VAL 0x04
21
22#define VTAC_SYS_CFG8521 0x824
23#define VTAC_SYS_CFG8522 0x828
24
25/* Number of phyts per pixel */
26#define VTAC_2_5_PPP 0x0005
27#define VTAC_3_PPP 0x0006
28#define VTAC_4_PPP 0x0008
29#define VTAC_5_PPP 0x000A
30#define VTAC_6_PPP 0x000C
31#define VTAC_13_PPP 0x001A
32#define VTAC_14_PPP 0x001C
33#define VTAC_15_PPP 0x001E
34#define VTAC_16_PPP 0x0020
35#define VTAC_17_PPP 0x0022
36#define VTAC_18_PPP 0x0024
37
38/* enable bits */
39#define VTAC_ENABLE 0x3003
40
41#define VTAC_TX_PHY_ENABLE_CLK_PHY BIT(0)
42#define VTAC_TX_PHY_ENABLE_CLK_DLL BIT(1)
43#define VTAC_TX_PHY_PLL_NOT_OSC_MODE BIT(3)
44#define VTAC_TX_PHY_RST_N_DLL_SWITCH BIT(4)
45#define VTAC_TX_PHY_PROG_N3 BIT(9)
46
47
48/**
49 * VTAC mode structure
50 *
51 * @vid_in_width: Video Data Resolution
52 * @phyts_width: Width of phyt buses(phyt low and phyt high).
53 * @phyts_per_pixel: Number of phyts sent per pixel
54 */
55struct sti_vtac_mode {
56 u32 vid_in_width;
57 u32 phyts_width;
58 u32 phyts_per_pixel;
59};
60
61static const struct sti_vtac_mode vtac_mode_main = {
62 .vid_in_width = 0x2,
63 .phyts_width = 0x2,
64 .phyts_per_pixel = VTAC_5_PPP,
65};
66static const struct sti_vtac_mode vtac_mode_aux = {
67 .vid_in_width = 0x1,
68 .phyts_width = 0x0,
69 .phyts_per_pixel = VTAC_17_PPP,
70};
71
72/**
73 * VTAC structure
74 *
75 * @dev: pointer to device structure
76 * @regs: ioremapped registers for RX and TX devices
77 * @phy_regs: phy registers for TX device
78 * @clk: clock
79 * @mode: main or auxillary configuration mode
80 */
81struct sti_vtac {
82 struct device *dev;
83 void __iomem *regs;
84 void __iomem *phy_regs;
85 struct clk *clk;
86 const struct sti_vtac_mode *mode;
87};
88
89static void sti_vtac_rx_set_config(struct sti_vtac *vtac)
90{
91 u32 config;
92
93 /* Enable VTAC clock */
94 if (clk_prepare_enable(vtac->clk))
95 DRM_ERROR("Failed to prepare/enable vtac_rx clock.\n");
96
97 writel(VTAC_FIFO_CONFIG_VAL, vtac->regs + VTAC_RX_FIFO_CONFIG);
98
99 config = VTAC_ENABLE;
100 config |= vtac->mode->vid_in_width << 4;
101 config |= vtac->mode->phyts_width << 16;
102 config |= vtac->mode->phyts_per_pixel << 23;
103 writel(config, vtac->regs + VTAC_CONFIG);
104}
105
106static void sti_vtac_tx_set_config(struct sti_vtac *vtac)
107{
108 u32 phy_config;
109 u32 config;
110
111 /* Enable VTAC clock */
112 if (clk_prepare_enable(vtac->clk))
113 DRM_ERROR("Failed to prepare/enable vtac_tx clock.\n");
114
115 /* Configure vtac phy */
116 phy_config = 0x00000000;
117 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8522);
118 phy_config = VTAC_TX_PHY_ENABLE_CLK_PHY;
119 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
120 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
121 phy_config |= VTAC_TX_PHY_PROG_N3;
122 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
123 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
124 phy_config |= VTAC_TX_PHY_ENABLE_CLK_DLL;
125 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
126 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
127 phy_config |= VTAC_TX_PHY_RST_N_DLL_SWITCH;
128 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
129 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
130 phy_config |= VTAC_TX_PHY_PLL_NOT_OSC_MODE;
131 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
132
133 /* Configure vtac tx */
134 config = VTAC_ENABLE;
135 config |= vtac->mode->vid_in_width << 4;
136 config |= vtac->mode->phyts_width << 16;
137 config |= vtac->mode->phyts_per_pixel << 23;
138 writel(config, vtac->regs + VTAC_CONFIG);
139}
140
141static const struct of_device_id vtac_of_match[] = {
142 {
143 .compatible = "st,vtac-main",
144 .data = &vtac_mode_main,
145 }, {
146 .compatible = "st,vtac-aux",
147 .data = &vtac_mode_aux,
148 }, {
149 /* end node */
150 }
151};
152MODULE_DEVICE_TABLE(of, vtac_of_match);
153
154static int sti_vtac_probe(struct platform_device *pdev)
155{
156 struct device *dev = &pdev->dev;
157 struct device_node *np = dev->of_node;
158 const struct of_device_id *id;
159 struct sti_vtac *vtac;
160 struct resource *res;
161
162 vtac = devm_kzalloc(dev, sizeof(*vtac), GFP_KERNEL);
163 if (!vtac)
164 return -ENOMEM;
165
166 vtac->dev = dev;
167
168 id = of_match_node(vtac_of_match, np);
169 if (!id)
170 return -ENOMEM;
171
172 vtac->mode = id->data;
173
174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175 if (!res) {
176 DRM_ERROR("Invalid resource\n");
177 return -ENOMEM;
178 }
179 vtac->regs = devm_ioremap_resource(dev, res);
180 if (IS_ERR(vtac->regs))
181 return PTR_ERR(vtac->regs);
182
183
184 vtac->clk = devm_clk_get(dev, "vtac");
185 if (IS_ERR(vtac->clk)) {
186 DRM_ERROR("Cannot get vtac clock\n");
187 return PTR_ERR(vtac->clk);
188 }
189
190 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
191 if (res) {
192 vtac->phy_regs = devm_ioremap_nocache(dev, res->start,
193 resource_size(res));
194 sti_vtac_tx_set_config(vtac);
195 } else {
196
197 sti_vtac_rx_set_config(vtac);
198 }
199
200 platform_set_drvdata(pdev, vtac);
201 DRM_INFO("%s %s\n", __func__, dev_name(vtac->dev));
202
203 return 0;
204}
205
206static int sti_vtac_remove(struct platform_device *pdev)
207{
208 return 0;
209}
210
211struct platform_driver sti_vtac_driver = {
212 .driver = {
213 .name = "sti-vtac",
214 .owner = THIS_MODULE,
215 .of_match_table = vtac_of_match,
216 },
217 .probe = sti_vtac_probe,
218 .remove = sti_vtac_remove,
219};
220
221MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
222MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
223MODULE_LICENSE("GPL");