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1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_i2c.h"
29#include "nouveau_connector.h"
30#include "nouveau_encoder.h"
31
32static int
33auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
34{
35 struct drm_device *dev = encoder->dev;
36 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
37 struct nouveau_i2c_chan *auxch;
38 int ret;
39
40 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
41 if (!auxch)
42 return -ENODEV;
43
44 ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
45 if (ret)
46 return ret;
47
48 return 0;
49}
50
51static int
52auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
53{
54 struct drm_device *dev = encoder->dev;
55 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
56 struct nouveau_i2c_chan *auxch;
57 int ret;
58
59 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
60 if (!auxch)
61 return -ENODEV;
62
63 ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
64 return ret;
65}
66
67static int
68nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
69{
70 struct drm_device *dev = encoder->dev;
71 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
72 uint32_t tmp;
73 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
74
75 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
76 tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
77 NV50_SOR_DP_CTRL_LANE_MASK);
78 tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
79 if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
80 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
81 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
82
83 return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
84}
85
86static int
87nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
88{
89 struct drm_device *dev = encoder->dev;
90 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
91 uint32_t tmp;
92 int reg = 0x614300 + (nv_encoder->or * 0x800);
93
94 tmp = nv_rd32(dev, reg);
95 tmp &= 0xfff3ffff;
96 if (cmd == DP_LINK_BW_2_7)
97 tmp |= 0x00040000;
98 nv_wr32(dev, reg, tmp);
99
100 return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
101}
102
103static int
104nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
105{
106 struct drm_device *dev = encoder->dev;
107 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
108 uint32_t tmp;
109 uint8_t cmd;
110 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
111 int ret;
112
113 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
114 tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
115 tmp |= (pattern << 24);
116 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
117
118 ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
119 if (ret)
120 return ret;
121 cmd &= ~DP_TRAINING_PATTERN_MASK;
122 cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
123 return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
124}
125
126static int
127nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
128{
129 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
130 struct drm_device *dev = encoder->dev;
131 struct bit_displayport_encoder_table_entry *dpse;
132 struct bit_displayport_encoder_table *dpe;
133 int i, dpe_headerlen, max_vs = 0;
134
135 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
136 if (!dpe)
137 return false;
138 dpse = (void *)((char *)dpe + dpe_headerlen);
139
140 for (i = 0; i < dpe_headerlen; i++, dpse++) {
141 if (dpse->vs_level > max_vs)
142 max_vs = dpse->vs_level;
143 }
144
145 return max_vs;
146}
147
148static int
149nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
150{
151 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
152 struct drm_device *dev = encoder->dev;
153 struct bit_displayport_encoder_table_entry *dpse;
154 struct bit_displayport_encoder_table *dpe;
155 int i, dpe_headerlen, max_pre = 0;
156
157 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
158 if (!dpe)
159 return false;
160 dpse = (void *)((char *)dpe + dpe_headerlen);
161
162 for (i = 0; i < dpe_headerlen; i++, dpse++) {
163 if (dpse->vs_level != vs)
164 continue;
165
166 if (dpse->pre_level > max_pre)
167 max_pre = dpse->pre_level;
168 }
169
170 return max_pre;
171}
172
173static bool
174nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
175{
176 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
177 struct drm_device *dev = encoder->dev;
178 struct bit_displayport_encoder_table *dpe;
179 int ret, i, dpe_headerlen, vs = 0, pre = 0;
180 uint8_t request[2];
181
182 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
183 if (!dpe)
184 return false;
185
186 ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
187 if (ret)
188 return false;
189
190 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
191
192 /* Keep all lanes at the same level.. */
193 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
194 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
195 int lane_vs = lane_req & 3;
196 int lane_pre = (lane_req >> 2) & 3;
197
198 if (lane_vs > vs)
199 vs = lane_vs;
200 if (lane_pre > pre)
201 pre = lane_pre;
202 }
203
204 if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
205 vs = nouveau_dp_max_voltage_swing(encoder);
206 vs |= 4;
207 }
208
209 if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
210 pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
211 pre |= 4;
212 }
213
214 /* Update the configuration for all lanes.. */
215 for (i = 0; i < nv_encoder->dp.link_nr; i++)
216 config[i] = (pre << 3) | vs;
217
218 return true;
219}
220
221static bool
222nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
223{
224 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
225 struct drm_device *dev = encoder->dev;
226 struct bit_displayport_encoder_table_entry *dpse;
227 struct bit_displayport_encoder_table *dpe;
228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
229 int dpe_headerlen, ret, i;
230
231 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
232 config[0], config[1], config[2], config[3]);
233
234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
235 if (!dpe)
236 return false;
237 dpse = (void *)((char *)dpe + dpe_headerlen);
238
239 for (i = 0; i < dpe->record_nr; i++, dpse++) {
240 if (dpse->vs_level == (config[0] & 3) &&
241 dpse->pre_level == ((config[0] >> 3) & 3))
242 break;
243 }
244 BUG_ON(i == dpe->record_nr);
245
246 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
247 const int shift[4] = { 16, 8, 0, 24 };
248 uint32_t mask = 0xff << shift[i];
249 uint32_t reg0, reg1, reg2;
250
251 reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
252 reg0 |= (dpse->reg0 << shift[i]);
253 reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
254 reg1 |= (dpse->reg1 << shift[i]);
255 reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
256 reg2 |= (dpse->reg2 << 8);
257 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
258 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
259 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
260 }
261
262 ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
263 if (ret)
264 return false;
265
266 return true;
267}
268
269bool
270nouveau_dp_link_train(struct drm_encoder *encoder)
271{
272 struct drm_device *dev = encoder->dev;
273 struct drm_nouveau_private *dev_priv = dev->dev_private;
274 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
275 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
276 struct nouveau_connector *nv_connector;
277 struct bit_displayport_encoder_table *dpe;
278 int dpe_headerlen;
279 uint8_t config[4], status[3];
280 bool cr_done, cr_max_vs, eq_done, hpd_state;
281 int ret = 0, i, tries, voltage;
282
283 NV_DEBUG_KMS(dev, "link training!!\n");
284
285 nv_connector = nouveau_encoder_connector_get(nv_encoder);
286 if (!nv_connector)
287 return false;
288
289 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
290 if (!dpe) {
291 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
292 return false;
293 }
294
295 /* disable hotplug detect, this flips around on some panels during
296 * link training.
297 */
298 hpd_state = pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
299
300 if (dpe->script0) {
301 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
302 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
303 nv_encoder->dcb);
304 }
305
306train:
307 cr_done = eq_done = false;
308
309 /* set link configuration */
310 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
311 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
312
313 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
314 if (ret)
315 return false;
316
317 config[0] = nv_encoder->dp.link_nr;
318 if (nv_encoder->dp.dpcd_version >= 0x11 &&
319 nv_encoder->dp.enhanced_frame)
320 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
321
322 ret = nouveau_dp_lane_count_set(encoder, config[0]);
323 if (ret)
324 return false;
325
326 /* clock recovery */
327 NV_DEBUG_KMS(dev, "\tbegin cr\n");
328 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
329 if (ret)
330 goto stop;
331
332 tries = 0;
333 voltage = -1;
334 memset(config, 0x00, sizeof(config));
335 for (;;) {
336 if (!nouveau_dp_link_train_commit(encoder, config))
337 break;
338
339 udelay(100);
340
341 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
342 if (ret)
343 break;
344 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
345 status[0], status[1]);
346
347 cr_done = true;
348 cr_max_vs = false;
349 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
350 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
351
352 if (!(lane & DP_LANE_CR_DONE)) {
353 cr_done = false;
354 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
355 cr_max_vs = true;
356 break;
357 }
358 }
359
360 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
361 voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
362 tries = 0;
363 }
364
365 if (cr_done || cr_max_vs || (++tries == 5))
366 break;
367
368 if (!nouveau_dp_link_train_adjust(encoder, config))
369 break;
370 }
371
372 if (!cr_done)
373 goto stop;
374
375 /* channel equalisation */
376 NV_DEBUG_KMS(dev, "\tbegin eq\n");
377 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
378 if (ret)
379 goto stop;
380
381 for (tries = 0; tries <= 5; tries++) {
382 udelay(400);
383
384 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
385 if (ret)
386 break;
387 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
388 status[0], status[1]);
389
390 eq_done = true;
391 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
392 eq_done = false;
393
394 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
395 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
396
397 if (!(lane & DP_LANE_CR_DONE)) {
398 cr_done = false;
399 break;
400 }
401
402 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
403 !(lane & DP_LANE_SYMBOL_LOCKED)) {
404 eq_done = false;
405 break;
406 }
407 }
408
409 if (eq_done || !cr_done)
410 break;
411
412 if (!nouveau_dp_link_train_adjust(encoder, config) ||
413 !nouveau_dp_link_train_commit(encoder, config))
414 break;
415 }
416
417stop:
418 /* end link training */
419 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
420 if (ret)
421 return false;
422
423 /* retry at a lower setting, if possible */
424 if (!ret && !(eq_done && cr_done)) {
425 NV_DEBUG_KMS(dev, "\twe failed\n");
426 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
427 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
428 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
429 goto train;
430 }
431 }
432
433 if (dpe->script1) {
434 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
435 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
436 nv_encoder->dcb);
437 }
438
439 /* re-enable hotplug detect */
440 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, hpd_state);
441
442 return eq_done;
443}
444
445bool
446nouveau_dp_detect(struct drm_encoder *encoder)
447{
448 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
449 struct drm_device *dev = encoder->dev;
450 uint8_t dpcd[4];
451 int ret;
452
453 ret = auxch_rd(encoder, 0x0000, dpcd, 4);
454 if (ret)
455 return false;
456
457 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
458 "display: link_bw %d, link_nr %d version 0x%02x\n",
459 nv_encoder->dcb->dpconf.link_bw,
460 nv_encoder->dcb->dpconf.link_nr,
461 dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
462
463 nv_encoder->dp.dpcd_version = dpcd[0];
464
465 nv_encoder->dp.link_bw = dpcd[1];
466 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
467 !nv_encoder->dcb->dpconf.link_bw)
468 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
469
470 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
471 if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
472 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
473
474 nv_encoder->dp.enhanced_frame = (dpcd[2] & DP_ENHANCED_FRAME_CAP);
475
476 return true;
477}
478
479int
480nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
481 uint8_t *data, int data_nr)
482{
483 struct drm_device *dev = auxch->dev;
484 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
485 int ret = 0, i, index = auxch->rd;
486
487 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
488
489 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
490 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
491 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
492 if (!(tmp & 0x01000000)) {
493 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
494 ret = -EIO;
495 goto out;
496 }
497
498 for (i = 0; i < 3; i++) {
499 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
500 if (tmp & NV50_AUXCH_STAT_STATE_READY)
501 break;
502 udelay(100);
503 }
504
505 if (i == 3) {
506 ret = -EBUSY;
507 goto out;
508 }
509
510 if (!(cmd & 1)) {
511 memcpy(data32, data, data_nr);
512 for (i = 0; i < 4; i++) {
513 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
514 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
515 }
516 }
517
518 nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
519 ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
520 ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
521 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
522 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
523
524 for (i = 0; i < 16; i++) {
525 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
526 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
527 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
528 if (!nv_wait(dev, NV50_AUXCH_CTRL(index),
529 0x00010000, 0x00000000)) {
530 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
531 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
532 ret = -EBUSY;
533 goto out;
534 }
535
536 udelay(400);
537
538 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
539 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
540 NV50_AUXCH_STAT_REPLY_AUX_DEFER)
541 break;
542 }
543
544 if (i == 16) {
545 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
546 ret = -EREMOTEIO;
547 goto out;
548 }
549
550 if (cmd & 1) {
551 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
552 ret = -EREMOTEIO;
553 goto out;
554 }
555
556 for (i = 0; i < 4; i++) {
557 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
558 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
559 }
560 memcpy(data, data32, data_nr);
561 }
562
563out:
564 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
565 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
566 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
567 if (tmp & 0x01000000) {
568 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
569 ret = -EIO;
570 }
571
572 udelay(400);
573
574 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
575}
576
577static int
578nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
579{
580 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
581 struct drm_device *dev = auxch->dev;
582 struct i2c_msg *msg = msgs;
583 int ret, mcnt = num;
584
585 while (mcnt--) {
586 u8 remaining = msg->len;
587 u8 *ptr = msg->buf;
588
589 while (remaining) {
590 u8 cnt = (remaining > 16) ? 16 : remaining;
591 u8 cmd;
592
593 if (msg->flags & I2C_M_RD)
594 cmd = AUX_I2C_READ;
595 else
596 cmd = AUX_I2C_WRITE;
597
598 if (mcnt || remaining > 16)
599 cmd |= AUX_I2C_MOT;
600
601 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
602 if (ret < 0)
603 return ret;
604
605 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
606 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
607 break;
608 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
609 return -EREMOTEIO;
610 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
611 udelay(100);
612 continue;
613 default:
614 NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret);
615 return -EREMOTEIO;
616 }
617
618 ptr += cnt;
619 remaining -= cnt;
620 }
621
622 msg++;
623 }
624
625 return num;
626}
627
628static u32
629nouveau_dp_i2c_func(struct i2c_adapter *adap)
630{
631 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
632}
633
634const struct i2c_algorithm nouveau_dp_i2c_algo = {
635 .master_xfer = nouveau_dp_i2c_xfer,
636 .functionality = nouveau_dp_i2c_func
637};
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <drm/drmP.h>
26#include <drm/drm_dp_helper.h>
27
28#include "nouveau_drv.h"
29#include "nouveau_connector.h"
30#include "nouveau_encoder.h"
31#include "nouveau_crtc.h"
32
33#include <nvif/class.h>
34#include <nvif/cl5070.h>
35
36MODULE_PARM_DESC(mst, "Enable DisplayPort multi-stream (default: enabled)");
37static int nouveau_mst = 1;
38module_param_named(mst, nouveau_mst, int, 0400);
39
40static void
41nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd)
42{
43 struct nouveau_drm *drm = nouveau_drm(dev);
44 u8 buf[3];
45
46 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
47 return;
48
49 if (!nvkm_rdaux(aux, DP_SINK_OUI, buf, 3))
50 NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
51 buf[0], buf[1], buf[2]);
52
53 if (!nvkm_rdaux(aux, DP_BRANCH_OUI, buf, 3))
54 NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
55 buf[0], buf[1], buf[2]);
56
57}
58
59int
60nouveau_dp_detect(struct nouveau_encoder *nv_encoder)
61{
62 struct drm_device *dev = nv_encoder->base.base.dev;
63 struct nouveau_drm *drm = nouveau_drm(dev);
64 struct nvkm_i2c_aux *aux;
65 u8 dpcd[8];
66 int ret;
67
68 aux = nv_encoder->aux;
69 if (!aux)
70 return -ENODEV;
71
72 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
73 if (ret)
74 return ret;
75
76 nv_encoder->dp.link_bw = 27000 * dpcd[1];
77 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
78
79 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
80 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
81 NV_DEBUG(drm, "encoder: %dx%d\n",
82 nv_encoder->dcb->dpconf.link_nr,
83 nv_encoder->dcb->dpconf.link_bw);
84
85 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
86 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
87 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
88 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
89
90 NV_DEBUG(drm, "maximum: %dx%d\n",
91 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
92
93 nouveau_dp_probe_oui(dev, aux, dpcd);
94
95 ret = nv50_mstm_detect(nv_encoder->dp.mstm, dpcd, nouveau_mst);
96 if (ret == 1)
97 return NOUVEAU_DP_MST;
98 if (ret == 0)
99 return NOUVEAU_DP_SST;
100 return ret;
101}