1/*
  2 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
  3 *
  4 * This code is based on drivers/video/fbdev/mxsfb.c :
  5 * Copyright (C) 2010 Juergen Beisert, Pengutronix
  6 * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  7 * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  8 *
  9 * This program is free software; you can redistribute it and/or
 10 * modify it under the terms of the GNU General Public License
 11 * as published by the Free Software Foundation; either version 2
 12 * of the License, or (at your option) any later version.
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 */
 18
 19#include <drm/drmP.h>
 20#include <drm/drm_atomic_helper.h>
 21#include <drm/drm_crtc.h>
 22#include <drm/drm_crtc_helper.h>
 23#include <drm/drm_fb_helper.h>
 24#include <drm/drm_fb_cma_helper.h>
 25#include <drm/drm_gem_cma_helper.h>
 26#include <drm/drm_of.h>
 27#include <drm/drm_plane_helper.h>
 28#include <drm/drm_simple_kms_helper.h>
 29#include <linux/clk.h>
 30#include <linux/iopoll.h>
 31#include <linux/of_graph.h>
 32#include <linux/platform_data/simplefb.h>
 33#include <video/videomode.h>
 34
 35#include "mxsfb_drv.h"
 36#include "mxsfb_regs.h"
 37
 38static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
 39{
 40	return (val & mxsfb->devdata->hs_wdth_mask) <<
 41		mxsfb->devdata->hs_wdth_shift;
 42}
 43
 44/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
 45static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
 46{
 47	struct drm_crtc *crtc = &mxsfb->pipe.crtc;
 48	struct drm_device *drm = crtc->dev;
 49	const u32 format = crtc->primary->state->fb->pixel_format;
 50	u32 ctrl, ctrl1;
 51
 52	ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
 53
 54	/*
 55	 * WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
 56	 * match the selected mode here. This differs from the original
 57	 * MXSFB driver, which had the option to configure the bus width
 58	 * to arbitrary value. This limitation should not pose an issue.
 59	 */
 60
 61	/* CTRL1 contains IRQ config and status bits, preserve those. */
 62	ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
 63	ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
 64
 65	switch (format) {
 66	case DRM_FORMAT_RGB565:
 67		dev_dbg(drm->dev, "Setting up RGB565 mode\n");
 68		ctrl |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
 69		ctrl |= CTRL_SET_WORD_LENGTH(0);
 70		ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
 71		break;
 72	case DRM_FORMAT_XRGB8888:
 73		dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
 74		ctrl |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
 75		ctrl |= CTRL_SET_WORD_LENGTH(3);
 76		/* Do not use packed pixels = one pixel per word instead. */
 77		ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
 78		break;
 79	default:
 80		dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
 81		return -EINVAL;
 82	}
 83
 84	writel(ctrl1, mxsfb->base + LCDC_CTRL1);
 85	writel(ctrl, mxsfb->base + LCDC_CTRL);
 86
 87	return 0;
 88}
 89
 90static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
 91{
 92	u32 reg;
 93
 94	if (mxsfb->clk_disp_axi)
 95		clk_prepare_enable(mxsfb->clk_disp_axi);
 96	clk_prepare_enable(mxsfb->clk);
 97	mxsfb_enable_axi_clk(mxsfb);
 98
 99	/* If it was disabled, re-enable the mode again */
100	writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
101
102	/* Enable the SYNC signals first, then the DMA engine */
103	reg = readl(mxsfb->base + LCDC_VDCTRL4);
104	reg |= VDCTRL4_SYNC_SIGNALS_ON;
105	writel(reg, mxsfb->base + LCDC_VDCTRL4);
106
107	writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
108}
109
110static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
111{
112	u32 reg;
113
114	/*
115	 * Even if we disable the controller here, it will still continue
116	 * until its FIFOs are running out of data
117	 */
118	writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
119
120	readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
121			   0, 1000);
122
123	reg = readl(mxsfb->base + LCDC_VDCTRL4);
124	reg &= ~VDCTRL4_SYNC_SIGNALS_ON;
125	writel(reg, mxsfb->base + LCDC_VDCTRL4);
126
127	mxsfb_disable_axi_clk(mxsfb);
128
129	clk_disable_unprepare(mxsfb->clk);
130	if (mxsfb->clk_disp_axi)
131		clk_disable_unprepare(mxsfb->clk_disp_axi);
132}
133
134static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
135{
136	struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
137	const u32 bus_flags = mxsfb->connector.display_info.bus_flags;
138	u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
139	int err;
140
141	/*
142	 * It seems, you can't re-program the controller if it is still
143	 * running. This may lead to shifted pictures (FIFO issue?), so
144	 * first stop the controller and drain its FIFOs.
145	 */
146	mxsfb_enable_axi_clk(mxsfb);
147
148	/* Clear the FIFOs */
149	writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
150
151	err = mxsfb_set_pixel_fmt(mxsfb);
152	if (err)
153		return;
154
155	clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
156
157	writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
158	       TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay),
159	       mxsfb->base + mxsfb->devdata->transfer_count);
160
161	vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start;
162
163	vdctrl0 = VDCTRL0_ENABLE_PRESENT |	/* Always in DOTCLOCK mode */
164		  VDCTRL0_VSYNC_PERIOD_UNIT |
165		  VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
166		  VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len);
167	if (m->flags & DRM_MODE_FLAG_PHSYNC)
168		vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
169	if (m->flags & DRM_MODE_FLAG_PVSYNC)
170		vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
171	if (bus_flags & DRM_BUS_FLAG_DE_HIGH)
172		vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
173	if (bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
174		vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
175
176	writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
177
178	/* Frame length in lines. */
179	writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
180
181	/* Line length in units of clocks or pixels. */
182	hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start;
183	writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
184	       VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal),
185	       mxsfb->base + LCDC_VDCTRL2);
186
187	writel(SET_HOR_WAIT_CNT(m->crtc_hblank_end - m->crtc_hsync_end) |
188	       SET_VERT_WAIT_CNT(m->crtc_vblank_end - m->crtc_vsync_end),
189	       mxsfb->base + LCDC_VDCTRL3);
190
191	writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
192	       mxsfb->base + LCDC_VDCTRL4);
193
194	mxsfb_disable_axi_clk(mxsfb);
195}
196
197void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
198{
199	mxsfb_crtc_mode_set_nofb(mxsfb);
200	mxsfb_enable_controller(mxsfb);
201}
202
203void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
204{
205	mxsfb_disable_controller(mxsfb);
206}
207
208void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
209			       struct drm_plane_state *state)
210{
211	struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
212	struct drm_crtc *crtc = &pipe->crtc;
213	struct drm_framebuffer *fb = pipe->plane.state->fb;
214	struct drm_pending_vblank_event *event;
215	struct drm_gem_cma_object *gem;
216
217	if (!crtc)
218		return;
219
220	spin_lock_irq(&crtc->dev->event_lock);
221	event = crtc->state->event;
222	if (event) {
223		crtc->state->event = NULL;
224
225		if (drm_crtc_vblank_get(crtc) == 0) {
226			drm_crtc_arm_vblank_event(crtc, event);
227		} else {
228			drm_crtc_send_vblank_event(crtc, event);
229		}
230	}
231	spin_unlock_irq(&crtc->dev->event_lock);
232
233	if (!fb)
234		return;
235
236	gem = drm_fb_cma_get_gem_obj(fb, 0);
237
238	mxsfb_enable_axi_clk(mxsfb);
239	writel(gem->paddr, mxsfb->base + mxsfb->devdata->next_buf);
240	mxsfb_disable_axi_clk(mxsfb);
241}