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1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/phy/phy.h>
21
22#define MIPITX_DSI_CON 0x00
23#define RG_DSI_LDOCORE_EN BIT(0)
24#define RG_DSI_CKG_LDOOUT_EN BIT(1)
25#define RG_DSI_BCLK_SEL (3 << 2)
26#define RG_DSI_LD_IDX_SEL (7 << 4)
27#define RG_DSI_PHYCLK_SEL (2 << 8)
28#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
29#define RG_DSI_LPTX_CLMP_EN BIT(11)
30
31#define MIPITX_DSI_CLOCK_LANE 0x04
32#define MIPITX_DSI_DATA_LANE0 0x08
33#define MIPITX_DSI_DATA_LANE1 0x0c
34#define MIPITX_DSI_DATA_LANE2 0x10
35#define MIPITX_DSI_DATA_LANE3 0x14
36#define RG_DSI_LNTx_LDOOUT_EN BIT(0)
37#define RG_DSI_LNTx_CKLANE_EN BIT(1)
38#define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
39#define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
40#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
41#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
42#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
43#define RG_DSI_LNTx_RT_CODE (0xf << 8)
44
45#define MIPITX_DSI_TOP_CON 0x40
46#define RG_DSI_LNT_INTR_EN BIT(0)
47#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
48#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
49#define RG_DSI_LNT_TESTMODE_EN BIT(3)
50#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
51#define RG_DSI_LNT_AIO_SEL (7 << 8)
52#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
53#define RG_DSI_DEBUG_INPUT_EN BIT(12)
54#define RG_DSI_PRESERVE (7 << 13)
55
56#define MIPITX_DSI_BG_CON 0x44
57#define RG_DSI_BG_CORE_EN BIT(0)
58#define RG_DSI_BG_CKEN BIT(1)
59#define RG_DSI_BG_DIV (0x3 << 2)
60#define RG_DSI_BG_FAST_CHARGE BIT(4)
61#define RG_DSI_VOUT_MSK (0x3ffff << 5)
62#define RG_DSI_V12_SEL (7 << 5)
63#define RG_DSI_V10_SEL (7 << 8)
64#define RG_DSI_V072_SEL (7 << 11)
65#define RG_DSI_V04_SEL (7 << 14)
66#define RG_DSI_V032_SEL (7 << 17)
67#define RG_DSI_V02_SEL (7 << 20)
68#define RG_DSI_BG_R1_TRIM (0xf << 24)
69#define RG_DSI_BG_R2_TRIM (0xf << 28)
70
71#define MIPITX_DSI_PLL_CON0 0x50
72#define RG_DSI_MPPLL_PLL_EN BIT(0)
73#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
74#define RG_DSI_MPPLL_PREDIV (3 << 1)
75#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
76#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
77#define RG_DSI_MPPLL_POSDIV (7 << 7)
78#define RG_DSI_MPPLL_MONVC_EN BIT(10)
79#define RG_DSI_MPPLL_MONREF_EN BIT(11)
80#define RG_DSI_MPPLL_VOD_EN BIT(12)
81
82#define MIPITX_DSI_PLL_CON1 0x54
83#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
84#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
85#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
86#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
87
88#define MIPITX_DSI_PLL_CON2 0x58
89
90#define MIPITX_DSI_PLL_PWR 0x68
91#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
92#define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
93#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
94
95#define MIPITX_DSI_SW_CTRL 0x80
96#define SW_CTRL_EN BIT(0)
97
98#define MIPITX_DSI_SW_CTRL_CON0 0x84
99#define SW_LNTC_LPTX_PRE_OE BIT(0)
100#define SW_LNTC_LPTX_OE BIT(1)
101#define SW_LNTC_LPTX_P BIT(2)
102#define SW_LNTC_LPTX_N BIT(3)
103#define SW_LNTC_HSTX_PRE_OE BIT(4)
104#define SW_LNTC_HSTX_OE BIT(5)
105#define SW_LNTC_HSTX_ZEROCLK BIT(6)
106#define SW_LNT0_LPTX_PRE_OE BIT(7)
107#define SW_LNT0_LPTX_OE BIT(8)
108#define SW_LNT0_LPTX_P BIT(9)
109#define SW_LNT0_LPTX_N BIT(10)
110#define SW_LNT0_HSTX_PRE_OE BIT(11)
111#define SW_LNT0_HSTX_OE BIT(12)
112#define SW_LNT0_LPRX_EN BIT(13)
113#define SW_LNT1_LPTX_PRE_OE BIT(14)
114#define SW_LNT1_LPTX_OE BIT(15)
115#define SW_LNT1_LPTX_P BIT(16)
116#define SW_LNT1_LPTX_N BIT(17)
117#define SW_LNT1_HSTX_PRE_OE BIT(18)
118#define SW_LNT1_HSTX_OE BIT(19)
119#define SW_LNT2_LPTX_PRE_OE BIT(20)
120#define SW_LNT2_LPTX_OE BIT(21)
121#define SW_LNT2_LPTX_P BIT(22)
122#define SW_LNT2_LPTX_N BIT(23)
123#define SW_LNT2_HSTX_PRE_OE BIT(24)
124#define SW_LNT2_HSTX_OE BIT(25)
125
126struct mtk_mipi_tx {
127 struct device *dev;
128 void __iomem *regs;
129 unsigned int data_rate;
130 struct clk_hw pll_hw;
131 struct clk *pll;
132};
133
134static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
135{
136 return container_of(hw, struct mtk_mipi_tx, pll_hw);
137}
138
139static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
140 u32 bits)
141{
142 u32 temp = readl(mipi_tx->regs + offset);
143
144 writel(temp & ~bits, mipi_tx->regs + offset);
145}
146
147static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
148 u32 bits)
149{
150 u32 temp = readl(mipi_tx->regs + offset);
151
152 writel(temp | bits, mipi_tx->regs + offset);
153}
154
155static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
156 u32 mask, u32 data)
157{
158 u32 temp = readl(mipi_tx->regs + offset);
159
160 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
161}
162
163static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
164{
165 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
166 unsigned int txdiv, txdiv0, txdiv1;
167 u64 pcw;
168
169 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
170
171 if (mipi_tx->data_rate >= 500000000) {
172 txdiv = 1;
173 txdiv0 = 0;
174 txdiv1 = 0;
175 } else if (mipi_tx->data_rate >= 250000000) {
176 txdiv = 2;
177 txdiv0 = 1;
178 txdiv1 = 0;
179 } else if (mipi_tx->data_rate >= 125000000) {
180 txdiv = 4;
181 txdiv0 = 2;
182 txdiv1 = 0;
183 } else if (mipi_tx->data_rate > 62000000) {
184 txdiv = 8;
185 txdiv0 = 2;
186 txdiv1 = 1;
187 } else if (mipi_tx->data_rate >= 50000000) {
188 txdiv = 16;
189 txdiv0 = 2;
190 txdiv1 = 2;
191 } else {
192 return -EINVAL;
193 }
194
195 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
196 RG_DSI_VOUT_MSK |
197 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
198 (4 << 20) | (4 << 17) | (4 << 14) |
199 (4 << 11) | (4 << 8) | (4 << 5) |
200 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
201
202 usleep_range(30, 100);
203
204 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
205 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
206 (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
207
208 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
209 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
210
211 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
212 RG_DSI_MPPLL_SDM_PWR_ON |
213 RG_DSI_MPPLL_SDM_ISO_EN,
214 RG_DSI_MPPLL_SDM_PWR_ON);
215
216 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
217 RG_DSI_MPPLL_PLL_EN);
218
219 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
220 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
221 RG_DSI_MPPLL_PREDIV,
222 (txdiv0 << 3) | (txdiv1 << 5));
223
224 /*
225 * PLL PCW config
226 * PCW bit 24~30 = integer part of pcw
227 * PCW bit 0~23 = fractional part of pcw
228 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
229 * Post DIV =4, so need data_Rate*4
230 * Ref_clk is 26MHz
231 */
232 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
233 26000000);
234 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
235
236 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
237 RG_DSI_MPPLL_SDM_FRA_EN);
238
239 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
240
241 usleep_range(20, 100);
242
243 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
244 RG_DSI_MPPLL_SDM_SSC_EN);
245
246 return 0;
247}
248
249static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
250{
251 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
252
253 dev_dbg(mipi_tx->dev, "unprepare\n");
254
255 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
256 RG_DSI_MPPLL_PLL_EN);
257
258 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
259 RG_DSI_MPPLL_SDM_ISO_EN |
260 RG_DSI_MPPLL_SDM_PWR_ON,
261 RG_DSI_MPPLL_SDM_ISO_EN);
262
263 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
264 RG_DSI_LNT_HS_BIAS_EN);
265
266 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
267 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
268
269 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
270 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
271
272 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
273 RG_DSI_MPPLL_DIV_MSK);
274}
275
276static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
277 unsigned long *prate)
278{
279 return clamp_val(rate, 50000000, 1250000000);
280}
281
282static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
283 unsigned long parent_rate)
284{
285 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
286
287 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
288
289 mipi_tx->data_rate = rate;
290
291 return 0;
292}
293
294static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
295 unsigned long parent_rate)
296{
297 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
298
299 return mipi_tx->data_rate;
300}
301
302static const struct clk_ops mtk_mipi_tx_pll_ops = {
303 .prepare = mtk_mipi_tx_pll_prepare,
304 .unprepare = mtk_mipi_tx_pll_unprepare,
305 .round_rate = mtk_mipi_tx_pll_round_rate,
306 .set_rate = mtk_mipi_tx_pll_set_rate,
307 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
308};
309
310static int mtk_mipi_tx_power_on_signal(struct phy *phy)
311{
312 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
313 unsigned int reg;
314
315 for (reg = MIPITX_DSI_CLOCK_LANE;
316 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
317 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
318
319 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
320 RG_DSI_PAD_TIE_LOW_EN);
321
322 return 0;
323}
324
325static int mtk_mipi_tx_power_on(struct phy *phy)
326{
327 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
328 int ret;
329
330 /* Power up core and enable PLL */
331 ret = clk_prepare_enable(mipi_tx->pll);
332 if (ret < 0)
333 return ret;
334
335 /* Enable DSI Lane LDO outputs, disable pad tie low */
336 mtk_mipi_tx_power_on_signal(phy);
337
338 return 0;
339}
340
341static void mtk_mipi_tx_power_off_signal(struct phy *phy)
342{
343 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
344 unsigned int reg;
345
346 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
347 RG_DSI_PAD_TIE_LOW_EN);
348
349 for (reg = MIPITX_DSI_CLOCK_LANE;
350 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
351 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
352}
353
354static int mtk_mipi_tx_power_off(struct phy *phy)
355{
356 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
357
358 /* Enable pad tie low, disable DSI Lane LDO outputs */
359 mtk_mipi_tx_power_off_signal(phy);
360
361 /* Disable PLL and power down core */
362 clk_disable_unprepare(mipi_tx->pll);
363
364 return 0;
365}
366
367static const struct phy_ops mtk_mipi_tx_ops = {
368 .power_on = mtk_mipi_tx_power_on,
369 .power_off = mtk_mipi_tx_power_off,
370 .owner = THIS_MODULE,
371};
372
373static int mtk_mipi_tx_probe(struct platform_device *pdev)
374{
375 struct device *dev = &pdev->dev;
376 struct mtk_mipi_tx *mipi_tx;
377 struct resource *mem;
378 struct clk *ref_clk;
379 const char *ref_clk_name;
380 struct clk_init_data clk_init = {
381 .ops = &mtk_mipi_tx_pll_ops,
382 .num_parents = 1,
383 .parent_names = (const char * const *)&ref_clk_name,
384 .flags = CLK_SET_RATE_GATE,
385 };
386 struct phy *phy;
387 struct phy_provider *phy_provider;
388 int ret;
389
390 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
391 if (!mipi_tx)
392 return -ENOMEM;
393
394 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
395 mipi_tx->regs = devm_ioremap_resource(dev, mem);
396 if (IS_ERR(mipi_tx->regs)) {
397 ret = PTR_ERR(mipi_tx->regs);
398 dev_err(dev, "Failed to get memory resource: %d\n", ret);
399 return ret;
400 }
401
402 ref_clk = devm_clk_get(dev, NULL);
403 if (IS_ERR(ref_clk)) {
404 ret = PTR_ERR(ref_clk);
405 dev_err(dev, "Failed to get reference clock: %d\n", ret);
406 return ret;
407 }
408 ref_clk_name = __clk_get_name(ref_clk);
409
410 ret = of_property_read_string(dev->of_node, "clock-output-names",
411 &clk_init.name);
412 if (ret < 0) {
413 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
414 return ret;
415 }
416
417 mipi_tx->pll_hw.init = &clk_init;
418 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
419 if (IS_ERR(mipi_tx->pll)) {
420 ret = PTR_ERR(mipi_tx->pll);
421 dev_err(dev, "Failed to register PLL: %d\n", ret);
422 return ret;
423 }
424
425 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
426 if (IS_ERR(phy)) {
427 ret = PTR_ERR(phy);
428 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
429 return ret;
430 }
431 phy_set_drvdata(phy, mipi_tx);
432
433 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
434 if (IS_ERR(phy_provider)) {
435 ret = PTR_ERR(phy_provider);
436 return ret;
437 }
438
439 mipi_tx->dev = dev;
440
441 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
442 mipi_tx->pll);
443}
444
445static int mtk_mipi_tx_remove(struct platform_device *pdev)
446{
447 of_clk_del_provider(pdev->dev.of_node);
448 return 0;
449}
450
451static const struct of_device_id mtk_mipi_tx_match[] = {
452 { .compatible = "mediatek,mt8173-mipi-tx", },
453 {},
454};
455
456struct platform_driver mtk_mipi_tx_driver = {
457 .probe = mtk_mipi_tx_probe,
458 .remove = mtk_mipi_tx_remove,
459 .driver = {
460 .name = "mediatek-mipi-tx",
461 .of_match_table = mtk_mipi_tx_match,
462 },
463};