1/*
  2 * Copyright © 2016 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include "i915_drv.h"
 26#include "intel_ringbuffer.h"
 27#include "intel_lrc.h"
 28
 29static const struct engine_info {
 30	const char *name;
 31	unsigned exec_id;
 32	enum intel_engine_hw_id hw_id;
 33	u32 mmio_base;
 34	unsigned irq_shift;
 35	int (*init_legacy)(struct intel_engine_cs *engine);
 36	int (*init_execlists)(struct intel_engine_cs *engine);
 37} intel_engines[] = {
 38	[RCS] = {
 39		.name = "render ring",
 40		.exec_id = I915_EXEC_RENDER,
 41		.hw_id = RCS_HW,
 42		.mmio_base = RENDER_RING_BASE,
 43		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 44		.init_execlists = logical_render_ring_init,
 45		.init_legacy = intel_init_render_ring_buffer,
 46	},
 47	[BCS] = {
 48		.name = "blitter ring",
 49		.exec_id = I915_EXEC_BLT,
 50		.hw_id = BCS_HW,
 51		.mmio_base = BLT_RING_BASE,
 52		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 53		.init_execlists = logical_xcs_ring_init,
 54		.init_legacy = intel_init_blt_ring_buffer,
 55	},
 56	[VCS] = {
 57		.name = "bsd ring",
 58		.exec_id = I915_EXEC_BSD,
 59		.hw_id = VCS_HW,
 60		.mmio_base = GEN6_BSD_RING_BASE,
 61		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 62		.init_execlists = logical_xcs_ring_init,
 63		.init_legacy = intel_init_bsd_ring_buffer,
 64	},
 65	[VCS2] = {
 66		.name = "bsd2 ring",
 67		.exec_id = I915_EXEC_BSD,
 68		.hw_id = VCS2_HW,
 69		.mmio_base = GEN8_BSD2_RING_BASE,
 70		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 71		.init_execlists = logical_xcs_ring_init,
 72		.init_legacy = intel_init_bsd2_ring_buffer,
 73	},
 74	[VECS] = {
 75		.name = "video enhancement ring",
 76		.exec_id = I915_EXEC_VEBOX,
 77		.hw_id = VECS_HW,
 78		.mmio_base = VEBOX_RING_BASE,
 79		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 80		.init_execlists = logical_xcs_ring_init,
 81		.init_legacy = intel_init_vebox_ring_buffer,
 82	},
 83};
 84
 85static int
 86intel_engine_setup(struct drm_i915_private *dev_priv,
 87		   enum intel_engine_id id)
 88{
 89	const struct engine_info *info = &intel_engines[id];
 90	struct intel_engine_cs *engine;
 91
 92	GEM_BUG_ON(dev_priv->engine[id]);
 93	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
 94	if (!engine)
 95		return -ENOMEM;
 96
 97	engine->id = id;
 98	engine->i915 = dev_priv;
 99	engine->name = info->name;
100	engine->exec_id = info->exec_id;
101	engine->hw_id = engine->guc_id = info->hw_id;
102	engine->mmio_base = info->mmio_base;
103	engine->irq_shift = info->irq_shift;
104
105	/* Nothing to do here, execute in order of dependencies */
106	engine->schedule = NULL;
107
108	dev_priv->engine[id] = engine;
109	return 0;
110}
111
112/**
113 * intel_engines_init() - allocate, populate and init the Engine Command Streamers
114 * @dev: DRM device.
115 *
116 * Return: non-zero if the initialization failed.
117 */
118int intel_engines_init(struct drm_device *dev)
119{
120	struct drm_i915_private *dev_priv = to_i915(dev);
121	struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
122	unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
123	unsigned int mask = 0;
124	int (*init)(struct intel_engine_cs *engine);
125	struct intel_engine_cs *engine;
126	enum intel_engine_id id;
127	unsigned int i;
128	int ret;
129
130	WARN_ON(ring_mask == 0);
131	WARN_ON(ring_mask &
132		GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
133
134	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
135		if (!HAS_ENGINE(dev_priv, i))
136			continue;
137
138		if (i915.enable_execlists)
139			init = intel_engines[i].init_execlists;
140		else
141			init = intel_engines[i].init_legacy;
142
143		if (!init)
144			continue;
145
146		ret = intel_engine_setup(dev_priv, i);
147		if (ret)
148			goto cleanup;
149
150		ret = init(dev_priv->engine[i]);
151		if (ret)
152			goto cleanup;
153
154		mask |= ENGINE_MASK(i);
155	}
156
157	/*
158	 * Catch failures to update intel_engines table when the new engines
159	 * are added to the driver by a warning and disabling the forgotten
160	 * engines.
161	 */
162	if (WARN_ON(mask != ring_mask))
163		device_info->ring_mask = mask;
164
165	device_info->num_rings = hweight32(mask);
166
167	return 0;
168
169cleanup:
170	for_each_engine(engine, dev_priv, id) {
171		if (i915.enable_execlists)
172			intel_logical_ring_cleanup(engine);
173		else
174			intel_engine_cleanup(engine);
175	}
176
177	return ret;
178}
179
180void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
181{
182	struct drm_i915_private *dev_priv = engine->i915;
183
184	/* Our semaphore implementation is strictly monotonic (i.e. we proceed
185	 * so long as the semaphore value in the register/page is greater
186	 * than the sync value), so whenever we reset the seqno,
187	 * so long as we reset the tracking semaphore value to 0, it will
188	 * always be before the next request's seqno. If we don't reset
189	 * the semaphore value, then when the seqno moves backwards all
190	 * future waits will complete instantly (causing rendering corruption).
191	 */
192	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
193		I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
194		I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
195		if (HAS_VEBOX(dev_priv))
196			I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
197	}
198	if (dev_priv->semaphore) {
199		struct page *page = i915_vma_first_page(dev_priv->semaphore);
200		void *semaphores;
201
202		/* Semaphores are in noncoherent memory, flush to be safe */
203		semaphores = kmap(page);
204		memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
205		       0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
206		drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
207				       I915_NUM_ENGINES * gen8_semaphore_seqno_size);
208		kunmap(page);
209	}
210
211	intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
212	if (engine->irq_seqno_barrier)
213		engine->irq_seqno_barrier(engine);
214
215	GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
216	engine->timeline->last_submitted_seqno = seqno;
217
218	engine->hangcheck.seqno = seqno;
219
220	/* After manually advancing the seqno, fake the interrupt in case
221	 * there are any waiters for that seqno.
222	 */
223	intel_engine_wakeup(engine);
224}
225
226static void intel_engine_init_timeline(struct intel_engine_cs *engine)
227{
228	engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
229}
230
231/**
232 * intel_engines_setup_common - setup engine state not requiring hw access
233 * @engine: Engine to setup.
234 *
235 * Initializes @engine@ structure members shared between legacy and execlists
236 * submission modes which do not require hardware access.
237 *
238 * Typically done early in the submission mode specific engine setup stage.
239 */
240void intel_engine_setup_common(struct intel_engine_cs *engine)
241{
242	engine->execlist_queue = RB_ROOT;
243	engine->execlist_first = NULL;
244
245	intel_engine_init_timeline(engine);
246	intel_engine_init_hangcheck(engine);
247	i915_gem_batch_pool_init(engine, &engine->batch_pool);
248
249	intel_engine_init_cmd_parser(engine);
250}
251
252int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
253{
254	struct drm_i915_gem_object *obj;
255	struct i915_vma *vma;
256	int ret;
257
258	WARN_ON(engine->scratch);
259
260	obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
261	if (!obj)
262		obj = i915_gem_object_create_internal(engine->i915, size);
263	if (IS_ERR(obj)) {
264		DRM_ERROR("Failed to allocate scratch page\n");
265		return PTR_ERR(obj);
266	}
267
268	vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
269	if (IS_ERR(vma)) {
270		ret = PTR_ERR(vma);
271		goto err_unref;
272	}
273
274	ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
275	if (ret)
276		goto err_unref;
277
278	engine->scratch = vma;
279	DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
280			 engine->name, i915_ggtt_offset(vma));
281	return 0;
282
283err_unref:
284	i915_gem_object_put(obj);
285	return ret;
286}
287
288static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
289{
290	i915_vma_unpin_and_release(&engine->scratch);
291}
292
293/**
294 * intel_engines_init_common - initialize cengine state which might require hw access
295 * @engine: Engine to initialize.
296 *
297 * Initializes @engine@ structure members shared between legacy and execlists
298 * submission modes which do require hardware access.
299 *
300 * Typcally done at later stages of submission mode specific engine setup.
301 *
302 * Returns zero on success or an error code on failure.
303 */
304int intel_engine_init_common(struct intel_engine_cs *engine)
305{
306	int ret;
307
308	ret = intel_engine_init_breadcrumbs(engine);
309	if (ret)
310		return ret;
311
312	ret = i915_gem_render_state_init(engine);
313	if (ret)
314		return ret;
315
316	return 0;
317}
318
319/**
320 * intel_engines_cleanup_common - cleans up the engine state created by
321 *                                the common initiailizers.
322 * @engine: Engine to cleanup.
323 *
324 * This cleans up everything created by the common helpers.
325 */
326void intel_engine_cleanup_common(struct intel_engine_cs *engine)
327{
328	intel_engine_cleanup_scratch(engine);
329
330	i915_gem_render_state_fini(engine);
331	intel_engine_fini_breadcrumbs(engine);
332	intel_engine_cleanup_cmd_parser(engine);
333	i915_gem_batch_pool_fini(&engine->batch_pool);
334}
335
336u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
337{
338	struct drm_i915_private *dev_priv = engine->i915;
339	u64 acthd;
340
341	if (INTEL_GEN(dev_priv) >= 8)
342		acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
343					 RING_ACTHD_UDW(engine->mmio_base));
344	else if (INTEL_GEN(dev_priv) >= 4)
345		acthd = I915_READ(RING_ACTHD(engine->mmio_base));
346	else
347		acthd = I915_READ(ACTHD);
348
349	return acthd;
350}
351
352u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
353{
354	struct drm_i915_private *dev_priv = engine->i915;
355	u64 bbaddr;
356
357	if (INTEL_GEN(dev_priv) >= 8)
358		bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
359					  RING_BBADDR_UDW(engine->mmio_base));
360	else
361		bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
362
363	return bbaddr;
364}
365
366const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
367{
368	switch (type) {
369	case I915_CACHE_NONE: return " uncached";
370	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
371	case I915_CACHE_L3_LLC: return " L3+LLC";
372	case I915_CACHE_WT: return " WT";
373	default: return "";
374	}
375}
376
377static inline uint32_t
378read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
379		  int subslice, i915_reg_t reg)
380{
381	uint32_t mcr;
382	uint32_t ret;
383	enum forcewake_domains fw_domains;
384
385	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
386						    FW_REG_READ);
387	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
388						     GEN8_MCR_SELECTOR,
389						     FW_REG_READ | FW_REG_WRITE);
390
391	spin_lock_irq(&dev_priv->uncore.lock);
392	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
393
394	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
395	/*
396	 * The HW expects the slice and sublice selectors to be reset to 0
397	 * after reading out the registers.
398	 */
399	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
400	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
401	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
402	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
403
404	ret = I915_READ_FW(reg);
405
406	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
407	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
408
409	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
410	spin_unlock_irq(&dev_priv->uncore.lock);
411
412	return ret;
413}
414
415/* NB: please notice the memset */
416void intel_engine_get_instdone(struct intel_engine_cs *engine,
417			       struct intel_instdone *instdone)
418{
419	struct drm_i915_private *dev_priv = engine->i915;
420	u32 mmio_base = engine->mmio_base;
421	int slice;
422	int subslice;
423
424	memset(instdone, 0, sizeof(*instdone));
425
426	switch (INTEL_GEN(dev_priv)) {
427	default:
428		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
429
430		if (engine->id != RCS)
431			break;
432
433		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
434		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
435			instdone->sampler[slice][subslice] =
436				read_subslice_reg(dev_priv, slice, subslice,
437						  GEN7_SAMPLER_INSTDONE);
438			instdone->row[slice][subslice] =
439				read_subslice_reg(dev_priv, slice, subslice,
440						  GEN7_ROW_INSTDONE);
441		}
442		break;
443	case 7:
444		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
445
446		if (engine->id != RCS)
447			break;
448
449		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
450		instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
451		instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
452
453		break;
454	case 6:
455	case 5:
456	case 4:
457		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
458
459		if (engine->id == RCS)
460			/* HACK: Using the wrong struct member */
461			instdone->slice_common = I915_READ(GEN4_INSTDONE1);
462		break;
463	case 3:
464	case 2:
465		instdone->instdone = I915_READ(GEN2_INSTDONE);
466		break;
467	}
468}