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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/kernel.h>
25#include <linux/component.h>
26#include <drm/i915_component.h>
27#include "intel_drv.h"
28
29#include <drm/drmP.h>
30#include <drm/drm_edid.h>
31#include "i915_drv.h"
32
33/**
34 * DOC: High Definition Audio over HDMI and Display Port
35 *
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
41 *
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
46 *
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
52 * covered here.)
53 *
54 * The struct &i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
58 */
59
60/* DP N/M table */
61#define LC_540M 540000
62#define LC_270M 270000
63#define LC_162M 162000
64
65struct dp_aud_n_m {
66 int sample_rate;
67 int clock;
68 u16 m;
69 u16 n;
70};
71
72/* Values according to DP 1.4 Table 2-104 */
73static const struct dp_aud_n_m dp_aud_n_m[] = {
74 { 32000, LC_162M, 1024, 10125 },
75 { 44100, LC_162M, 784, 5625 },
76 { 48000, LC_162M, 512, 3375 },
77 { 64000, LC_162M, 2048, 10125 },
78 { 88200, LC_162M, 1568, 5625 },
79 { 96000, LC_162M, 1024, 3375 },
80 { 128000, LC_162M, 4096, 10125 },
81 { 176400, LC_162M, 3136, 5625 },
82 { 192000, LC_162M, 2048, 3375 },
83 { 32000, LC_270M, 1024, 16875 },
84 { 44100, LC_270M, 784, 9375 },
85 { 48000, LC_270M, 512, 5625 },
86 { 64000, LC_270M, 2048, 16875 },
87 { 88200, LC_270M, 1568, 9375 },
88 { 96000, LC_270M, 1024, 5625 },
89 { 128000, LC_270M, 4096, 16875 },
90 { 176400, LC_270M, 3136, 9375 },
91 { 192000, LC_270M, 2048, 5625 },
92 { 32000, LC_540M, 1024, 33750 },
93 { 44100, LC_540M, 784, 18750 },
94 { 48000, LC_540M, 512, 11250 },
95 { 64000, LC_540M, 2048, 33750 },
96 { 88200, LC_540M, 1568, 18750 },
97 { 96000, LC_540M, 1024, 11250 },
98 { 128000, LC_540M, 4096, 33750 },
99 { 176400, LC_540M, 3136, 18750 },
100 { 192000, LC_540M, 2048, 11250 },
101};
102
103static const struct dp_aud_n_m *
104audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate)
105{
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
109 if (rate == dp_aud_n_m[i].sample_rate &&
110 intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
111 return &dp_aud_n_m[i];
112 }
113
114 return NULL;
115}
116
117static const struct {
118 int clock;
119 u32 config;
120} hdmi_audio_clock[] = {
121 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
122 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
123 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
124 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
125 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
126 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
127 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
128 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
129 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
130 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
131};
132
133/* HDMI N/CTS table */
134#define TMDS_297M 297000
135#define TMDS_296M 296703
136static const struct {
137 int sample_rate;
138 int clock;
139 int n;
140 int cts;
141} hdmi_aud_ncts[] = {
142 { 44100, TMDS_296M, 4459, 234375 },
143 { 44100, TMDS_297M, 4704, 247500 },
144 { 48000, TMDS_296M, 5824, 281250 },
145 { 48000, TMDS_297M, 5120, 247500 },
146 { 32000, TMDS_296M, 5824, 421875 },
147 { 32000, TMDS_297M, 3072, 222750 },
148 { 88200, TMDS_296M, 8918, 234375 },
149 { 88200, TMDS_297M, 9408, 247500 },
150 { 96000, TMDS_296M, 11648, 281250 },
151 { 96000, TMDS_297M, 10240, 247500 },
152 { 176400, TMDS_296M, 17836, 234375 },
153 { 176400, TMDS_297M, 18816, 247500 },
154 { 192000, TMDS_296M, 23296, 281250 },
155 { 192000, TMDS_297M, 20480, 247500 },
156};
157
158/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
159static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
160{
161 int i;
162
163 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
164 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
165 break;
166 }
167
168 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
169 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
170 adjusted_mode->crtc_clock);
171 i = 1;
172 }
173
174 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
175 hdmi_audio_clock[i].clock,
176 hdmi_audio_clock[i].config);
177
178 return hdmi_audio_clock[i].config;
179}
180
181static int audio_config_hdmi_get_n(const struct drm_display_mode *adjusted_mode,
182 int rate)
183{
184 int i;
185
186 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
187 if (rate == hdmi_aud_ncts[i].sample_rate &&
188 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
189 return hdmi_aud_ncts[i].n;
190 }
191 }
192 return 0;
193}
194
195static bool intel_eld_uptodate(struct drm_connector *connector,
196 i915_reg_t reg_eldv, uint32_t bits_eldv,
197 i915_reg_t reg_elda, uint32_t bits_elda,
198 i915_reg_t reg_edid)
199{
200 struct drm_i915_private *dev_priv = to_i915(connector->dev);
201 uint8_t *eld = connector->eld;
202 uint32_t tmp;
203 int i;
204
205 tmp = I915_READ(reg_eldv);
206 tmp &= bits_eldv;
207
208 if (!tmp)
209 return false;
210
211 tmp = I915_READ(reg_elda);
212 tmp &= ~bits_elda;
213 I915_WRITE(reg_elda, tmp);
214
215 for (i = 0; i < drm_eld_size(eld) / 4; i++)
216 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
217 return false;
218
219 return true;
220}
221
222static void g4x_audio_codec_disable(struct intel_encoder *encoder)
223{
224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
225 uint32_t eldv, tmp;
226
227 DRM_DEBUG_KMS("Disable audio codec\n");
228
229 tmp = I915_READ(G4X_AUD_VID_DID);
230 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
231 eldv = G4X_ELDV_DEVCL_DEVBLC;
232 else
233 eldv = G4X_ELDV_DEVCTG;
234
235 /* Invalidate ELD */
236 tmp = I915_READ(G4X_AUD_CNTL_ST);
237 tmp &= ~eldv;
238 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
239}
240
241static void g4x_audio_codec_enable(struct drm_connector *connector,
242 struct intel_encoder *encoder,
243 const struct drm_display_mode *adjusted_mode)
244{
245 struct drm_i915_private *dev_priv = to_i915(connector->dev);
246 uint8_t *eld = connector->eld;
247 uint32_t eldv;
248 uint32_t tmp;
249 int len, i;
250
251 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
252
253 tmp = I915_READ(G4X_AUD_VID_DID);
254 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
255 eldv = G4X_ELDV_DEVCL_DEVBLC;
256 else
257 eldv = G4X_ELDV_DEVCTG;
258
259 if (intel_eld_uptodate(connector,
260 G4X_AUD_CNTL_ST, eldv,
261 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
262 G4X_HDMIW_HDMIEDID))
263 return;
264
265 tmp = I915_READ(G4X_AUD_CNTL_ST);
266 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
267 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
268 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
269
270 len = min(drm_eld_size(eld) / 4, len);
271 DRM_DEBUG_DRIVER("ELD size %d\n", len);
272 for (i = 0; i < len; i++)
273 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
274
275 tmp = I915_READ(G4X_AUD_CNTL_ST);
276 tmp |= eldv;
277 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
278}
279
280static void
281hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
282 const struct drm_display_mode *adjusted_mode)
283{
284 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
285 struct i915_audio_component *acomp = dev_priv->audio_component;
286 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
287 const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate);
288 enum pipe pipe = intel_crtc->pipe;
289 u32 tmp;
290
291 if (nm)
292 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
293 else
294 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
295
296 tmp = I915_READ(HSW_AUD_CFG(pipe));
297 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
298 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
299 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
300 tmp |= AUD_CONFIG_N_VALUE_INDEX;
301
302 if (nm) {
303 tmp &= ~AUD_CONFIG_N_MASK;
304 tmp |= AUD_CONFIG_N(nm->n);
305 tmp |= AUD_CONFIG_N_PROG_ENABLE;
306 }
307
308 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
309
310 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
311 tmp &= ~AUD_CONFIG_M_MASK;
312 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
313 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
314
315 if (nm) {
316 tmp |= nm->m;
317 tmp |= AUD_M_CTS_M_VALUE_INDEX;
318 tmp |= AUD_M_CTS_M_PROG_ENABLE;
319 }
320
321 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
322}
323
324static void
325hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
326 const struct drm_display_mode *adjusted_mode)
327{
328 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
329 struct i915_audio_component *acomp = dev_priv->audio_component;
330 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
331 enum pipe pipe = intel_crtc->pipe;
332 int n;
333 u32 tmp;
334
335 tmp = I915_READ(HSW_AUD_CFG(pipe));
336 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
337 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
338 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
339 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
340
341 n = audio_config_hdmi_get_n(adjusted_mode, rate);
342 if (n != 0) {
343 DRM_DEBUG_KMS("using N %d\n", n);
344
345 tmp &= ~AUD_CONFIG_N_MASK;
346 tmp |= AUD_CONFIG_N(n);
347 tmp |= AUD_CONFIG_N_PROG_ENABLE;
348 } else {
349 DRM_DEBUG_KMS("using automatic N\n");
350 }
351
352 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
353
354 /*
355 * Let's disable "Enable CTS or M Prog bit"
356 * and let HW calculate the value
357 */
358 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
359 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
360 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
361 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
362}
363
364static void
365hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
366 const struct drm_display_mode *adjusted_mode)
367{
368 if (intel_crtc_has_dp_encoder(intel_crtc->config))
369 hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode);
370 else
371 hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode);
372}
373
374static void hsw_audio_codec_disable(struct intel_encoder *encoder)
375{
376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
377 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
378 enum pipe pipe = intel_crtc->pipe;
379 uint32_t tmp;
380
381 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
382
383 mutex_lock(&dev_priv->av_mutex);
384
385 /* Disable timestamps */
386 tmp = I915_READ(HSW_AUD_CFG(pipe));
387 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
388 tmp |= AUD_CONFIG_N_PROG_ENABLE;
389 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
390 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
391 if (intel_crtc_has_dp_encoder(intel_crtc->config))
392 tmp |= AUD_CONFIG_N_VALUE_INDEX;
393 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
394
395 /* Invalidate ELD */
396 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
397 tmp &= ~AUDIO_ELD_VALID(pipe);
398 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
399 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
400
401 mutex_unlock(&dev_priv->av_mutex);
402}
403
404static void hsw_audio_codec_enable(struct drm_connector *connector,
405 struct intel_encoder *intel_encoder,
406 const struct drm_display_mode *adjusted_mode)
407{
408 struct drm_i915_private *dev_priv = to_i915(connector->dev);
409 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
410 enum pipe pipe = intel_crtc->pipe;
411 enum port port = intel_encoder->port;
412 const uint8_t *eld = connector->eld;
413 uint32_t tmp;
414 int len, i;
415
416 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
417 pipe_name(pipe), drm_eld_size(eld));
418
419 mutex_lock(&dev_priv->av_mutex);
420
421 /* Enable audio presence detect, invalidate ELD */
422 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
423 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
424 tmp &= ~AUDIO_ELD_VALID(pipe);
425 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
426
427 /*
428 * FIXME: We're supposed to wait for vblank here, but we have vblanks
429 * disabled during the mode set. The proper fix would be to push the
430 * rest of the setup into a vblank work item, queued here, but the
431 * infrastructure is not there yet.
432 */
433
434 /* Reset ELD write address */
435 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
436 tmp &= ~IBX_ELD_ADDRESS_MASK;
437 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
438
439 /* Up to 84 bytes of hw ELD buffer */
440 len = min(drm_eld_size(eld), 84);
441 for (i = 0; i < len / 4; i++)
442 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
443
444 /* ELD valid */
445 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
446 tmp |= AUDIO_ELD_VALID(pipe);
447 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
448
449 /* Enable timestamps */
450 hsw_audio_config_update(intel_crtc, port, adjusted_mode);
451
452 mutex_unlock(&dev_priv->av_mutex);
453}
454
455static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder)
456{
457 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
458 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
459 enum pipe pipe = intel_crtc->pipe;
460 enum port port = intel_encoder->port;
461 uint32_t tmp, eldv;
462 i915_reg_t aud_config, aud_cntrl_st2;
463
464 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
465 port_name(port), pipe_name(pipe));
466
467 if (WARN_ON(port == PORT_A))
468 return;
469
470 if (HAS_PCH_IBX(dev_priv)) {
471 aud_config = IBX_AUD_CFG(pipe);
472 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
473 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
474 aud_config = VLV_AUD_CFG(pipe);
475 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
476 } else {
477 aud_config = CPT_AUD_CFG(pipe);
478 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
479 }
480
481 /* Disable timestamps */
482 tmp = I915_READ(aud_config);
483 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
484 tmp |= AUD_CONFIG_N_PROG_ENABLE;
485 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
486 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
487 if (intel_crtc_has_dp_encoder(intel_crtc->config))
488 tmp |= AUD_CONFIG_N_VALUE_INDEX;
489 I915_WRITE(aud_config, tmp);
490
491 eldv = IBX_ELD_VALID(port);
492
493 /* Invalidate ELD */
494 tmp = I915_READ(aud_cntrl_st2);
495 tmp &= ~eldv;
496 I915_WRITE(aud_cntrl_st2, tmp);
497}
498
499static void ilk_audio_codec_enable(struct drm_connector *connector,
500 struct intel_encoder *intel_encoder,
501 const struct drm_display_mode *adjusted_mode)
502{
503 struct drm_i915_private *dev_priv = to_i915(connector->dev);
504 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
505 enum pipe pipe = intel_crtc->pipe;
506 enum port port = intel_encoder->port;
507 uint8_t *eld = connector->eld;
508 uint32_t tmp, eldv;
509 int len, i;
510 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
511
512 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
513 port_name(port), pipe_name(pipe), drm_eld_size(eld));
514
515 if (WARN_ON(port == PORT_A))
516 return;
517
518 /*
519 * FIXME: We're supposed to wait for vblank here, but we have vblanks
520 * disabled during the mode set. The proper fix would be to push the
521 * rest of the setup into a vblank work item, queued here, but the
522 * infrastructure is not there yet.
523 */
524
525 if (HAS_PCH_IBX(dev_priv)) {
526 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
527 aud_config = IBX_AUD_CFG(pipe);
528 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
529 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
530 } else if (IS_VALLEYVIEW(dev_priv) ||
531 IS_CHERRYVIEW(dev_priv)) {
532 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
533 aud_config = VLV_AUD_CFG(pipe);
534 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
535 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
536 } else {
537 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
538 aud_config = CPT_AUD_CFG(pipe);
539 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
540 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
541 }
542
543 eldv = IBX_ELD_VALID(port);
544
545 /* Invalidate ELD */
546 tmp = I915_READ(aud_cntrl_st2);
547 tmp &= ~eldv;
548 I915_WRITE(aud_cntrl_st2, tmp);
549
550 /* Reset ELD write address */
551 tmp = I915_READ(aud_cntl_st);
552 tmp &= ~IBX_ELD_ADDRESS_MASK;
553 I915_WRITE(aud_cntl_st, tmp);
554
555 /* Up to 84 bytes of hw ELD buffer */
556 len = min(drm_eld_size(eld), 84);
557 for (i = 0; i < len / 4; i++)
558 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
559
560 /* ELD valid */
561 tmp = I915_READ(aud_cntrl_st2);
562 tmp |= eldv;
563 I915_WRITE(aud_cntrl_st2, tmp);
564
565 /* Enable timestamps */
566 tmp = I915_READ(aud_config);
567 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
568 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
569 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
570 if (intel_crtc_has_dp_encoder(intel_crtc->config))
571 tmp |= AUD_CONFIG_N_VALUE_INDEX;
572 else
573 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
574 I915_WRITE(aud_config, tmp);
575}
576
577/**
578 * intel_audio_codec_enable - Enable the audio codec for HD audio
579 * @intel_encoder: encoder on which to enable audio
580 * @crtc_state: pointer to the current crtc state.
581 * @conn_state: pointer to the current connector state.
582 *
583 * The enable sequences may only be performed after enabling the transcoder and
584 * port, and after completed link training.
585 */
586void intel_audio_codec_enable(struct intel_encoder *intel_encoder,
587 const struct intel_crtc_state *crtc_state,
588 const struct drm_connector_state *conn_state)
589{
590 struct drm_encoder *encoder = &intel_encoder->base;
591 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
592 struct drm_connector *connector;
593 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
594 struct i915_audio_component *acomp = dev_priv->audio_component;
595 enum port port = intel_encoder->port;
596 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
597
598 connector = conn_state->connector;
599 if (!connector || !connector->eld[0])
600 return;
601
602 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
603 connector->base.id,
604 connector->name,
605 connector->encoder->base.id,
606 connector->encoder->name);
607
608 /* ELD Conn_Type */
609 connector->eld[5] &= ~(3 << 2);
610 if (intel_crtc_has_dp_encoder(crtc_state))
611 connector->eld[5] |= (1 << 2);
612
613 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
614
615 if (dev_priv->display.audio_codec_enable)
616 dev_priv->display.audio_codec_enable(connector, intel_encoder,
617 adjusted_mode);
618
619 mutex_lock(&dev_priv->av_mutex);
620 intel_encoder->audio_connector = connector;
621
622 /* referred in audio callbacks */
623 dev_priv->av_enc_map[pipe] = intel_encoder;
624 mutex_unlock(&dev_priv->av_mutex);
625
626 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
627 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
628 pipe = -1;
629
630 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
631 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
632 (int) port, (int) pipe);
633}
634
635/**
636 * intel_audio_codec_disable - Disable the audio codec for HD audio
637 * @intel_encoder: encoder on which to disable audio
638 *
639 * The disable sequences must be performed before disabling the transcoder or
640 * port.
641 */
642void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
643{
644 struct drm_encoder *encoder = &intel_encoder->base;
645 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
646 struct i915_audio_component *acomp = dev_priv->audio_component;
647 enum port port = intel_encoder->port;
648 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
649 enum pipe pipe = crtc->pipe;
650
651 if (dev_priv->display.audio_codec_disable)
652 dev_priv->display.audio_codec_disable(intel_encoder);
653
654 mutex_lock(&dev_priv->av_mutex);
655 intel_encoder->audio_connector = NULL;
656 dev_priv->av_enc_map[pipe] = NULL;
657 mutex_unlock(&dev_priv->av_mutex);
658
659 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
660 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
661 pipe = -1;
662
663 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
664 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
665 (int) port, (int) pipe);
666}
667
668/**
669 * intel_init_audio_hooks - Set up chip specific audio hooks
670 * @dev_priv: device private
671 */
672void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
673{
674 if (IS_G4X(dev_priv)) {
675 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
676 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
677 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
678 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
679 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
680 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
681 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
682 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
683 } else if (HAS_PCH_SPLIT(dev_priv)) {
684 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
685 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
686 }
687}
688
689static void i915_audio_component_get_power(struct device *kdev)
690{
691 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
692}
693
694static void i915_audio_component_put_power(struct device *kdev)
695{
696 intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
697}
698
699static void i915_audio_component_codec_wake_override(struct device *kdev,
700 bool enable)
701{
702 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
703 u32 tmp;
704
705 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
706 return;
707
708 i915_audio_component_get_power(kdev);
709
710 /*
711 * Enable/disable generating the codec wake signal, overriding the
712 * internal logic to generate the codec wake to controller.
713 */
714 tmp = I915_READ(HSW_AUD_CHICKENBIT);
715 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
716 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
717 usleep_range(1000, 1500);
718
719 if (enable) {
720 tmp = I915_READ(HSW_AUD_CHICKENBIT);
721 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
722 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
723 usleep_range(1000, 1500);
724 }
725
726 i915_audio_component_put_power(kdev);
727}
728
729/* Get CDCLK in kHz */
730static int i915_audio_component_get_cdclk_freq(struct device *kdev)
731{
732 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
733
734 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
735 return -ENODEV;
736
737 return dev_priv->cdclk_freq;
738}
739
740static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
741 int port, int pipe)
742{
743
744 if (WARN_ON(pipe >= I915_MAX_PIPES))
745 return NULL;
746
747 /* MST */
748 if (pipe >= 0)
749 return dev_priv->av_enc_map[pipe];
750
751 /* Non-MST */
752 for_each_pipe(dev_priv, pipe) {
753 struct intel_encoder *encoder;
754
755 encoder = dev_priv->av_enc_map[pipe];
756 if (encoder == NULL)
757 continue;
758
759 if (port == encoder->port)
760 return encoder;
761 }
762
763 return NULL;
764}
765
766static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
767 int pipe, int rate)
768{
769 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
770 struct intel_encoder *intel_encoder;
771 struct intel_crtc *crtc;
772 struct drm_display_mode *adjusted_mode;
773 struct i915_audio_component *acomp = dev_priv->audio_component;
774 int err = 0;
775
776 if (!HAS_DDI(dev_priv))
777 return 0;
778
779 i915_audio_component_get_power(kdev);
780 mutex_lock(&dev_priv->av_mutex);
781
782 /* 1. get the pipe */
783 intel_encoder = get_saved_enc(dev_priv, port, pipe);
784 if (!intel_encoder || !intel_encoder->base.crtc ||
785 (intel_encoder->type != INTEL_OUTPUT_HDMI &&
786 intel_encoder->type != INTEL_OUTPUT_DP)) {
787 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
788 err = -ENODEV;
789 goto unlock;
790 }
791
792 /* pipe passed from the audio driver will be -1 for Non-MST case */
793 crtc = to_intel_crtc(intel_encoder->base.crtc);
794 pipe = crtc->pipe;
795
796 adjusted_mode = &crtc->config->base.adjusted_mode;
797
798 /* port must be valid now, otherwise the pipe will be invalid */
799 acomp->aud_sample_rate[port] = rate;
800
801 hsw_audio_config_update(crtc, port, adjusted_mode);
802
803 unlock:
804 mutex_unlock(&dev_priv->av_mutex);
805 i915_audio_component_put_power(kdev);
806 return err;
807}
808
809static int i915_audio_component_get_eld(struct device *kdev, int port,
810 int pipe, bool *enabled,
811 unsigned char *buf, int max_bytes)
812{
813 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
814 struct intel_encoder *intel_encoder;
815 const u8 *eld;
816 int ret = -EINVAL;
817
818 mutex_lock(&dev_priv->av_mutex);
819
820 intel_encoder = get_saved_enc(dev_priv, port, pipe);
821 if (!intel_encoder) {
822 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
823 mutex_unlock(&dev_priv->av_mutex);
824 return ret;
825 }
826
827 ret = 0;
828 *enabled = intel_encoder->audio_connector != NULL;
829 if (*enabled) {
830 eld = intel_encoder->audio_connector->eld;
831 ret = drm_eld_size(eld);
832 memcpy(buf, eld, min(max_bytes, ret));
833 }
834
835 mutex_unlock(&dev_priv->av_mutex);
836 return ret;
837}
838
839static const struct i915_audio_component_ops i915_audio_component_ops = {
840 .owner = THIS_MODULE,
841 .get_power = i915_audio_component_get_power,
842 .put_power = i915_audio_component_put_power,
843 .codec_wake_override = i915_audio_component_codec_wake_override,
844 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
845 .sync_audio_rate = i915_audio_component_sync_audio_rate,
846 .get_eld = i915_audio_component_get_eld,
847};
848
849static int i915_audio_component_bind(struct device *i915_kdev,
850 struct device *hda_kdev, void *data)
851{
852 struct i915_audio_component *acomp = data;
853 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
854 int i;
855
856 if (WARN_ON(acomp->ops || acomp->dev))
857 return -EEXIST;
858
859 drm_modeset_lock_all(&dev_priv->drm);
860 acomp->ops = &i915_audio_component_ops;
861 acomp->dev = i915_kdev;
862 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
863 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
864 acomp->aud_sample_rate[i] = 0;
865 dev_priv->audio_component = acomp;
866 drm_modeset_unlock_all(&dev_priv->drm);
867
868 return 0;
869}
870
871static void i915_audio_component_unbind(struct device *i915_kdev,
872 struct device *hda_kdev, void *data)
873{
874 struct i915_audio_component *acomp = data;
875 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
876
877 drm_modeset_lock_all(&dev_priv->drm);
878 acomp->ops = NULL;
879 acomp->dev = NULL;
880 dev_priv->audio_component = NULL;
881 drm_modeset_unlock_all(&dev_priv->drm);
882}
883
884static const struct component_ops i915_audio_component_bind_ops = {
885 .bind = i915_audio_component_bind,
886 .unbind = i915_audio_component_unbind,
887};
888
889/**
890 * i915_audio_component_init - initialize and register the audio component
891 * @dev_priv: i915 device instance
892 *
893 * This will register with the component framework a child component which
894 * will bind dynamically to the snd_hda_intel driver's corresponding master
895 * component when the latter is registered. During binding the child
896 * initializes an instance of struct i915_audio_component which it receives
897 * from the master. The master can then start to use the interface defined by
898 * this struct. Each side can break the binding at any point by deregistering
899 * its own component after which each side's component unbind callback is
900 * called.
901 *
902 * We ignore any error during registration and continue with reduced
903 * functionality (i.e. without HDMI audio).
904 */
905void i915_audio_component_init(struct drm_i915_private *dev_priv)
906{
907 int ret;
908
909 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
910 if (ret < 0) {
911 DRM_ERROR("failed to add audio component (%d)\n", ret);
912 /* continue with reduced functionality */
913 return;
914 }
915
916 dev_priv->audio_component_registered = true;
917}
918
919/**
920 * i915_audio_component_cleanup - deregister the audio component
921 * @dev_priv: i915 device instance
922 *
923 * Deregisters the audio component, breaking any existing binding to the
924 * corresponding snd_hda_intel driver's master component.
925 */
926void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
927{
928 if (!dev_priv->audio_component_registered)
929 return;
930
931 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
932 dev_priv->audio_component_registered = false;
933}