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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#include <linux/firmware.h>
25#include <linux/circ_buf.h>
26#include <linux/debugfs.h>
27#include <linux/relay.h>
28#include "i915_drv.h"
29#include "intel_guc.h"
30
31/**
32 * DOC: GuC-based command submission
33 *
34 * i915_guc_client:
35 * We use the term client to avoid confusion with contexts. A i915_guc_client is
36 * equivalent to GuC object guc_context_desc. This context descriptor is
37 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
38 * and workqueue for it. Also the process descriptor (guc_process_desc), which
39 * is mapped to client space. So the client can write Work Item then ring the
40 * doorbell.
41 *
42 * To simplify the implementation, we allocate one gem object that contains all
43 * pages for doorbell, process descriptor and workqueue.
44 *
45 * The Scratch registers:
46 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
47 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
48 * triggers an interrupt on the GuC via another register write (0xC4C8).
49 * Firmware writes a success/fail code back to the action register after
50 * processes the request. The kernel driver polls waiting for this update and
51 * then proceeds.
52 * See host2guc_action()
53 *
54 * Doorbells:
55 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
56 * mapped into process space.
57 *
58 * Work Items:
59 * There are several types of work items that the host may place into a
60 * workqueue, each with its own requirements and limitations. Currently only
61 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
62 * represents in-order queue. The kernel driver packs ring tail pointer and an
63 * ELSP context descriptor dword into Work Item.
64 * See guc_wq_item_append()
65 *
66 */
67
68/*
69 * Read GuC command/status register (SOFT_SCRATCH_0)
70 * Return true if it contains a response rather than a command
71 */
72static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
73 u32 *status)
74{
75 u32 val = I915_READ(SOFT_SCRATCH(0));
76 *status = val;
77 return GUC2HOST_IS_RESPONSE(val);
78}
79
80static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
81{
82 struct drm_i915_private *dev_priv = guc_to_i915(guc);
83 u32 status;
84 int i;
85 int ret;
86
87 if (WARN_ON(len < 1 || len > 15))
88 return -EINVAL;
89
90 mutex_lock(&guc->action_lock);
91 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
92
93 dev_priv->guc.action_count += 1;
94 dev_priv->guc.action_cmd = data[0];
95
96 for (i = 0; i < len; i++)
97 I915_WRITE(SOFT_SCRATCH(i), data[i]);
98
99 POSTING_READ(SOFT_SCRATCH(i - 1));
100
101 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
102
103 /*
104 * Fast commands should complete in less than 10us, so sample quickly
105 * up to that length of time, then switch to a slower sleep-wait loop.
106 * No HOST2GUC command should ever take longer than 10ms.
107 */
108 ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
109 if (ret)
110 ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
111 if (status != GUC2HOST_STATUS_SUCCESS) {
112 /*
113 * Either the GuC explicitly returned an error (which
114 * we convert to -EIO here) or no response at all was
115 * received within the timeout limit (-ETIMEDOUT)
116 */
117 if (ret != -ETIMEDOUT)
118 ret = -EIO;
119
120 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
121 data[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
122
123 dev_priv->guc.action_fail += 1;
124 dev_priv->guc.action_err = ret;
125 }
126 dev_priv->guc.action_status = status;
127
128 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
129 mutex_unlock(&guc->action_lock);
130
131 return ret;
132}
133
134/*
135 * Tell the GuC to allocate or deallocate a specific doorbell
136 */
137
138static int host2guc_allocate_doorbell(struct intel_guc *guc,
139 struct i915_guc_client *client)
140{
141 u32 data[2];
142
143 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
144 data[1] = client->ctx_index;
145
146 return host2guc_action(guc, data, 2);
147}
148
149static int host2guc_release_doorbell(struct intel_guc *guc,
150 struct i915_guc_client *client)
151{
152 u32 data[2];
153
154 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
155 data[1] = client->ctx_index;
156
157 return host2guc_action(guc, data, 2);
158}
159
160static int host2guc_sample_forcewake(struct intel_guc *guc,
161 struct i915_guc_client *client)
162{
163 struct drm_i915_private *dev_priv = guc_to_i915(guc);
164 u32 data[2];
165
166 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
167 /* WaRsDisableCoarsePowerGating:skl,bxt */
168 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
169 data[1] = 0;
170 else
171 /* bit 0 and 1 are for Render and Media domain separately */
172 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
173
174 return host2guc_action(guc, data, ARRAY_SIZE(data));
175}
176
177static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
178{
179 u32 data[1];
180
181 data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
182
183 return host2guc_action(guc, data, 1);
184}
185
186static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
187{
188 u32 data[2];
189
190 data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
191 data[1] = 0;
192
193 return host2guc_action(guc, data, 2);
194}
195
196static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
197{
198 u32 data[2];
199
200 data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING;
201 data[1] = control_val;
202
203 return host2guc_action(guc, data, 2);
204}
205
206/*
207 * Initialise, update, or clear doorbell data shared with the GuC
208 *
209 * These functions modify shared data and so need access to the mapped
210 * client object which contains the page being used for the doorbell
211 */
212
213static int guc_update_doorbell_id(struct intel_guc *guc,
214 struct i915_guc_client *client,
215 u16 new_id)
216{
217 struct sg_table *sg = guc->ctx_pool_vma->pages;
218 void *doorbell_bitmap = guc->doorbell_bitmap;
219 struct guc_doorbell_info *doorbell;
220 struct guc_context_desc desc;
221 size_t len;
222
223 doorbell = client->vaddr + client->doorbell_offset;
224
225 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
226 test_bit(client->doorbell_id, doorbell_bitmap)) {
227 /* Deactivate the old doorbell */
228 doorbell->db_status = GUC_DOORBELL_DISABLED;
229 (void)host2guc_release_doorbell(guc, client);
230 __clear_bit(client->doorbell_id, doorbell_bitmap);
231 }
232
233 /* Update the GuC's idea of the doorbell ID */
234 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
235 sizeof(desc) * client->ctx_index);
236 if (len != sizeof(desc))
237 return -EFAULT;
238 desc.db_id = new_id;
239 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
240 sizeof(desc) * client->ctx_index);
241 if (len != sizeof(desc))
242 return -EFAULT;
243
244 client->doorbell_id = new_id;
245 if (new_id == GUC_INVALID_DOORBELL_ID)
246 return 0;
247
248 /* Activate the new doorbell */
249 __set_bit(new_id, doorbell_bitmap);
250 doorbell->cookie = 0;
251 doorbell->db_status = GUC_DOORBELL_ENABLED;
252 return host2guc_allocate_doorbell(guc, client);
253}
254
255static int guc_init_doorbell(struct intel_guc *guc,
256 struct i915_guc_client *client,
257 uint16_t db_id)
258{
259 return guc_update_doorbell_id(guc, client, db_id);
260}
261
262static void guc_disable_doorbell(struct intel_guc *guc,
263 struct i915_guc_client *client)
264{
265 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
266
267 /* XXX: wait for any interrupts */
268 /* XXX: wait for workqueue to drain */
269}
270
271static uint16_t
272select_doorbell_register(struct intel_guc *guc, uint32_t priority)
273{
274 /*
275 * The bitmap tracks which doorbell registers are currently in use.
276 * It is split into two halves; the first half is used for normal
277 * priority contexts, the second half for high-priority ones.
278 * Note that logically higher priorities are numerically less than
279 * normal ones, so the test below means "is it high-priority?"
280 */
281 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
282 const uint16_t half = GUC_MAX_DOORBELLS / 2;
283 const uint16_t start = hi_pri ? half : 0;
284 const uint16_t end = start + half;
285 uint16_t id;
286
287 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
288 if (id == end)
289 id = GUC_INVALID_DOORBELL_ID;
290
291 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
292 hi_pri ? "high" : "normal", id);
293
294 return id;
295}
296
297/*
298 * Select, assign and relase doorbell cachelines
299 *
300 * These functions track which doorbell cachelines are in use.
301 * The data they manipulate is protected by the host2guc lock.
302 */
303
304static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
305{
306 const uint32_t cacheline_size = cache_line_size();
307 uint32_t offset;
308
309 /* Doorbell uses a single cache line within a page */
310 offset = offset_in_page(guc->db_cacheline);
311
312 /* Moving to next cache line to reduce contention */
313 guc->db_cacheline += cacheline_size;
314
315 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
316 offset, guc->db_cacheline, cacheline_size);
317
318 return offset;
319}
320
321/*
322 * Initialise the process descriptor shared with the GuC firmware.
323 */
324static void guc_proc_desc_init(struct intel_guc *guc,
325 struct i915_guc_client *client)
326{
327 struct guc_process_desc *desc;
328
329 desc = client->vaddr + client->proc_desc_offset;
330
331 memset(desc, 0, sizeof(*desc));
332
333 /*
334 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
335 * space for ring3 clients (set them as in mmap_ioctl) or kernel
336 * space for kernel clients (map on demand instead? May make debug
337 * easier to have it mapped).
338 */
339 desc->wq_base_addr = 0;
340 desc->db_base_addr = 0;
341
342 desc->context_id = client->ctx_index;
343 desc->wq_size_bytes = client->wq_size;
344 desc->wq_status = WQ_STATUS_ACTIVE;
345 desc->priority = client->priority;
346}
347
348/*
349 * Initialise/clear the context descriptor shared with the GuC firmware.
350 *
351 * This descriptor tells the GuC where (in GGTT space) to find the important
352 * data structures relating to this client (doorbell, process descriptor,
353 * write queue, etc).
354 */
355
356static void guc_ctx_desc_init(struct intel_guc *guc,
357 struct i915_guc_client *client)
358{
359 struct drm_i915_private *dev_priv = guc_to_i915(guc);
360 struct intel_engine_cs *engine;
361 struct i915_gem_context *ctx = client->owner;
362 struct guc_context_desc desc;
363 struct sg_table *sg;
364 unsigned int tmp;
365 u32 gfx_addr;
366
367 memset(&desc, 0, sizeof(desc));
368
369 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
370 desc.context_id = client->ctx_index;
371 desc.priority = client->priority;
372 desc.db_id = client->doorbell_id;
373
374 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
375 struct intel_context *ce = &ctx->engine[engine->id];
376 uint32_t guc_engine_id = engine->guc_id;
377 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
378
379 /* TODO: We have a design issue to be solved here. Only when we
380 * receive the first batch, we know which engine is used by the
381 * user. But here GuC expects the lrc and ring to be pinned. It
382 * is not an issue for default context, which is the only one
383 * for now who owns a GuC client. But for future owner of GuC
384 * client, need to make sure lrc is pinned prior to enter here.
385 */
386 if (!ce->state)
387 break; /* XXX: continue? */
388
389 lrc->context_desc = lower_32_bits(ce->lrc_desc);
390
391 /* The state page is after PPHWSP */
392 lrc->ring_lcra =
393 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
394 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
395 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
396
397 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma);
398 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
399 lrc->ring_next_free_location = lrc->ring_begin;
400 lrc->ring_current_tail_pointer_value = 0;
401
402 desc.engines_used |= (1 << guc_engine_id);
403 }
404
405 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
406 client->engines, desc.engines_used);
407 WARN_ON(desc.engines_used == 0);
408
409 /*
410 * The doorbell, process descriptor, and workqueue are all parts
411 * of the client object, which the GuC will reference via the GGTT
412 */
413 gfx_addr = i915_ggtt_offset(client->vma);
414 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
415 client->doorbell_offset;
416 desc.db_trigger_cpu =
417 (uintptr_t)client->vaddr + client->doorbell_offset;
418 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
419 desc.process_desc = gfx_addr + client->proc_desc_offset;
420 desc.wq_addr = gfx_addr + client->wq_offset;
421 desc.wq_size = client->wq_size;
422
423 /*
424 * XXX: Take LRCs from an existing context if this is not an
425 * IsKMDCreatedContext client
426 */
427 desc.desc_private = (uintptr_t)client;
428
429 /* Pool context is pinned already */
430 sg = guc->ctx_pool_vma->pages;
431 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
432 sizeof(desc) * client->ctx_index);
433}
434
435static void guc_ctx_desc_fini(struct intel_guc *guc,
436 struct i915_guc_client *client)
437{
438 struct guc_context_desc desc;
439 struct sg_table *sg;
440
441 memset(&desc, 0, sizeof(desc));
442
443 sg = guc->ctx_pool_vma->pages;
444 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
445 sizeof(desc) * client->ctx_index);
446}
447
448/**
449 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
450 * @request: request associated with the commands
451 *
452 * Return: 0 if space is available
453 * -EAGAIN if space is not currently available
454 *
455 * This function must be called (and must return 0) before a request
456 * is submitted to the GuC via i915_guc_submit() below. Once a result
457 * of 0 has been returned, it must be balanced by a corresponding
458 * call to submit().
459 *
460 * Reservation allows the caller to determine in advance that space
461 * will be available for the next submission before committing resources
462 * to it, and helps avoid late failures with complicated recovery paths.
463 */
464int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
465{
466 const size_t wqi_size = sizeof(struct guc_wq_item);
467 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
468 struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset;
469 u32 freespace;
470 int ret;
471
472 spin_lock(&gc->wq_lock);
473 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
474 freespace -= gc->wq_rsvd;
475 if (likely(freespace >= wqi_size)) {
476 gc->wq_rsvd += wqi_size;
477 ret = 0;
478 } else {
479 gc->no_wq_space++;
480 ret = -EAGAIN;
481 }
482 spin_unlock(&gc->wq_lock);
483
484 return ret;
485}
486
487void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
488{
489 const size_t wqi_size = sizeof(struct guc_wq_item);
490 struct i915_guc_client *gc = request->i915->guc.execbuf_client;
491
492 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
493
494 spin_lock(&gc->wq_lock);
495 gc->wq_rsvd -= wqi_size;
496 spin_unlock(&gc->wq_lock);
497}
498
499/* Construct a Work Item and append it to the GuC's Work Queue */
500static void guc_wq_item_append(struct i915_guc_client *gc,
501 struct drm_i915_gem_request *rq)
502{
503 /* wqi_len is in DWords, and does not include the one-word header */
504 const size_t wqi_size = sizeof(struct guc_wq_item);
505 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
506 struct intel_engine_cs *engine = rq->engine;
507 struct guc_process_desc *desc;
508 struct guc_wq_item *wqi;
509 u32 freespace, tail, wq_off;
510
511 desc = gc->vaddr + gc->proc_desc_offset;
512
513 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
514 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
515 GEM_BUG_ON(freespace < wqi_size);
516
517 /* The GuC firmware wants the tail index in QWords, not bytes */
518 tail = rq->tail;
519 GEM_BUG_ON(tail & 7);
520 tail >>= 3;
521 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
522
523 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
524 * should not have the case where structure wqi is across page, neither
525 * wrapped to the beginning. This simplifies the implementation below.
526 *
527 * XXX: if not the case, we need save data to a temp wqi and copy it to
528 * workqueue buffer dw by dw.
529 */
530 BUILD_BUG_ON(wqi_size != 16);
531 GEM_BUG_ON(gc->wq_rsvd < wqi_size);
532
533 /* postincrement WQ tail for next time */
534 wq_off = gc->wq_tail;
535 GEM_BUG_ON(wq_off & (wqi_size - 1));
536 gc->wq_tail += wqi_size;
537 gc->wq_tail &= gc->wq_size - 1;
538 gc->wq_rsvd -= wqi_size;
539
540 /* WQ starts from the page after doorbell / process_desc */
541 wqi = gc->vaddr + wq_off + GUC_DB_SIZE;
542
543 /* Now fill in the 4-word work queue item */
544 wqi->header = WQ_TYPE_INORDER |
545 (wqi_len << WQ_LEN_SHIFT) |
546 (engine->guc_id << WQ_TARGET_SHIFT) |
547 WQ_NO_WCFLUSH_WAIT;
548
549 /* The GuC wants only the low-order word of the context descriptor */
550 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
551
552 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
553 wqi->fence_id = rq->global_seqno;
554}
555
556static int guc_ring_doorbell(struct i915_guc_client *gc)
557{
558 struct guc_process_desc *desc;
559 union guc_doorbell_qw db_cmp, db_exc, db_ret;
560 union guc_doorbell_qw *db;
561 int attempt = 2, ret = -EAGAIN;
562
563 desc = gc->vaddr + gc->proc_desc_offset;
564
565 /* Update the tail so it is visible to GuC */
566 desc->tail = gc->wq_tail;
567
568 /* current cookie */
569 db_cmp.db_status = GUC_DOORBELL_ENABLED;
570 db_cmp.cookie = gc->cookie;
571
572 /* cookie to be updated */
573 db_exc.db_status = GUC_DOORBELL_ENABLED;
574 db_exc.cookie = gc->cookie + 1;
575 if (db_exc.cookie == 0)
576 db_exc.cookie = 1;
577
578 /* pointer of current doorbell cacheline */
579 db = gc->vaddr + gc->doorbell_offset;
580
581 while (attempt--) {
582 /* lets ring the doorbell */
583 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
584 db_cmp.value_qw, db_exc.value_qw);
585
586 /* if the exchange was successfully executed */
587 if (db_ret.value_qw == db_cmp.value_qw) {
588 /* db was successfully rung */
589 gc->cookie = db_exc.cookie;
590 ret = 0;
591 break;
592 }
593
594 /* XXX: doorbell was lost and need to acquire it again */
595 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
596 break;
597
598 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
599 db_cmp.cookie, db_ret.cookie);
600
601 /* update the cookie to newly read cookie from GuC */
602 db_cmp.cookie = db_ret.cookie;
603 db_exc.cookie = db_ret.cookie + 1;
604 if (db_exc.cookie == 0)
605 db_exc.cookie = 1;
606 }
607
608 return ret;
609}
610
611/**
612 * i915_guc_submit() - Submit commands through GuC
613 * @rq: request associated with the commands
614 *
615 * Return: 0 on success, otherwise an errno.
616 * (Note: nonzero really shouldn't happen!)
617 *
618 * The caller must have already called i915_guc_wq_reserve() above with
619 * a result of 0 (success), guaranteeing that there is space in the work
620 * queue for the new request, so enqueuing the item cannot fail.
621 *
622 * Bad Things Will Happen if the caller violates this protocol e.g. calls
623 * submit() when _reserve() says there's no space, or calls _submit()
624 * a different number of times from (successful) calls to _reserve().
625 *
626 * The only error here arises if the doorbell hardware isn't functioning
627 * as expected, which really shouln't happen.
628 */
629static void i915_guc_submit(struct drm_i915_gem_request *rq)
630{
631 struct drm_i915_private *dev_priv = rq->i915;
632 struct intel_engine_cs *engine = rq->engine;
633 unsigned int engine_id = engine->id;
634 struct intel_guc *guc = &rq->i915->guc;
635 struct i915_guc_client *client = guc->execbuf_client;
636 int b_ret;
637
638 /* We keep the previous context alive until we retire the following
639 * request. This ensures that any the context object is still pinned
640 * for any residual writes the HW makes into it on the context switch
641 * into the next object following the breadcrumb. Otherwise, we may
642 * retire the context too early.
643 */
644 rq->previous_context = engine->last_context;
645 engine->last_context = rq->ctx;
646
647 i915_gem_request_submit(rq);
648
649 spin_lock(&client->wq_lock);
650 guc_wq_item_append(client, rq);
651
652 /* WA to flush out the pending GMADR writes to ring buffer. */
653 if (i915_vma_is_map_and_fenceable(rq->ring->vma))
654 POSTING_READ_FW(GUC_STATUS);
655
656 b_ret = guc_ring_doorbell(client);
657
658 client->submissions[engine_id] += 1;
659 client->retcode = b_ret;
660 if (b_ret)
661 client->b_fail += 1;
662
663 guc->submissions[engine_id] += 1;
664 guc->last_seqno[engine_id] = rq->global_seqno;
665 spin_unlock(&client->wq_lock);
666}
667
668/*
669 * Everything below here is concerned with setup & teardown, and is
670 * therefore not part of the somewhat time-critical batch-submission
671 * path of i915_guc_submit() above.
672 */
673
674/**
675 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
676 * @guc: the guc
677 * @size: size of area to allocate (both virtual space and memory)
678 *
679 * This is a wrapper to create an object for use with the GuC. In order to
680 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
681 * both some backing storage and a range inside the Global GTT. We must pin
682 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
683 * range is reserved inside GuC.
684 *
685 * Return: A i915_vma if successful, otherwise an ERR_PTR.
686 */
687static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
688{
689 struct drm_i915_private *dev_priv = guc_to_i915(guc);
690 struct drm_i915_gem_object *obj;
691 struct i915_vma *vma;
692 int ret;
693
694 obj = i915_gem_object_create(&dev_priv->drm, size);
695 if (IS_ERR(obj))
696 return ERR_CAST(obj);
697
698 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
699 if (IS_ERR(vma))
700 goto err;
701
702 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
703 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
704 if (ret) {
705 vma = ERR_PTR(ret);
706 goto err;
707 }
708
709 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
710 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
711
712 return vma;
713
714err:
715 i915_gem_object_put(obj);
716 return vma;
717}
718
719static void
720guc_client_free(struct drm_i915_private *dev_priv,
721 struct i915_guc_client *client)
722{
723 struct intel_guc *guc = &dev_priv->guc;
724
725 if (!client)
726 return;
727
728 /*
729 * XXX: wait for any outstanding submissions before freeing memory.
730 * Be sure to drop any locks
731 */
732
733 if (client->vaddr) {
734 /*
735 * If we got as far as setting up a doorbell, make sure we
736 * shut it down before unmapping & deallocating the memory.
737 */
738 guc_disable_doorbell(guc, client);
739
740 i915_gem_object_unpin_map(client->vma->obj);
741 }
742
743 i915_vma_unpin_and_release(&client->vma);
744
745 if (client->ctx_index != GUC_INVALID_CTX_ID) {
746 guc_ctx_desc_fini(guc, client);
747 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
748 }
749
750 kfree(client);
751}
752
753/* Check that a doorbell register is in the expected state */
754static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
755{
756 struct drm_i915_private *dev_priv = guc_to_i915(guc);
757 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
758 uint32_t value = I915_READ(drbreg);
759 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
760 bool expected = test_bit(db_id, guc->doorbell_bitmap);
761
762 if (enabled == expected)
763 return true;
764
765 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
766 db_id, drbreg.reg, value,
767 expected ? "active" : "inactive");
768
769 return false;
770}
771
772/*
773 * Borrow the first client to set up & tear down each unused doorbell
774 * in turn, to ensure that all doorbell h/w is (re)initialised.
775 */
776static void guc_init_doorbell_hw(struct intel_guc *guc)
777{
778 struct i915_guc_client *client = guc->execbuf_client;
779 uint16_t db_id;
780 int i, err;
781
782 /* Save client's original doorbell selection */
783 db_id = client->doorbell_id;
784
785 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
786 /* Skip if doorbell is OK */
787 if (guc_doorbell_check(guc, i))
788 continue;
789
790 err = guc_update_doorbell_id(guc, client, i);
791 if (err)
792 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
793 i, err);
794 }
795
796 /* Restore to original value */
797 err = guc_update_doorbell_id(guc, client, db_id);
798 if (err)
799 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
800 db_id, err);
801
802 /* Read back & verify all doorbell registers */
803 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
804 (void)guc_doorbell_check(guc, i);
805}
806
807/**
808 * guc_client_alloc() - Allocate an i915_guc_client
809 * @dev_priv: driver private data structure
810 * @engines: The set of engines to enable for this client
811 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
812 * The kernel client to replace ExecList submission is created with
813 * NORMAL priority. Priority of a client for scheduler can be HIGH,
814 * while a preemption context can use CRITICAL.
815 * @ctx: the context that owns the client (we use the default render
816 * context)
817 *
818 * Return: An i915_guc_client object if success, else NULL.
819 */
820static struct i915_guc_client *
821guc_client_alloc(struct drm_i915_private *dev_priv,
822 uint32_t engines,
823 uint32_t priority,
824 struct i915_gem_context *ctx)
825{
826 struct i915_guc_client *client;
827 struct intel_guc *guc = &dev_priv->guc;
828 struct i915_vma *vma;
829 void *vaddr;
830 uint16_t db_id;
831
832 client = kzalloc(sizeof(*client), GFP_KERNEL);
833 if (!client)
834 return NULL;
835
836 client->owner = ctx;
837 client->guc = guc;
838 client->engines = engines;
839 client->priority = priority;
840 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
841
842 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
843 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
844 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
845 client->ctx_index = GUC_INVALID_CTX_ID;
846 goto err;
847 }
848
849 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
850 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
851 if (IS_ERR(vma))
852 goto err;
853
854 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
855 client->vma = vma;
856
857 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
858 if (IS_ERR(vaddr))
859 goto err;
860
861 client->vaddr = vaddr;
862
863 spin_lock_init(&client->wq_lock);
864 client->wq_offset = GUC_DB_SIZE;
865 client->wq_size = GUC_WQ_SIZE;
866
867 db_id = select_doorbell_register(guc, client->priority);
868 if (db_id == GUC_INVALID_DOORBELL_ID)
869 /* XXX: evict a doorbell instead? */
870 goto err;
871
872 client->doorbell_offset = select_doorbell_cacheline(guc);
873
874 /*
875 * Since the doorbell only requires a single cacheline, we can save
876 * space by putting the application process descriptor in the same
877 * page. Use the half of the page that doesn't include the doorbell.
878 */
879 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
880 client->proc_desc_offset = 0;
881 else
882 client->proc_desc_offset = (GUC_DB_SIZE / 2);
883
884 guc_proc_desc_init(guc, client);
885 guc_ctx_desc_init(guc, client);
886 if (guc_init_doorbell(guc, client, db_id))
887 goto err;
888
889 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
890 priority, client, client->engines, client->ctx_index);
891 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
892 client->doorbell_id, client->doorbell_offset);
893
894 return client;
895
896err:
897 guc_client_free(dev_priv, client);
898 return NULL;
899}
900
901/*
902 * Sub buffer switch callback. Called whenever relay has to switch to a new
903 * sub buffer, relay stays on the same sub buffer if 0 is returned.
904 */
905static int subbuf_start_callback(struct rchan_buf *buf,
906 void *subbuf,
907 void *prev_subbuf,
908 size_t prev_padding)
909{
910 /* Use no-overwrite mode by default, where relay will stop accepting
911 * new data if there are no empty sub buffers left.
912 * There is no strict synchronization enforced by relay between Consumer
913 * and Producer. In overwrite mode, there is a possibility of getting
914 * inconsistent/garbled data, the producer could be writing on to the
915 * same sub buffer from which Consumer is reading. This can't be avoided
916 * unless Consumer is fast enough and can always run in tandem with
917 * Producer.
918 */
919 if (relay_buf_full(buf))
920 return 0;
921
922 return 1;
923}
924
925/*
926 * file_create() callback. Creates relay file in debugfs.
927 */
928static struct dentry *create_buf_file_callback(const char *filename,
929 struct dentry *parent,
930 umode_t mode,
931 struct rchan_buf *buf,
932 int *is_global)
933{
934 struct dentry *buf_file;
935
936 /* This to enable the use of a single buffer for the relay channel and
937 * correspondingly have a single file exposed to User, through which
938 * it can collect the logs in order without any post-processing.
939 * Need to set 'is_global' even if parent is NULL for early logging.
940 */
941 *is_global = 1;
942
943 if (!parent)
944 return NULL;
945
946 /* Not using the channel filename passed as an argument, since for each
947 * channel relay appends the corresponding CPU number to the filename
948 * passed in relay_open(). This should be fine as relay just needs a
949 * dentry of the file associated with the channel buffer and that file's
950 * name need not be same as the filename passed as an argument.
951 */
952 buf_file = debugfs_create_file("guc_log", mode,
953 parent, buf, &relay_file_operations);
954 return buf_file;
955}
956
957/*
958 * file_remove() default callback. Removes relay file in debugfs.
959 */
960static int remove_buf_file_callback(struct dentry *dentry)
961{
962 debugfs_remove(dentry);
963 return 0;
964}
965
966/* relay channel callbacks */
967static struct rchan_callbacks relay_callbacks = {
968 .subbuf_start = subbuf_start_callback,
969 .create_buf_file = create_buf_file_callback,
970 .remove_buf_file = remove_buf_file_callback,
971};
972
973static void guc_log_remove_relay_file(struct intel_guc *guc)
974{
975 relay_close(guc->log.relay_chan);
976}
977
978static int guc_log_create_relay_channel(struct intel_guc *guc)
979{
980 struct drm_i915_private *dev_priv = guc_to_i915(guc);
981 struct rchan *guc_log_relay_chan;
982 size_t n_subbufs, subbuf_size;
983
984 /* Keep the size of sub buffers same as shared log buffer */
985 subbuf_size = guc->log.vma->obj->base.size;
986
987 /* Store up to 8 snapshots, which is large enough to buffer sufficient
988 * boot time logs and provides enough leeway to User, in terms of
989 * latency, for consuming the logs from relay. Also doesn't take
990 * up too much memory.
991 */
992 n_subbufs = 8;
993
994 guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size,
995 n_subbufs, &relay_callbacks, dev_priv);
996 if (!guc_log_relay_chan) {
997 DRM_ERROR("Couldn't create relay chan for GuC logging\n");
998 return -ENOMEM;
999 }
1000
1001 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
1002 guc->log.relay_chan = guc_log_relay_chan;
1003 return 0;
1004}
1005
1006static int guc_log_create_relay_file(struct intel_guc *guc)
1007{
1008 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1009 struct dentry *log_dir;
1010 int ret;
1011
1012 /* For now create the log file in /sys/kernel/debug/dri/0 dir */
1013 log_dir = dev_priv->drm.primary->debugfs_root;
1014
1015 /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
1016 * not mounted and so can't create the relay file.
1017 * The relay API seems to fit well with debugfs only, for availing relay
1018 * there are 3 requirements which can be met for debugfs file only in a
1019 * straightforward/clean manner :-
1020 * i) Need the associated dentry pointer of the file, while opening the
1021 * relay channel.
1022 * ii) Should be able to use 'relay_file_operations' fops for the file.
1023 * iii) Set the 'i_private' field of file's inode to the pointer of
1024 * relay channel buffer.
1025 */
1026 if (!log_dir) {
1027 DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
1028 return -ENODEV;
1029 }
1030
1031 ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir);
1032 if (ret) {
1033 DRM_ERROR("Couldn't associate relay chan with file %d\n", ret);
1034 return ret;
1035 }
1036
1037 return 0;
1038}
1039
1040static void guc_move_to_next_buf(struct intel_guc *guc)
1041{
1042 /* Make sure the updates made in the sub buffer are visible when
1043 * Consumer sees the following update to offset inside the sub buffer.
1044 */
1045 smp_wmb();
1046
1047 /* All data has been written, so now move the offset of sub buffer. */
1048 relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size);
1049
1050 /* Switch to the next sub buffer */
1051 relay_flush(guc->log.relay_chan);
1052}
1053
1054static void *guc_get_write_buffer(struct intel_guc *guc)
1055{
1056 if (!guc->log.relay_chan)
1057 return NULL;
1058
1059 /* Just get the base address of a new sub buffer and copy data into it
1060 * ourselves. NULL will be returned in no-overwrite mode, if all sub
1061 * buffers are full. Could have used the relay_write() to indirectly
1062 * copy the data, but that would have been bit convoluted, as we need to
1063 * write to only certain locations inside a sub buffer which cannot be
1064 * done without using relay_reserve() along with relay_write(). So its
1065 * better to use relay_reserve() alone.
1066 */
1067 return relay_reserve(guc->log.relay_chan, 0);
1068}
1069
1070static bool
1071guc_check_log_buf_overflow(struct intel_guc *guc,
1072 enum guc_log_buffer_type type, unsigned int full_cnt)
1073{
1074 unsigned int prev_full_cnt = guc->log.prev_overflow_count[type];
1075 bool overflow = false;
1076
1077 if (full_cnt != prev_full_cnt) {
1078 overflow = true;
1079
1080 guc->log.prev_overflow_count[type] = full_cnt;
1081 guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt;
1082
1083 if (full_cnt < prev_full_cnt) {
1084 /* buffer_full_cnt is a 4 bit counter */
1085 guc->log.total_overflow_count[type] += 16;
1086 }
1087 DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
1088 }
1089
1090 return overflow;
1091}
1092
1093static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
1094{
1095 switch (type) {
1096 case GUC_ISR_LOG_BUFFER:
1097 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE;
1098 case GUC_DPC_LOG_BUFFER:
1099 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE;
1100 case GUC_CRASH_DUMP_LOG_BUFFER:
1101 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE;
1102 default:
1103 MISSING_CASE(type);
1104 }
1105
1106 return 0;
1107}
1108
1109static void guc_read_update_log_buffer(struct intel_guc *guc)
1110{
1111 unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
1112 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
1113 struct guc_log_buffer_state log_buf_state_local;
1114 enum guc_log_buffer_type type;
1115 void *src_data, *dst_data;
1116 bool new_overflow;
1117
1118 if (WARN_ON(!guc->log.buf_addr))
1119 return;
1120
1121 /* Get the pointer to shared GuC log buffer */
1122 log_buf_state = src_data = guc->log.buf_addr;
1123
1124 /* Get the pointer to local buffer to store the logs */
1125 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
1126
1127 /* Actual logs are present from the 2nd page */
1128 src_data += PAGE_SIZE;
1129 dst_data += PAGE_SIZE;
1130
1131 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
1132 /* Make a copy of the state structure, inside GuC log buffer
1133 * (which is uncached mapped), on the stack to avoid reading
1134 * from it multiple times.
1135 */
1136 memcpy(&log_buf_state_local, log_buf_state,
1137 sizeof(struct guc_log_buffer_state));
1138 buffer_size = guc_get_log_buffer_size(type);
1139 read_offset = log_buf_state_local.read_ptr;
1140 write_offset = log_buf_state_local.sampled_write_ptr;
1141 full_cnt = log_buf_state_local.buffer_full_cnt;
1142
1143 /* Bookkeeping stuff */
1144 guc->log.flush_count[type] += log_buf_state_local.flush_to_file;
1145 new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt);
1146
1147 /* Update the state of shared log buffer */
1148 log_buf_state->read_ptr = write_offset;
1149 log_buf_state->flush_to_file = 0;
1150 log_buf_state++;
1151
1152 if (unlikely(!log_buf_snapshot_state))
1153 continue;
1154
1155 /* First copy the state structure in snapshot buffer */
1156 memcpy(log_buf_snapshot_state, &log_buf_state_local,
1157 sizeof(struct guc_log_buffer_state));
1158
1159 /* The write pointer could have been updated by GuC firmware,
1160 * after sending the flush interrupt to Host, for consistency
1161 * set write pointer value to same value of sampled_write_ptr
1162 * in the snapshot buffer.
1163 */
1164 log_buf_snapshot_state->write_ptr = write_offset;
1165 log_buf_snapshot_state++;
1166
1167 /* Now copy the actual logs. */
1168 if (unlikely(new_overflow)) {
1169 /* copy the whole buffer in case of overflow */
1170 read_offset = 0;
1171 write_offset = buffer_size;
1172 } else if (unlikely((read_offset > buffer_size) ||
1173 (write_offset > buffer_size))) {
1174 DRM_ERROR("invalid log buffer state\n");
1175 /* copy whole buffer as offsets are unreliable */
1176 read_offset = 0;
1177 write_offset = buffer_size;
1178 }
1179
1180 /* Just copy the newly written data */
1181 if (read_offset > write_offset) {
1182 i915_memcpy_from_wc(dst_data, src_data, write_offset);
1183 bytes_to_copy = buffer_size - read_offset;
1184 } else {
1185 bytes_to_copy = write_offset - read_offset;
1186 }
1187 i915_memcpy_from_wc(dst_data + read_offset,
1188 src_data + read_offset, bytes_to_copy);
1189
1190 src_data += buffer_size;
1191 dst_data += buffer_size;
1192 }
1193
1194 if (log_buf_snapshot_state)
1195 guc_move_to_next_buf(guc);
1196 else {
1197 /* Used rate limited to avoid deluge of messages, logs might be
1198 * getting consumed by User at a slow rate.
1199 */
1200 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
1201 guc->log.capture_miss_count++;
1202 }
1203}
1204
1205static void guc_capture_logs_work(struct work_struct *work)
1206{
1207 struct drm_i915_private *dev_priv =
1208 container_of(work, struct drm_i915_private, guc.log.flush_work);
1209
1210 i915_guc_capture_logs(dev_priv);
1211}
1212
1213static void guc_log_cleanup(struct intel_guc *guc)
1214{
1215 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1216
1217 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1218
1219 /* First disable the flush interrupt */
1220 gen9_disable_guc_interrupts(dev_priv);
1221
1222 if (guc->log.flush_wq)
1223 destroy_workqueue(guc->log.flush_wq);
1224
1225 guc->log.flush_wq = NULL;
1226
1227 if (guc->log.relay_chan)
1228 guc_log_remove_relay_file(guc);
1229
1230 guc->log.relay_chan = NULL;
1231
1232 if (guc->log.buf_addr)
1233 i915_gem_object_unpin_map(guc->log.vma->obj);
1234
1235 guc->log.buf_addr = NULL;
1236}
1237
1238static int guc_log_create_extras(struct intel_guc *guc)
1239{
1240 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1241 void *vaddr;
1242 int ret;
1243
1244 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1245
1246 /* Nothing to do */
1247 if (i915.guc_log_level < 0)
1248 return 0;
1249
1250 if (!guc->log.buf_addr) {
1251 /* Create a WC (Uncached for read) vmalloc mapping of log
1252 * buffer pages, so that we can directly get the data
1253 * (up-to-date) from memory.
1254 */
1255 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC);
1256 if (IS_ERR(vaddr)) {
1257 ret = PTR_ERR(vaddr);
1258 DRM_ERROR("Couldn't map log buffer pages %d\n", ret);
1259 return ret;
1260 }
1261
1262 guc->log.buf_addr = vaddr;
1263 }
1264
1265 if (!guc->log.relay_chan) {
1266 /* Create a relay channel, so that we have buffers for storing
1267 * the GuC firmware logs, the channel will be linked with a file
1268 * later on when debugfs is registered.
1269 */
1270 ret = guc_log_create_relay_channel(guc);
1271 if (ret)
1272 return ret;
1273 }
1274
1275 if (!guc->log.flush_wq) {
1276 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work);
1277
1278 /*
1279 * GuC log buffer flush work item has to do register access to
1280 * send the ack to GuC and this work item, if not synced before
1281 * suspend, can potentially get executed after the GFX device is
1282 * suspended.
1283 * By marking the WQ as freezable, we don't have to bother about
1284 * flushing of this work item from the suspend hooks, the pending
1285 * work item if any will be either executed before the suspend
1286 * or scheduled later on resume. This way the handling of work
1287 * item can be kept same between system suspend & rpm suspend.
1288 */
1289 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log",
1290 WQ_HIGHPRI | WQ_FREEZABLE);
1291 if (guc->log.flush_wq == NULL) {
1292 DRM_ERROR("Couldn't allocate the wq for GuC logging\n");
1293 return -ENOMEM;
1294 }
1295 }
1296
1297 return 0;
1298}
1299
1300static void guc_log_create(struct intel_guc *guc)
1301{
1302 struct i915_vma *vma;
1303 unsigned long offset;
1304 uint32_t size, flags;
1305
1306 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
1307 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
1308
1309 /* The first page is to save log buffer state. Allocate one
1310 * extra page for others in case for overlap */
1311 size = (1 + GUC_LOG_DPC_PAGES + 1 +
1312 GUC_LOG_ISR_PAGES + 1 +
1313 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
1314
1315 vma = guc->log.vma;
1316 if (!vma) {
1317 /* We require SSE 4.1 for fast reads from the GuC log buffer and
1318 * it should be present on the chipsets supporting GuC based
1319 * submisssions.
1320 */
1321 if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) {
1322 /* logging will not be enabled */
1323 i915.guc_log_level = -1;
1324 return;
1325 }
1326
1327 vma = guc_allocate_vma(guc, size);
1328 if (IS_ERR(vma)) {
1329 /* logging will be off */
1330 i915.guc_log_level = -1;
1331 return;
1332 }
1333
1334 guc->log.vma = vma;
1335
1336 if (guc_log_create_extras(guc)) {
1337 guc_log_cleanup(guc);
1338 i915_vma_unpin_and_release(&guc->log.vma);
1339 i915.guc_log_level = -1;
1340 return;
1341 }
1342 }
1343
1344 /* each allocated unit is a page */
1345 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
1346 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
1347 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
1348 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
1349
1350 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
1351 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
1352}
1353
1354static int guc_log_late_setup(struct intel_guc *guc)
1355{
1356 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1357 int ret;
1358
1359 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1360
1361 if (i915.guc_log_level < 0)
1362 return -EINVAL;
1363
1364 /* If log_level was set as -1 at boot time, then setup needed to
1365 * handle log buffer flush interrupts would not have been done yet,
1366 * so do that now.
1367 */
1368 ret = guc_log_create_extras(guc);
1369 if (ret)
1370 goto err;
1371
1372 ret = guc_log_create_relay_file(guc);
1373 if (ret)
1374 goto err;
1375
1376 return 0;
1377err:
1378 guc_log_cleanup(guc);
1379 /* logging will remain off */
1380 i915.guc_log_level = -1;
1381 return ret;
1382}
1383
1384static void guc_policies_init(struct guc_policies *policies)
1385{
1386 struct guc_policy *policy;
1387 u32 p, i;
1388
1389 policies->dpc_promote_time = 500000;
1390 policies->max_num_work_items = POLICY_MAX_NUM_WI;
1391
1392 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
1393 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
1394 policy = &policies->policy[p][i];
1395
1396 policy->execution_quantum = 1000000;
1397 policy->preemption_time = 500000;
1398 policy->fault_time = 250000;
1399 policy->policy_flags = 0;
1400 }
1401 }
1402
1403 policies->is_valid = 1;
1404}
1405
1406static void guc_addon_create(struct intel_guc *guc)
1407{
1408 struct drm_i915_private *dev_priv = guc_to_i915(guc);
1409 struct i915_vma *vma;
1410 struct guc_ads *ads;
1411 struct guc_policies *policies;
1412 struct guc_mmio_reg_state *reg_state;
1413 struct intel_engine_cs *engine;
1414 enum intel_engine_id id;
1415 struct page *page;
1416 u32 size;
1417
1418 /* The ads obj includes the struct itself and buffers passed to GuC */
1419 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
1420 sizeof(struct guc_mmio_reg_state) +
1421 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
1422
1423 vma = guc->ads_vma;
1424 if (!vma) {
1425 vma = guc_allocate_vma(guc, PAGE_ALIGN(size));
1426 if (IS_ERR(vma))
1427 return;
1428
1429 guc->ads_vma = vma;
1430 }
1431
1432 page = i915_vma_first_page(vma);
1433 ads = kmap(page);
1434
1435 /*
1436 * The GuC requires a "Golden Context" when it reinitialises
1437 * engines after a reset. Here we use the Render ring default
1438 * context, which must already exist and be pinned in the GGTT,
1439 * so its address won't change after we've told the GuC where
1440 * to find it.
1441 */
1442 engine = dev_priv->engine[RCS];
1443 ads->golden_context_lrca = engine->status_page.ggtt_offset;
1444
1445 for_each_engine(engine, dev_priv, id)
1446 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
1447
1448 /* GuC scheduling policies */
1449 policies = (void *)ads + sizeof(struct guc_ads);
1450 guc_policies_init(policies);
1451
1452 ads->scheduler_policies =
1453 i915_ggtt_offset(vma) + sizeof(struct guc_ads);
1454
1455 /* MMIO reg state */
1456 reg_state = (void *)policies + sizeof(struct guc_policies);
1457
1458 for_each_engine(engine, dev_priv, id) {
1459 reg_state->mmio_white_list[engine->guc_id].mmio_start =
1460 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
1461
1462 /* Nothing to be saved or restored for now. */
1463 reg_state->mmio_white_list[engine->guc_id].count = 0;
1464 }
1465
1466 ads->reg_state_addr = ads->scheduler_policies +
1467 sizeof(struct guc_policies);
1468
1469 ads->reg_state_buffer = ads->reg_state_addr +
1470 sizeof(struct guc_mmio_reg_state);
1471
1472 kunmap(page);
1473}
1474
1475/*
1476 * Set up the memory resources to be shared with the GuC. At this point,
1477 * we require just one object that can be mapped through the GGTT.
1478 */
1479int i915_guc_submission_init(struct drm_i915_private *dev_priv)
1480{
1481 const size_t ctxsize = sizeof(struct guc_context_desc);
1482 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
1483 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
1484 struct intel_guc *guc = &dev_priv->guc;
1485 struct i915_vma *vma;
1486
1487 /* Wipe bitmap & delete client in case of reinitialisation */
1488 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
1489 i915_guc_submission_disable(dev_priv);
1490
1491 if (!i915.enable_guc_submission)
1492 return 0; /* not enabled */
1493
1494 if (guc->ctx_pool_vma)
1495 return 0; /* already allocated */
1496
1497 vma = guc_allocate_vma(guc, gemsize);
1498 if (IS_ERR(vma))
1499 return PTR_ERR(vma);
1500
1501 guc->ctx_pool_vma = vma;
1502 ida_init(&guc->ctx_ids);
1503 mutex_init(&guc->action_lock);
1504 guc_log_create(guc);
1505 guc_addon_create(guc);
1506
1507 return 0;
1508}
1509
1510int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1511{
1512 struct intel_guc *guc = &dev_priv->guc;
1513 struct drm_i915_gem_request *request;
1514 struct i915_guc_client *client;
1515 struct intel_engine_cs *engine;
1516 enum intel_engine_id id;
1517
1518 /* client for execbuf submission */
1519 client = guc_client_alloc(dev_priv,
1520 INTEL_INFO(dev_priv)->ring_mask,
1521 GUC_CTX_PRIORITY_KMD_NORMAL,
1522 dev_priv->kernel_context);
1523 if (!client) {
1524 DRM_ERROR("Failed to create normal GuC client!\n");
1525 return -ENOMEM;
1526 }
1527
1528 guc->execbuf_client = client;
1529 host2guc_sample_forcewake(guc, client);
1530 guc_init_doorbell_hw(guc);
1531
1532 /* Take over from manual control of ELSP (execlists) */
1533 for_each_engine(engine, dev_priv, id) {
1534 engine->submit_request = i915_guc_submit;
1535 engine->schedule = NULL;
1536
1537 /* Replay the current set of previously submitted requests */
1538 list_for_each_entry(request,
1539 &engine->timeline->requests, link) {
1540 client->wq_rsvd += sizeof(struct guc_wq_item);
1541 if (i915_sw_fence_done(&request->submit))
1542 i915_guc_submit(request);
1543 }
1544 }
1545
1546 return 0;
1547}
1548
1549void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1550{
1551 struct intel_guc *guc = &dev_priv->guc;
1552
1553 if (!guc->execbuf_client)
1554 return;
1555
1556 /* Revert back to manual ELSP submission */
1557 intel_execlists_enable_submission(dev_priv);
1558
1559 guc_client_free(dev_priv, guc->execbuf_client);
1560 guc->execbuf_client = NULL;
1561}
1562
1563void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1564{
1565 struct intel_guc *guc = &dev_priv->guc;
1566
1567 i915_vma_unpin_and_release(&guc->ads_vma);
1568 i915_vma_unpin_and_release(&guc->log.vma);
1569
1570 if (guc->ctx_pool_vma)
1571 ida_destroy(&guc->ctx_ids);
1572 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
1573}
1574
1575/**
1576 * intel_guc_suspend() - notify GuC entering suspend state
1577 * @dev: drm device
1578 */
1579int intel_guc_suspend(struct drm_device *dev)
1580{
1581 struct drm_i915_private *dev_priv = to_i915(dev);
1582 struct intel_guc *guc = &dev_priv->guc;
1583 struct i915_gem_context *ctx;
1584 u32 data[3];
1585
1586 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1587 return 0;
1588
1589 gen9_disable_guc_interrupts(dev_priv);
1590
1591 ctx = dev_priv->kernel_context;
1592
1593 data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
1594 /* any value greater than GUC_POWER_D0 */
1595 data[1] = GUC_POWER_D1;
1596 /* first page is shared data with GuC */
1597 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1598
1599 return host2guc_action(guc, data, ARRAY_SIZE(data));
1600}
1601
1602
1603/**
1604 * intel_guc_resume() - notify GuC resuming from suspend state
1605 * @dev: drm device
1606 */
1607int intel_guc_resume(struct drm_device *dev)
1608{
1609 struct drm_i915_private *dev_priv = to_i915(dev);
1610 struct intel_guc *guc = &dev_priv->guc;
1611 struct i915_gem_context *ctx;
1612 u32 data[3];
1613
1614 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
1615 return 0;
1616
1617 if (i915.guc_log_level >= 0)
1618 gen9_enable_guc_interrupts(dev_priv);
1619
1620 ctx = dev_priv->kernel_context;
1621
1622 data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
1623 data[1] = GUC_POWER_D0;
1624 /* first page is shared data with GuC */
1625 data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
1626
1627 return host2guc_action(guc, data, ARRAY_SIZE(data));
1628}
1629
1630void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
1631{
1632 guc_read_update_log_buffer(&dev_priv->guc);
1633
1634 /* Generally device is expected to be active only at this
1635 * time, so get/put should be really quick.
1636 */
1637 intel_runtime_pm_get(dev_priv);
1638 host2guc_logbuffer_flush_complete(&dev_priv->guc);
1639 intel_runtime_pm_put(dev_priv);
1640}
1641
1642void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
1643{
1644 if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
1645 return;
1646
1647 /* First disable the interrupts, will be renabled afterwards */
1648 gen9_disable_guc_interrupts(dev_priv);
1649
1650 /* Before initiating the forceful flush, wait for any pending/ongoing
1651 * flush to complete otherwise forceful flush may not actually happen.
1652 */
1653 flush_work(&dev_priv->guc.log.flush_work);
1654
1655 /* Ask GuC to update the log buffer state */
1656 host2guc_force_logbuffer_flush(&dev_priv->guc);
1657
1658 /* GuC would have updated log buffer by now, so capture it */
1659 i915_guc_capture_logs(dev_priv);
1660}
1661
1662void i915_guc_unregister(struct drm_i915_private *dev_priv)
1663{
1664 if (!i915.enable_guc_submission)
1665 return;
1666
1667 mutex_lock(&dev_priv->drm.struct_mutex);
1668 guc_log_cleanup(&dev_priv->guc);
1669 mutex_unlock(&dev_priv->drm.struct_mutex);
1670}
1671
1672void i915_guc_register(struct drm_i915_private *dev_priv)
1673{
1674 if (!i915.enable_guc_submission)
1675 return;
1676
1677 mutex_lock(&dev_priv->drm.struct_mutex);
1678 guc_log_late_setup(&dev_priv->guc);
1679 mutex_unlock(&dev_priv->drm.struct_mutex);
1680}
1681
1682int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
1683{
1684 union guc_log_control log_param;
1685 int ret;
1686
1687 log_param.value = control_val;
1688
1689 if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN ||
1690 log_param.verbosity > GUC_LOG_VERBOSITY_MAX)
1691 return -EINVAL;
1692
1693 /* This combination doesn't make sense & won't have any effect */
1694 if (!log_param.logging_enabled && (i915.guc_log_level < 0))
1695 return 0;
1696
1697 ret = host2guc_logging_control(&dev_priv->guc, log_param.value);
1698 if (ret < 0) {
1699 DRM_DEBUG_DRIVER("host2guc action failed %d\n", ret);
1700 return ret;
1701 }
1702
1703 i915.guc_log_level = log_param.verbosity;
1704
1705 /* If log_level was set as -1 at boot time, then the relay channel file
1706 * wouldn't have been created by now and interrupts also would not have
1707 * been enabled.
1708 */
1709 if (!dev_priv->guc.log.relay_chan) {
1710 ret = guc_log_late_setup(&dev_priv->guc);
1711 if (!ret)
1712 gen9_enable_guc_interrupts(dev_priv);
1713 } else if (!log_param.logging_enabled) {
1714 /* Once logging is disabled, GuC won't generate logs & send an
1715 * interrupt. But there could be some data in the log buffer
1716 * which is yet to be captured. So request GuC to update the log
1717 * buffer state and then collect the left over logs.
1718 */
1719 i915_guc_flush_logs(dev_priv);
1720
1721 /* As logging is disabled, update log level to reflect that */
1722 i915.guc_log_level = -1;
1723 } else {
1724 /* In case interrupts were disabled, enable them now */
1725 gen9_enable_guc_interrupts(dev_priv);
1726 }
1727
1728 return ret;
1729}