1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Mika Kuoppala <mika.kuoppala@intel.com>
 25 *
 26 */
 27
 28#include "i915_drv.h"
 29#include "intel_renderstate.h"
 30
 31struct intel_render_state {
 32	const struct intel_renderstate_rodata *rodata;
 33	struct i915_vma *vma;
 34	u32 batch_offset;
 35	u32 batch_size;
 36	u32 aux_offset;
 37	u32 aux_size;
 38};
 39
 40static const struct intel_renderstate_rodata *
 41render_state_get_rodata(const struct intel_engine_cs *engine)
 42{
 43	switch (INTEL_GEN(engine->i915)) {
 44	case 6:
 45		return &gen6_null_state;
 46	case 7:
 47		return &gen7_null_state;
 48	case 8:
 49		return &gen8_null_state;
 50	case 9:
 51		return &gen9_null_state;
 52	}
 53
 54	return NULL;
 55}
 56
 57/*
 58 * Macro to add commands to auxiliary batch.
 59 * This macro only checks for page overflow before inserting the commands,
 60 * this is sufficient as the null state generator makes the final batch
 61 * with two passes to build command and state separately. At this point
 62 * the size of both are known and it compacts them by relocating the state
 63 * right after the commands taking care of aligment so we should sufficient
 64 * space below them for adding new commands.
 65 */
 66#define OUT_BATCH(batch, i, val)				\
 67	do {							\
 68		if ((i) >= PAGE_SIZE / sizeof(u32))		\
 69			goto err;				\
 70		(batch)[(i)++] = (val);				\
 71	} while(0)
 72
 73static int render_state_setup(struct intel_render_state *so,
 74			      struct drm_i915_private *i915)
 75{
 76	const struct intel_renderstate_rodata *rodata = so->rodata;
 77	struct drm_i915_gem_object *obj = so->vma->obj;
 78	unsigned int i = 0, reloc_index = 0;
 79	unsigned int needs_clflush;
 80	u32 *d;
 81	int ret;
 82
 83	ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
 84	if (ret)
 85		return ret;
 86
 87	d = kmap_atomic(i915_gem_object_get_dirty_page(obj, 0));
 88
 89	while (i < rodata->batch_items) {
 90		u32 s = rodata->batch[i];
 91
 92		if (i * 4  == rodata->reloc[reloc_index]) {
 93			u64 r = s + so->vma->node.start;
 94			s = lower_32_bits(r);
 95			if (HAS_64BIT_RELOC(i915)) {
 96				if (i + 1 >= rodata->batch_items ||
 97				    rodata->batch[i + 1] != 0)
 98					goto err;
 99
100				d[i++] = s;
101				s = upper_32_bits(r);
102			}
103
104			reloc_index++;
105		}
106
107		d[i++] = s;
108	}
109
110	if (rodata->reloc[reloc_index] != -1) {
111		DRM_ERROR("only %d relocs resolved\n", reloc_index);
112		goto err;
113	}
114
115	so->batch_offset = so->vma->node.start;
116	so->batch_size = rodata->batch_items * sizeof(u32);
117
118	while (i % CACHELINE_DWORDS)
119		OUT_BATCH(d, i, MI_NOOP);
120
121	so->aux_offset = i * sizeof(u32);
122
123	if (HAS_POOLED_EU(i915)) {
124		/*
125		 * We always program 3x6 pool config but depending upon which
126		 * subslice is disabled HW drops down to appropriate config
127		 * shown below.
128		 *
129		 * In the below table 2x6 config always refers to
130		 * fused-down version, native 2x6 is not available and can
131		 * be ignored
132		 *
133		 * SNo  subslices config                eu pool configuration
134		 * -----------------------------------------------------------
135		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
136		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
137		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
138		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
139		 */
140		u32 eu_pool_config = 0x00777000;
141
142		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
143		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
144		OUT_BATCH(d, i, eu_pool_config);
145		OUT_BATCH(d, i, 0);
146		OUT_BATCH(d, i, 0);
147		OUT_BATCH(d, i, 0);
148	}
149
150	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
151	so->aux_size = i * sizeof(u32) - so->aux_offset;
152	so->aux_offset += so->batch_offset;
153	/*
154	 * Since we are sending length, we need to strictly conform to
155	 * all requirements. For Gen2 this must be a multiple of 8.
156	 */
157	so->aux_size = ALIGN(so->aux_size, 8);
158
159	if (needs_clflush)
160		drm_clflush_virt_range(d, i * sizeof(u32));
161	kunmap_atomic(d);
162
163	ret = i915_gem_object_set_to_gtt_domain(obj, false);
164out:
165	i915_gem_obj_finish_shmem_access(obj);
166	return ret;
167
168err:
169	kunmap_atomic(d);
170	ret = -EINVAL;
171	goto out;
172}
173
174#undef OUT_BATCH
175
176int i915_gem_render_state_init(struct intel_engine_cs *engine)
177{
178	struct intel_render_state *so;
179	const struct intel_renderstate_rodata *rodata;
180	struct drm_i915_gem_object *obj;
181	int ret;
182
183	if (engine->id != RCS)
184		return 0;
185
186	rodata = render_state_get_rodata(engine);
187	if (!rodata)
188		return 0;
189
190	if (rodata->batch_items * 4 > 4096)
191		return -EINVAL;
192
193	so = kmalloc(sizeof(*so), GFP_KERNEL);
194	if (!so)
195		return -ENOMEM;
196
197	obj = i915_gem_object_create_internal(engine->i915, 4096);
198	if (IS_ERR(obj)) {
199		ret = PTR_ERR(obj);
200		goto err_free;
201	}
202
203	so->vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
204	if (IS_ERR(so->vma)) {
205		ret = PTR_ERR(so->vma);
206		goto err_obj;
207	}
208
209	so->rodata = rodata;
210	engine->render_state = so;
211	return 0;
212
213err_obj:
214	i915_gem_object_put(obj);
215err_free:
216	kfree(so);
217	return ret;
218}
219
220int i915_gem_render_state_emit(struct drm_i915_gem_request *req)
221{
222	struct intel_render_state *so;
223	int ret;
224
225	lockdep_assert_held(&req->i915->drm.struct_mutex);
226
227	so = req->engine->render_state;
228	if (!so)
229		return 0;
230
231	/* Recreate the page after shrinking */
232	if (!so->vma->obj->mm.pages)
233		so->batch_offset = -1;
234
235	ret = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
236	if (ret)
237		return ret;
238
239	if (so->vma->node.start != so->batch_offset) {
240		ret = render_state_setup(so, req->i915);
241		if (ret)
242			goto err_unpin;
243	}
244
245	ret = req->engine->emit_bb_start(req,
246					 so->batch_offset, so->batch_size,
247					 I915_DISPATCH_SECURE);
248	if (ret)
249		goto err_unpin;
250
251	if (so->aux_size > 8) {
252		ret = req->engine->emit_bb_start(req,
253						 so->aux_offset, so->aux_size,
254						 I915_DISPATCH_SECURE);
255		if (ret)
256			goto err_unpin;
257	}
258
259	i915_vma_move_to_active(so->vma, req, 0);
260err_unpin:
261	i915_vma_unpin(so->vma);
262	return ret;
263}
264
265void i915_gem_render_state_fini(struct intel_engine_cs *engine)
266{
267	struct intel_render_state *so;
268	struct drm_i915_gem_object *obj;
269
270	so = fetch_and_zero(&engine->render_state);
271	if (!so)
272		return;
273
274	obj = so->vma->obj;
275
276	i915_vma_close(so->vma);
277	__i915_gem_object_release_unless_active(obj);
278
279	kfree(so);
280}