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1/*
2 * Copyright © 2011-2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28/*
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
35 *
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
46 *
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
51 *
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
63 *
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
73 *
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
80 *
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
85 *
86 */
87
88#include <drm/drmP.h>
89#include <drm/i915_drm.h>
90#include "i915_drv.h"
91#include "i915_trace.h"
92
93#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
94
95/* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
98 */
99#define GEN6_CONTEXT_ALIGN (64<<10)
100#define GEN7_CONTEXT_ALIGN 4096
101
102static size_t get_context_alignment(struct drm_i915_private *dev_priv)
103{
104 if (IS_GEN6(dev_priv))
105 return GEN6_CONTEXT_ALIGN;
106
107 return GEN7_CONTEXT_ALIGN;
108}
109
110static int get_context_size(struct drm_i915_private *dev_priv)
111{
112 int ret;
113 u32 reg;
114
115 switch (INTEL_GEN(dev_priv)) {
116 case 6:
117 reg = I915_READ(CXT_SIZE);
118 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
119 break;
120 case 7:
121 reg = I915_READ(GEN7_CXT_SIZE);
122 if (IS_HASWELL(dev_priv))
123 ret = HSW_CXT_TOTAL_SIZE;
124 else
125 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
126 break;
127 case 8:
128 ret = GEN8_CXT_TOTAL_SIZE;
129 break;
130 default:
131 BUG();
132 }
133
134 return ret;
135}
136
137void i915_gem_context_free(struct kref *ctx_ref)
138{
139 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
140 int i;
141
142 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
143 trace_i915_context_free(ctx);
144 GEM_BUG_ON(!ctx->closed);
145
146 i915_ppgtt_put(ctx->ppgtt);
147
148 for (i = 0; i < I915_NUM_ENGINES; i++) {
149 struct intel_context *ce = &ctx->engine[i];
150
151 if (!ce->state)
152 continue;
153
154 WARN_ON(ce->pin_count);
155 if (ce->ring)
156 intel_ring_free(ce->ring);
157
158 __i915_gem_object_release_unless_active(ce->state->obj);
159 }
160
161 kfree(ctx->name);
162 put_pid(ctx->pid);
163 list_del(&ctx->link);
164
165 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
166 kfree(ctx);
167}
168
169struct drm_i915_gem_object *
170i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
171{
172 struct drm_i915_gem_object *obj;
173 int ret;
174
175 lockdep_assert_held(&dev->struct_mutex);
176
177 obj = i915_gem_object_create(dev, size);
178 if (IS_ERR(obj))
179 return obj;
180
181 /*
182 * Try to make the context utilize L3 as well as LLC.
183 *
184 * On VLV we don't have L3 controls in the PTEs so we
185 * shouldn't touch the cache level, especially as that
186 * would make the object snooped which might have a
187 * negative performance impact.
188 *
189 * Snooping is required on non-llc platforms in execlist
190 * mode, but since all GGTT accesses use PAT entry 0 we
191 * get snooping anyway regardless of cache_level.
192 *
193 * This is only applicable for Ivy Bridge devices since
194 * later platforms don't have L3 control bits in the PTE.
195 */
196 if (IS_IVYBRIDGE(to_i915(dev))) {
197 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
198 /* Failure shouldn't ever happen this early */
199 if (WARN_ON(ret)) {
200 i915_gem_object_put(obj);
201 return ERR_PTR(ret);
202 }
203 }
204
205 return obj;
206}
207
208static void i915_ppgtt_close(struct i915_address_space *vm)
209{
210 struct list_head *phases[] = {
211 &vm->active_list,
212 &vm->inactive_list,
213 &vm->unbound_list,
214 NULL,
215 }, **phase;
216
217 GEM_BUG_ON(vm->closed);
218 vm->closed = true;
219
220 for (phase = phases; *phase; phase++) {
221 struct i915_vma *vma, *vn;
222
223 list_for_each_entry_safe(vma, vn, *phase, vm_link)
224 if (!i915_vma_is_closed(vma))
225 i915_vma_close(vma);
226 }
227}
228
229static void context_close(struct i915_gem_context *ctx)
230{
231 GEM_BUG_ON(ctx->closed);
232 ctx->closed = true;
233 if (ctx->ppgtt)
234 i915_ppgtt_close(&ctx->ppgtt->base);
235 ctx->file_priv = ERR_PTR(-EBADF);
236 i915_gem_context_put(ctx);
237}
238
239static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
240{
241 int ret;
242
243 ret = ida_simple_get(&dev_priv->context_hw_ida,
244 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
245 if (ret < 0) {
246 /* Contexts are only released when no longer active.
247 * Flush any pending retires to hopefully release some
248 * stale contexts and try again.
249 */
250 i915_gem_retire_requests(dev_priv);
251 ret = ida_simple_get(&dev_priv->context_hw_ida,
252 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
253 if (ret < 0)
254 return ret;
255 }
256
257 *out = ret;
258 return 0;
259}
260
261static struct i915_gem_context *
262__create_hw_context(struct drm_device *dev,
263 struct drm_i915_file_private *file_priv)
264{
265 struct drm_i915_private *dev_priv = to_i915(dev);
266 struct i915_gem_context *ctx;
267 int ret;
268
269 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
270 if (ctx == NULL)
271 return ERR_PTR(-ENOMEM);
272
273 ret = assign_hw_id(dev_priv, &ctx->hw_id);
274 if (ret) {
275 kfree(ctx);
276 return ERR_PTR(ret);
277 }
278
279 kref_init(&ctx->ref);
280 list_add_tail(&ctx->link, &dev_priv->context_list);
281 ctx->i915 = dev_priv;
282
283 ctx->ggtt_alignment = get_context_alignment(dev_priv);
284
285 if (dev_priv->hw_context_size) {
286 struct drm_i915_gem_object *obj;
287 struct i915_vma *vma;
288
289 obj = i915_gem_alloc_context_obj(dev,
290 dev_priv->hw_context_size);
291 if (IS_ERR(obj)) {
292 ret = PTR_ERR(obj);
293 goto err_out;
294 }
295
296 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
297 if (IS_ERR(vma)) {
298 i915_gem_object_put(obj);
299 ret = PTR_ERR(vma);
300 goto err_out;
301 }
302
303 ctx->engine[RCS].state = vma;
304 }
305
306 /* Default context will never have a file_priv */
307 ret = DEFAULT_CONTEXT_HANDLE;
308 if (file_priv) {
309 ret = idr_alloc(&file_priv->context_idr, ctx,
310 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
311 if (ret < 0)
312 goto err_out;
313 }
314 ctx->user_handle = ret;
315
316 ctx->file_priv = file_priv;
317 if (file_priv) {
318 ctx->pid = get_task_pid(current, PIDTYPE_PID);
319 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
320 current->comm,
321 pid_nr(ctx->pid),
322 ctx->user_handle);
323 if (!ctx->name) {
324 ret = -ENOMEM;
325 goto err_pid;
326 }
327 }
328
329 /* NB: Mark all slices as needing a remap so that when the context first
330 * loads it will restore whatever remap state already exists. If there
331 * is no remap info, it will be a NOP. */
332 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
333
334 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
335 ctx->ring_size = 4 * PAGE_SIZE;
336 ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
337 GEN8_CTX_ADDRESSING_MODE_SHIFT;
338 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
339
340 return ctx;
341
342err_pid:
343 put_pid(ctx->pid);
344 idr_remove(&file_priv->context_idr, ctx->user_handle);
345err_out:
346 context_close(ctx);
347 return ERR_PTR(ret);
348}
349
350/**
351 * The default context needs to exist per ring that uses contexts. It stores the
352 * context state of the GPU for applications that don't utilize HW contexts, as
353 * well as an idle case.
354 */
355static struct i915_gem_context *
356i915_gem_create_context(struct drm_device *dev,
357 struct drm_i915_file_private *file_priv)
358{
359 struct i915_gem_context *ctx;
360
361 lockdep_assert_held(&dev->struct_mutex);
362
363 ctx = __create_hw_context(dev, file_priv);
364 if (IS_ERR(ctx))
365 return ctx;
366
367 if (USES_FULL_PPGTT(dev)) {
368 struct i915_hw_ppgtt *ppgtt;
369
370 ppgtt = i915_ppgtt_create(to_i915(dev), file_priv, ctx->name);
371 if (IS_ERR(ppgtt)) {
372 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
373 PTR_ERR(ppgtt));
374 idr_remove(&file_priv->context_idr, ctx->user_handle);
375 context_close(ctx);
376 return ERR_CAST(ppgtt);
377 }
378
379 ctx->ppgtt = ppgtt;
380 }
381
382 trace_i915_context_create(ctx);
383
384 return ctx;
385}
386
387/**
388 * i915_gem_context_create_gvt - create a GVT GEM context
389 * @dev: drm device *
390 *
391 * This function is used to create a GVT specific GEM context.
392 *
393 * Returns:
394 * pointer to i915_gem_context on success, error pointer if failed
395 *
396 */
397struct i915_gem_context *
398i915_gem_context_create_gvt(struct drm_device *dev)
399{
400 struct i915_gem_context *ctx;
401 int ret;
402
403 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
404 return ERR_PTR(-ENODEV);
405
406 ret = i915_mutex_lock_interruptible(dev);
407 if (ret)
408 return ERR_PTR(ret);
409
410 ctx = i915_gem_create_context(dev, NULL);
411 if (IS_ERR(ctx))
412 goto out;
413
414 ctx->execlists_force_single_submission = true;
415 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
416out:
417 mutex_unlock(&dev->struct_mutex);
418 return ctx;
419}
420
421static void i915_gem_context_unpin(struct i915_gem_context *ctx,
422 struct intel_engine_cs *engine)
423{
424 if (i915.enable_execlists) {
425 intel_lr_context_unpin(ctx, engine);
426 } else {
427 struct intel_context *ce = &ctx->engine[engine->id];
428
429 if (ce->state)
430 i915_vma_unpin(ce->state);
431
432 i915_gem_context_put(ctx);
433 }
434}
435
436int i915_gem_context_init(struct drm_device *dev)
437{
438 struct drm_i915_private *dev_priv = to_i915(dev);
439 struct i915_gem_context *ctx;
440
441 /* Init should only be called once per module load. Eventually the
442 * restriction on the context_disabled check can be loosened. */
443 if (WARN_ON(dev_priv->kernel_context))
444 return 0;
445
446 if (intel_vgpu_active(dev_priv) &&
447 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
448 if (!i915.enable_execlists) {
449 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
450 return -EINVAL;
451 }
452 }
453
454 /* Using the simple ida interface, the max is limited by sizeof(int) */
455 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
456 ida_init(&dev_priv->context_hw_ida);
457
458 if (i915.enable_execlists) {
459 /* NB: intentionally left blank. We will allocate our own
460 * backing objects as we need them, thank you very much */
461 dev_priv->hw_context_size = 0;
462 } else if (HAS_HW_CONTEXTS(dev_priv)) {
463 dev_priv->hw_context_size =
464 round_up(get_context_size(dev_priv), 4096);
465 if (dev_priv->hw_context_size > (1<<20)) {
466 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
467 dev_priv->hw_context_size);
468 dev_priv->hw_context_size = 0;
469 }
470 }
471
472 ctx = i915_gem_create_context(dev, NULL);
473 if (IS_ERR(ctx)) {
474 DRM_ERROR("Failed to create default global context (error %ld)\n",
475 PTR_ERR(ctx));
476 return PTR_ERR(ctx);
477 }
478
479 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
480 dev_priv->kernel_context = ctx;
481
482 DRM_DEBUG_DRIVER("%s context support initialized\n",
483 i915.enable_execlists ? "LR" :
484 dev_priv->hw_context_size ? "HW" : "fake");
485 return 0;
486}
487
488void i915_gem_context_lost(struct drm_i915_private *dev_priv)
489{
490 struct intel_engine_cs *engine;
491 enum intel_engine_id id;
492
493 lockdep_assert_held(&dev_priv->drm.struct_mutex);
494
495 for_each_engine(engine, dev_priv, id) {
496 if (engine->last_context) {
497 i915_gem_context_unpin(engine->last_context, engine);
498 engine->last_context = NULL;
499 }
500 }
501
502 /* Force the GPU state to be restored on enabling */
503 if (!i915.enable_execlists) {
504 struct i915_gem_context *ctx;
505
506 list_for_each_entry(ctx, &dev_priv->context_list, link) {
507 if (!i915_gem_context_is_default(ctx))
508 continue;
509
510 for_each_engine(engine, dev_priv, id)
511 ctx->engine[engine->id].initialised = false;
512
513 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
514 }
515
516 for_each_engine(engine, dev_priv, id) {
517 struct intel_context *kce =
518 &dev_priv->kernel_context->engine[engine->id];
519
520 kce->initialised = true;
521 }
522 }
523}
524
525void i915_gem_context_fini(struct drm_device *dev)
526{
527 struct drm_i915_private *dev_priv = to_i915(dev);
528 struct i915_gem_context *dctx = dev_priv->kernel_context;
529
530 lockdep_assert_held(&dev->struct_mutex);
531
532 context_close(dctx);
533 dev_priv->kernel_context = NULL;
534
535 ida_destroy(&dev_priv->context_hw_ida);
536}
537
538static int context_idr_cleanup(int id, void *p, void *data)
539{
540 struct i915_gem_context *ctx = p;
541
542 context_close(ctx);
543 return 0;
544}
545
546int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
547{
548 struct drm_i915_file_private *file_priv = file->driver_priv;
549 struct i915_gem_context *ctx;
550
551 idr_init(&file_priv->context_idr);
552
553 mutex_lock(&dev->struct_mutex);
554 ctx = i915_gem_create_context(dev, file_priv);
555 mutex_unlock(&dev->struct_mutex);
556
557 if (IS_ERR(ctx)) {
558 idr_destroy(&file_priv->context_idr);
559 return PTR_ERR(ctx);
560 }
561
562 return 0;
563}
564
565void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
566{
567 struct drm_i915_file_private *file_priv = file->driver_priv;
568
569 lockdep_assert_held(&dev->struct_mutex);
570
571 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
572 idr_destroy(&file_priv->context_idr);
573}
574
575static inline int
576mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
577{
578 struct drm_i915_private *dev_priv = req->i915;
579 struct intel_ring *ring = req->ring;
580 struct intel_engine_cs *engine = req->engine;
581 enum intel_engine_id id;
582 u32 flags = hw_flags | MI_MM_SPACE_GTT;
583 const int num_rings =
584 /* Use an extended w/a on ivb+ if signalling from other rings */
585 i915.semaphores ?
586 INTEL_INFO(dev_priv)->num_rings - 1 :
587 0;
588 int len, ret;
589
590 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
591 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
592 * explicitly, so we rely on the value at ring init, stored in
593 * itlb_before_ctx_switch.
594 */
595 if (IS_GEN6(dev_priv)) {
596 ret = engine->emit_flush(req, EMIT_INVALIDATE);
597 if (ret)
598 return ret;
599 }
600
601 /* These flags are for resource streamer on HSW+ */
602 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
603 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
604 else if (INTEL_GEN(dev_priv) < 8)
605 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
606
607
608 len = 4;
609 if (INTEL_GEN(dev_priv) >= 7)
610 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
611
612 ret = intel_ring_begin(req, len);
613 if (ret)
614 return ret;
615
616 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
617 if (INTEL_GEN(dev_priv) >= 7) {
618 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
619 if (num_rings) {
620 struct intel_engine_cs *signaller;
621
622 intel_ring_emit(ring,
623 MI_LOAD_REGISTER_IMM(num_rings));
624 for_each_engine(signaller, dev_priv, id) {
625 if (signaller == engine)
626 continue;
627
628 intel_ring_emit_reg(ring,
629 RING_PSMI_CTL(signaller->mmio_base));
630 intel_ring_emit(ring,
631 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
632 }
633 }
634 }
635
636 intel_ring_emit(ring, MI_NOOP);
637 intel_ring_emit(ring, MI_SET_CONTEXT);
638 intel_ring_emit(ring,
639 i915_ggtt_offset(req->ctx->engine[RCS].state) | flags);
640 /*
641 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
642 * WaMiSetContext_Hang:snb,ivb,vlv
643 */
644 intel_ring_emit(ring, MI_NOOP);
645
646 if (INTEL_GEN(dev_priv) >= 7) {
647 if (num_rings) {
648 struct intel_engine_cs *signaller;
649 i915_reg_t last_reg = {}; /* keep gcc quiet */
650
651 intel_ring_emit(ring,
652 MI_LOAD_REGISTER_IMM(num_rings));
653 for_each_engine(signaller, dev_priv, id) {
654 if (signaller == engine)
655 continue;
656
657 last_reg = RING_PSMI_CTL(signaller->mmio_base);
658 intel_ring_emit_reg(ring, last_reg);
659 intel_ring_emit(ring,
660 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
661 }
662
663 /* Insert a delay before the next switch! */
664 intel_ring_emit(ring,
665 MI_STORE_REGISTER_MEM |
666 MI_SRM_LRM_GLOBAL_GTT);
667 intel_ring_emit_reg(ring, last_reg);
668 intel_ring_emit(ring,
669 i915_ggtt_offset(engine->scratch));
670 intel_ring_emit(ring, MI_NOOP);
671 }
672 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
673 }
674
675 intel_ring_advance(ring);
676
677 return ret;
678}
679
680static int remap_l3(struct drm_i915_gem_request *req, int slice)
681{
682 u32 *remap_info = req->i915->l3_parity.remap_info[slice];
683 struct intel_ring *ring = req->ring;
684 int i, ret;
685
686 if (!remap_info)
687 return 0;
688
689 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
690 if (ret)
691 return ret;
692
693 /*
694 * Note: We do not worry about the concurrent register cacheline hang
695 * here because no other code should access these registers other than
696 * at initialization time.
697 */
698 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
699 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
700 intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
701 intel_ring_emit(ring, remap_info[i]);
702 }
703 intel_ring_emit(ring, MI_NOOP);
704 intel_ring_advance(ring);
705
706 return 0;
707}
708
709static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
710 struct intel_engine_cs *engine,
711 struct i915_gem_context *to)
712{
713 if (to->remap_slice)
714 return false;
715
716 if (!to->engine[RCS].initialised)
717 return false;
718
719 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
720 return false;
721
722 return to == engine->last_context;
723}
724
725static bool
726needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
727 struct intel_engine_cs *engine,
728 struct i915_gem_context *to)
729{
730 if (!ppgtt)
731 return false;
732
733 /* Always load the ppgtt on first use */
734 if (!engine->last_context)
735 return true;
736
737 /* Same context without new entries, skip */
738 if (engine->last_context == to &&
739 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
740 return false;
741
742 if (engine->id != RCS)
743 return true;
744
745 if (INTEL_GEN(engine->i915) < 8)
746 return true;
747
748 return false;
749}
750
751static bool
752needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
753 struct i915_gem_context *to,
754 u32 hw_flags)
755{
756 if (!ppgtt)
757 return false;
758
759 if (!IS_GEN8(to->i915))
760 return false;
761
762 if (hw_flags & MI_RESTORE_INHIBIT)
763 return true;
764
765 return false;
766}
767
768struct i915_vma *
769i915_gem_context_pin_legacy(struct i915_gem_context *ctx,
770 unsigned int flags)
771{
772 struct i915_vma *vma = ctx->engine[RCS].state;
773 int ret;
774
775 /* Clear this page out of any CPU caches for coherent swap-in/out.
776 * We only want to do this on the first bind so that we do not stall
777 * on an active context (which by nature is already on the GPU).
778 */
779 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
780 ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
781 if (ret)
782 return ERR_PTR(ret);
783 }
784
785 ret = i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | flags);
786 if (ret)
787 return ERR_PTR(ret);
788
789 return vma;
790}
791
792static int do_rcs_switch(struct drm_i915_gem_request *req)
793{
794 struct i915_gem_context *to = req->ctx;
795 struct intel_engine_cs *engine = req->engine;
796 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
797 struct i915_vma *vma;
798 struct i915_gem_context *from;
799 u32 hw_flags;
800 int ret, i;
801
802 if (skip_rcs_switch(ppgtt, engine, to))
803 return 0;
804
805 /* Trying to pin first makes error handling easier. */
806 vma = i915_gem_context_pin_legacy(to, 0);
807 if (IS_ERR(vma))
808 return PTR_ERR(vma);
809
810 /*
811 * Pin can switch back to the default context if we end up calling into
812 * evict_everything - as a last ditch gtt defrag effort that also
813 * switches to the default context. Hence we need to reload from here.
814 *
815 * XXX: Doing so is painfully broken!
816 */
817 from = engine->last_context;
818
819 if (needs_pd_load_pre(ppgtt, engine, to)) {
820 /* Older GENs and non render rings still want the load first,
821 * "PP_DCLV followed by PP_DIR_BASE register through Load
822 * Register Immediate commands in Ring Buffer before submitting
823 * a context."*/
824 trace_switch_mm(engine, to);
825 ret = ppgtt->switch_mm(ppgtt, req);
826 if (ret)
827 goto err;
828 }
829
830 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
831 /* NB: If we inhibit the restore, the context is not allowed to
832 * die because future work may end up depending on valid address
833 * space. This means we must enforce that a page table load
834 * occur when this occurs. */
835 hw_flags = MI_RESTORE_INHIBIT;
836 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
837 hw_flags = MI_FORCE_RESTORE;
838 else
839 hw_flags = 0;
840
841 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
842 ret = mi_set_context(req, hw_flags);
843 if (ret)
844 goto err;
845 }
846
847 /* The backing object for the context is done after switching to the
848 * *next* context. Therefore we cannot retire the previous context until
849 * the next context has already started running. In fact, the below code
850 * is a bit suboptimal because the retiring can occur simply after the
851 * MI_SET_CONTEXT instead of when the next seqno has completed.
852 */
853 if (from != NULL) {
854 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
855 * whole damn pipeline, we don't need to explicitly mark the
856 * object dirty. The only exception is that the context must be
857 * correct in case the object gets swapped out. Ideally we'd be
858 * able to defer doing this until we know the object would be
859 * swapped, but there is no way to do that yet.
860 */
861 i915_vma_move_to_active(from->engine[RCS].state, req, 0);
862 /* state is kept alive until the next request */
863 i915_vma_unpin(from->engine[RCS].state);
864 i915_gem_context_put(from);
865 }
866 engine->last_context = i915_gem_context_get(to);
867
868 /* GEN8 does *not* require an explicit reload if the PDPs have been
869 * setup, and we do not wish to move them.
870 */
871 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
872 trace_switch_mm(engine, to);
873 ret = ppgtt->switch_mm(ppgtt, req);
874 /* The hardware context switch is emitted, but we haven't
875 * actually changed the state - so it's probably safe to bail
876 * here. Still, let the user know something dangerous has
877 * happened.
878 */
879 if (ret)
880 return ret;
881 }
882
883 if (ppgtt)
884 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
885
886 for (i = 0; i < MAX_L3_SLICES; i++) {
887 if (!(to->remap_slice & (1<<i)))
888 continue;
889
890 ret = remap_l3(req, i);
891 if (ret)
892 return ret;
893
894 to->remap_slice &= ~(1<<i);
895 }
896
897 if (!to->engine[RCS].initialised) {
898 if (engine->init_context) {
899 ret = engine->init_context(req);
900 if (ret)
901 return ret;
902 }
903 to->engine[RCS].initialised = true;
904 }
905
906 return 0;
907
908err:
909 i915_vma_unpin(vma);
910 return ret;
911}
912
913/**
914 * i915_switch_context() - perform a GPU context switch.
915 * @req: request for which we'll execute the context switch
916 *
917 * The context life cycle is simple. The context refcount is incremented and
918 * decremented by 1 and create and destroy. If the context is in use by the GPU,
919 * it will have a refcount > 1. This allows us to destroy the context abstract
920 * object while letting the normal object tracking destroy the backing BO.
921 *
922 * This function should not be used in execlists mode. Instead the context is
923 * switched by writing to the ELSP and requests keep a reference to their
924 * context.
925 */
926int i915_switch_context(struct drm_i915_gem_request *req)
927{
928 struct intel_engine_cs *engine = req->engine;
929
930 lockdep_assert_held(&req->i915->drm.struct_mutex);
931 if (i915.enable_execlists)
932 return 0;
933
934 if (!req->ctx->engine[engine->id].state) {
935 struct i915_gem_context *to = req->ctx;
936 struct i915_hw_ppgtt *ppgtt =
937 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
938
939 if (needs_pd_load_pre(ppgtt, engine, to)) {
940 int ret;
941
942 trace_switch_mm(engine, to);
943 ret = ppgtt->switch_mm(ppgtt, req);
944 if (ret)
945 return ret;
946
947 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
948 }
949
950 if (to != engine->last_context) {
951 if (engine->last_context)
952 i915_gem_context_put(engine->last_context);
953 engine->last_context = i915_gem_context_get(to);
954 }
955
956 return 0;
957 }
958
959 return do_rcs_switch(req);
960}
961
962int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
963{
964 struct intel_engine_cs *engine;
965 struct i915_gem_timeline *timeline;
966 enum intel_engine_id id;
967
968 lockdep_assert_held(&dev_priv->drm.struct_mutex);
969
970 for_each_engine(engine, dev_priv, id) {
971 struct drm_i915_gem_request *req;
972 int ret;
973
974 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
975 if (IS_ERR(req))
976 return PTR_ERR(req);
977
978 /* Queue this switch after all other activity */
979 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
980 struct drm_i915_gem_request *prev;
981 struct intel_timeline *tl;
982
983 tl = &timeline->engine[engine->id];
984 prev = i915_gem_active_raw(&tl->last_request,
985 &dev_priv->drm.struct_mutex);
986 if (prev)
987 i915_sw_fence_await_sw_fence_gfp(&req->submit,
988 &prev->submit,
989 GFP_KERNEL);
990 }
991
992 ret = i915_switch_context(req);
993 i915_add_request_no_flush(req);
994 if (ret)
995 return ret;
996 }
997
998 return 0;
999}
1000
1001static bool contexts_enabled(struct drm_device *dev)
1002{
1003 return i915.enable_execlists || to_i915(dev)->hw_context_size;
1004}
1005
1006int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file)
1008{
1009 struct drm_i915_gem_context_create *args = data;
1010 struct drm_i915_file_private *file_priv = file->driver_priv;
1011 struct i915_gem_context *ctx;
1012 int ret;
1013
1014 if (!contexts_enabled(dev))
1015 return -ENODEV;
1016
1017 if (args->pad != 0)
1018 return -EINVAL;
1019
1020 ret = i915_mutex_lock_interruptible(dev);
1021 if (ret)
1022 return ret;
1023
1024 ctx = i915_gem_create_context(dev, file_priv);
1025 mutex_unlock(&dev->struct_mutex);
1026 if (IS_ERR(ctx))
1027 return PTR_ERR(ctx);
1028
1029 args->ctx_id = ctx->user_handle;
1030 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
1031
1032 return 0;
1033}
1034
1035int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1036 struct drm_file *file)
1037{
1038 struct drm_i915_gem_context_destroy *args = data;
1039 struct drm_i915_file_private *file_priv = file->driver_priv;
1040 struct i915_gem_context *ctx;
1041 int ret;
1042
1043 if (args->pad != 0)
1044 return -EINVAL;
1045
1046 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1047 return -ENOENT;
1048
1049 ret = i915_mutex_lock_interruptible(dev);
1050 if (ret)
1051 return ret;
1052
1053 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1054 if (IS_ERR(ctx)) {
1055 mutex_unlock(&dev->struct_mutex);
1056 return PTR_ERR(ctx);
1057 }
1058
1059 idr_remove(&file_priv->context_idr, ctx->user_handle);
1060 context_close(ctx);
1061 mutex_unlock(&dev->struct_mutex);
1062
1063 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
1064 return 0;
1065}
1066
1067int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *file)
1069{
1070 struct drm_i915_file_private *file_priv = file->driver_priv;
1071 struct drm_i915_gem_context_param *args = data;
1072 struct i915_gem_context *ctx;
1073 int ret;
1074
1075 ret = i915_mutex_lock_interruptible(dev);
1076 if (ret)
1077 return ret;
1078
1079 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1080 if (IS_ERR(ctx)) {
1081 mutex_unlock(&dev->struct_mutex);
1082 return PTR_ERR(ctx);
1083 }
1084
1085 args->size = 0;
1086 switch (args->param) {
1087 case I915_CONTEXT_PARAM_BAN_PERIOD:
1088 args->value = ctx->hang_stats.ban_period_seconds;
1089 break;
1090 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1091 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1092 break;
1093 case I915_CONTEXT_PARAM_GTT_SIZE:
1094 if (ctx->ppgtt)
1095 args->value = ctx->ppgtt->base.total;
1096 else if (to_i915(dev)->mm.aliasing_ppgtt)
1097 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1098 else
1099 args->value = to_i915(dev)->ggtt.base.total;
1100 break;
1101 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1102 args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
1103 break;
1104 default:
1105 ret = -EINVAL;
1106 break;
1107 }
1108 mutex_unlock(&dev->struct_mutex);
1109
1110 return ret;
1111}
1112
1113int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *file)
1115{
1116 struct drm_i915_file_private *file_priv = file->driver_priv;
1117 struct drm_i915_gem_context_param *args = data;
1118 struct i915_gem_context *ctx;
1119 int ret;
1120
1121 ret = i915_mutex_lock_interruptible(dev);
1122 if (ret)
1123 return ret;
1124
1125 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1126 if (IS_ERR(ctx)) {
1127 mutex_unlock(&dev->struct_mutex);
1128 return PTR_ERR(ctx);
1129 }
1130
1131 switch (args->param) {
1132 case I915_CONTEXT_PARAM_BAN_PERIOD:
1133 if (args->size)
1134 ret = -EINVAL;
1135 else if (args->value < ctx->hang_stats.ban_period_seconds &&
1136 !capable(CAP_SYS_ADMIN))
1137 ret = -EPERM;
1138 else
1139 ctx->hang_stats.ban_period_seconds = args->value;
1140 break;
1141 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1142 if (args->size) {
1143 ret = -EINVAL;
1144 } else {
1145 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1146 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1147 }
1148 break;
1149 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1150 if (args->size) {
1151 ret = -EINVAL;
1152 } else {
1153 if (args->value)
1154 ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
1155 else
1156 ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
1157 }
1158 break;
1159 default:
1160 ret = -EINVAL;
1161 break;
1162 }
1163 mutex_unlock(&dev->struct_mutex);
1164
1165 return ret;
1166}
1167
1168int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1169 void *data, struct drm_file *file)
1170{
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct drm_i915_reset_stats *args = data;
1173 struct i915_ctx_hang_stats *hs;
1174 struct i915_gem_context *ctx;
1175 int ret;
1176
1177 if (args->flags || args->pad)
1178 return -EINVAL;
1179
1180 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1181 return -EPERM;
1182
1183 ret = i915_mutex_lock_interruptible(dev);
1184 if (ret)
1185 return ret;
1186
1187 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1188 if (IS_ERR(ctx)) {
1189 mutex_unlock(&dev->struct_mutex);
1190 return PTR_ERR(ctx);
1191 }
1192 hs = &ctx->hang_stats;
1193
1194 if (capable(CAP_SYS_ADMIN))
1195 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1196 else
1197 args->reset_count = 0;
1198
1199 args->batch_active = hs->batch_active;
1200 args->batch_pending = hs->batch_pending;
1201
1202 mutex_unlock(&dev->struct_mutex);
1203
1204 return 0;
1205}