1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 *
 23 * Authors:
 24 *    Kevin Tian <kevin.tian@intel.com>
 25 *    Zhi Wang <zhi.a.wang@intel.com>
 26 *
 27 * Contributors:
 28 *    Min he <min.he@intel.com>
 29 *
 30 */
 31
 32#ifndef _GVT_INTERRUPT_H_
 33#define _GVT_INTERRUPT_H_
 34
 35enum intel_gvt_event_type {
 36	RCS_MI_USER_INTERRUPT = 0,
 37	RCS_DEBUG,
 38	RCS_MMIO_SYNC_FLUSH,
 39	RCS_CMD_STREAMER_ERR,
 40	RCS_PIPE_CONTROL,
 41	RCS_L3_PARITY_ERR,
 42	RCS_WATCHDOG_EXCEEDED,
 43	RCS_PAGE_DIRECTORY_FAULT,
 44	RCS_AS_CONTEXT_SWITCH,
 45	RCS_MONITOR_BUFF_HALF_FULL,
 46
 47	VCS_MI_USER_INTERRUPT,
 48	VCS_MMIO_SYNC_FLUSH,
 49	VCS_CMD_STREAMER_ERR,
 50	VCS_MI_FLUSH_DW,
 51	VCS_WATCHDOG_EXCEEDED,
 52	VCS_PAGE_DIRECTORY_FAULT,
 53	VCS_AS_CONTEXT_SWITCH,
 54
 55	VCS2_MI_USER_INTERRUPT,
 56	VCS2_MI_FLUSH_DW,
 57	VCS2_AS_CONTEXT_SWITCH,
 58
 59	BCS_MI_USER_INTERRUPT,
 60	BCS_MMIO_SYNC_FLUSH,
 61	BCS_CMD_STREAMER_ERR,
 62	BCS_MI_FLUSH_DW,
 63	BCS_PAGE_DIRECTORY_FAULT,
 64	BCS_AS_CONTEXT_SWITCH,
 65
 66	VECS_MI_USER_INTERRUPT,
 67	VECS_MI_FLUSH_DW,
 68	VECS_AS_CONTEXT_SWITCH,
 69
 70	PIPE_A_FIFO_UNDERRUN,
 71	PIPE_B_FIFO_UNDERRUN,
 72	PIPE_A_CRC_ERR,
 73	PIPE_B_CRC_ERR,
 74	PIPE_A_CRC_DONE,
 75	PIPE_B_CRC_DONE,
 76	PIPE_A_ODD_FIELD,
 77	PIPE_B_ODD_FIELD,
 78	PIPE_A_EVEN_FIELD,
 79	PIPE_B_EVEN_FIELD,
 80	PIPE_A_LINE_COMPARE,
 81	PIPE_B_LINE_COMPARE,
 82	PIPE_C_LINE_COMPARE,
 83	PIPE_A_VBLANK,
 84	PIPE_B_VBLANK,
 85	PIPE_C_VBLANK,
 86	PIPE_A_VSYNC,
 87	PIPE_B_VSYNC,
 88	PIPE_C_VSYNC,
 89	PRIMARY_A_FLIP_DONE,
 90	PRIMARY_B_FLIP_DONE,
 91	PRIMARY_C_FLIP_DONE,
 92	SPRITE_A_FLIP_DONE,
 93	SPRITE_B_FLIP_DONE,
 94	SPRITE_C_FLIP_DONE,
 95
 96	PCU_THERMAL,
 97	PCU_PCODE2DRIVER_MAILBOX,
 98
 99	DPST_PHASE_IN,
100	DPST_HISTOGRAM,
101	GSE,
102	DP_A_HOTPLUG,
103	AUX_CHANNEL_A,
104	PERF_COUNTER,
105	POISON,
106	GTT_FAULT,
107	ERROR_INTERRUPT_COMBINED,
108
109	FDI_RX_INTERRUPTS_TRANSCODER_A,
110	AUDIO_CP_CHANGE_TRANSCODER_A,
111	AUDIO_CP_REQUEST_TRANSCODER_A,
112	FDI_RX_INTERRUPTS_TRANSCODER_B,
113	AUDIO_CP_CHANGE_TRANSCODER_B,
114	AUDIO_CP_REQUEST_TRANSCODER_B,
115	FDI_RX_INTERRUPTS_TRANSCODER_C,
116	AUDIO_CP_CHANGE_TRANSCODER_C,
117	AUDIO_CP_REQUEST_TRANSCODER_C,
118	ERR_AND_DBG,
119	GMBUS,
120	SDVO_B_HOTPLUG,
121	CRT_HOTPLUG,
122	DP_B_HOTPLUG,
123	DP_C_HOTPLUG,
124	DP_D_HOTPLUG,
125	AUX_CHANNEL_B,
126	AUX_CHANNEL_C,
127	AUX_CHANNEL_D,
128	AUDIO_POWER_STATE_CHANGE_B,
129	AUDIO_POWER_STATE_CHANGE_C,
130	AUDIO_POWER_STATE_CHANGE_D,
131
132	INTEL_GVT_EVENT_RESERVED,
133	INTEL_GVT_EVENT_MAX,
134};
135
136struct intel_gvt_irq;
137struct intel_gvt;
138
139typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq,
140	enum intel_gvt_event_type event, struct intel_vgpu *vgpu);
141
142struct intel_gvt_irq_ops {
143	void (*init_irq)(struct intel_gvt_irq *irq);
144	void (*check_pending_irq)(struct intel_vgpu *vgpu);
145};
146
147/* the list of physical interrupt control register groups */
148enum intel_gvt_irq_type {
149	INTEL_GVT_IRQ_INFO_GT,
150	INTEL_GVT_IRQ_INFO_DPY,
151	INTEL_GVT_IRQ_INFO_PCH,
152	INTEL_GVT_IRQ_INFO_PM,
153
154	INTEL_GVT_IRQ_INFO_MASTER,
155	INTEL_GVT_IRQ_INFO_GT0,
156	INTEL_GVT_IRQ_INFO_GT1,
157	INTEL_GVT_IRQ_INFO_GT2,
158	INTEL_GVT_IRQ_INFO_GT3,
159	INTEL_GVT_IRQ_INFO_DE_PIPE_A,
160	INTEL_GVT_IRQ_INFO_DE_PIPE_B,
161	INTEL_GVT_IRQ_INFO_DE_PIPE_C,
162	INTEL_GVT_IRQ_INFO_DE_PORT,
163	INTEL_GVT_IRQ_INFO_DE_MISC,
164	INTEL_GVT_IRQ_INFO_AUD,
165	INTEL_GVT_IRQ_INFO_PCU,
166
167	INTEL_GVT_IRQ_INFO_MAX,
168};
169
170#define INTEL_GVT_IRQ_BITWIDTH	32
171
172/* device specific interrupt bit definitions */
173struct intel_gvt_irq_info {
174	char *name;
175	i915_reg_t reg_base;
176	enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
177	unsigned long warned;
178	int group;
179	DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
180	bool has_upstream_irq;
181};
182
183/* per-event information */
184struct intel_gvt_event_info {
185	int bit;				/* map to register bit */
186	int policy;				/* forwarding policy */
187	struct intel_gvt_irq_info *info;	/* register info */
188	gvt_event_virt_handler_t v_handler;	/* for v_event */
189};
190
191struct intel_gvt_irq_map {
192	int up_irq_group;
193	int up_irq_bit;
194	int down_irq_group;
195	u32 down_irq_bitmask;
196};
197
198struct intel_gvt_vblank_timer {
199	struct hrtimer timer;
200	u64 period;
201};
202
203/* structure containing device specific IRQ state */
204struct intel_gvt_irq {
205	struct intel_gvt_irq_ops *ops;
206	struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
207	DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
208	struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
209	DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
210	struct intel_gvt_irq_map *irq_map;
211	struct intel_gvt_vblank_timer vblank_timer;
212};
213
214int intel_gvt_init_irq(struct intel_gvt *gvt);
215void intel_gvt_clean_irq(struct intel_gvt *gvt);
216
217void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
218	enum intel_gvt_event_type event);
219
220int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
221	void *p_data, unsigned int bytes);
222int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
223	unsigned int reg, void *p_data, unsigned int bytes);
224int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
225	unsigned int reg, void *p_data, unsigned int bytes);
226int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
227	unsigned int reg, void *p_data, unsigned int bytes);
228
229int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
230int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
231int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);
232
233#endif /* _GVT_INTERRUPT_H_ */