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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _AMD_POWERPLAY_H_
24#define _AMD_POWERPLAY_H_
25
26#include <linux/seq_file.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include "amd_shared.h"
30#include "cgs_common.h"
31
32extern int amdgpu_dpm;
33
34enum amd_pp_sensors {
35 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
36 AMDGPU_PP_SENSOR_VDDNB,
37 AMDGPU_PP_SENSOR_VDDGFX,
38 AMDGPU_PP_SENSOR_UVD_VCLK,
39 AMDGPU_PP_SENSOR_UVD_DCLK,
40 AMDGPU_PP_SENSOR_VCE_ECCLK,
41 AMDGPU_PP_SENSOR_GPU_LOAD,
42 AMDGPU_PP_SENSOR_GFX_MCLK,
43 AMDGPU_PP_SENSOR_GPU_TEMP,
44 AMDGPU_PP_SENSOR_VCE_POWER,
45 AMDGPU_PP_SENSOR_UVD_POWER,
46};
47
48enum amd_pp_event {
49 AMD_PP_EVENT_INITIALIZE = 0,
50 AMD_PP_EVENT_UNINITIALIZE,
51 AMD_PP_EVENT_POWER_SOURCE_CHANGE,
52 AMD_PP_EVENT_SUSPEND,
53 AMD_PP_EVENT_RESUME,
54 AMD_PP_EVENT_ENTER_REST_STATE,
55 AMD_PP_EVENT_EXIT_REST_STATE,
56 AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
57 AMD_PP_EVENT_THERMAL_NOTIFICATION,
58 AMD_PP_EVENT_VBIOS_NOTIFICATION,
59 AMD_PP_EVENT_ENTER_THERMAL_STATE,
60 AMD_PP_EVENT_EXIT_THERMAL_STATE,
61 AMD_PP_EVENT_ENTER_FORCED_STATE,
62 AMD_PP_EVENT_EXIT_FORCED_STATE,
63 AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
64 AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
65 AMD_PP_EVENT_ENTER_SCREEN_SAVER,
66 AMD_PP_EVENT_EXIT_SCREEN_SAVER,
67 AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
68 AMD_PP_EVENT_VPU_RECOVERY_END,
69 AMD_PP_EVENT_ENABLE_POWER_PLAY,
70 AMD_PP_EVENT_DISABLE_POWER_PLAY,
71 AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
72 AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
73 AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
74 AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
75 AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
76 AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
77 AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
78 AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
79 AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
80 AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
81 AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
82 AMD_PP_EVENT_ENABLE_CGPG,
83 AMD_PP_EVENT_DISABLE_CGPG,
84 AMD_PP_EVENT_ENTER_TEXT_MODE,
85 AMD_PP_EVENT_EXIT_TEXT_MODE,
86 AMD_PP_EVENT_VIDEO_START,
87 AMD_PP_EVENT_VIDEO_STOP,
88 AMD_PP_EVENT_ENABLE_USER_STATE,
89 AMD_PP_EVENT_DISABLE_USER_STATE,
90 AMD_PP_EVENT_READJUST_POWER_STATE,
91 AMD_PP_EVENT_START_INACTIVITY,
92 AMD_PP_EVENT_STOP_INACTIVITY,
93 AMD_PP_EVENT_LINKED_ADAPTERS_READY,
94 AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
95 AMD_PP_EVENT_COMPLETE_INIT,
96 AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
97 AMD_PP_EVENT_BACKLIGHT_CHANGED,
98 AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
99 AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
100 AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
101 AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
102 AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
103 AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
104 AMD_PP_EVENT_SCREEN_ON,
105 AMD_PP_EVENT_SCREEN_OFF,
106 AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
107 AMD_PP_EVENT_ENTER_ULP_STATE,
108 AMD_PP_EVENT_EXIT_ULP_STATE,
109 AMD_PP_EVENT_REGISTER_IP_STATE,
110 AMD_PP_EVENT_UNREGISTER_IP_STATE,
111 AMD_PP_EVENT_ENTER_MGPU_MODE,
112 AMD_PP_EVENT_EXIT_MGPU_MODE,
113 AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
114 AMD_PP_EVENT_PRE_SUSPEND,
115 AMD_PP_EVENT_PRE_RESUME,
116 AMD_PP_EVENT_ENTER_BACOS,
117 AMD_PP_EVENT_EXIT_BACOS,
118 AMD_PP_EVENT_RESUME_BACO,
119 AMD_PP_EVENT_RESET_BACO,
120 AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
121 AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
122 AMD_PP_EVENT_START_COMPUTE_APPLICATION,
123 AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
124 AMD_PP_EVENT_REDUCE_POWER_LIMIT,
125 AMD_PP_EVENT_ENTER_FRAME_LOCK,
126 AMD_PP_EVENT_EXIT_FRAME_LOOCK,
127 AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
128 AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
129 AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
130 AMD_PP_EVENT_HIBERNATE,
131 AMD_PP_EVENT_CONNECTED_STANDBY,
132 AMD_PP_EVENT_ENTER_SELF_REFRESH,
133 AMD_PP_EVENT_EXIT_SELF_REFRESH,
134 AMD_PP_EVENT_START_AVFS_BTC,
135 AMD_PP_EVENT_MAX
136};
137
138enum amd_dpm_forced_level {
139 AMD_DPM_FORCED_LEVEL_AUTO = 0,
140 AMD_DPM_FORCED_LEVEL_LOW = 1,
141 AMD_DPM_FORCED_LEVEL_HIGH = 2,
142 AMD_DPM_FORCED_LEVEL_MANUAL = 3,
143};
144
145struct amd_pp_init {
146 struct cgs_device *device;
147 uint32_t chip_family;
148 uint32_t chip_id;
149};
150
151enum amd_pp_display_config_type{
152 AMD_PP_DisplayConfigType_None = 0,
153 AMD_PP_DisplayConfigType_DP54 ,
154 AMD_PP_DisplayConfigType_DP432 ,
155 AMD_PP_DisplayConfigType_DP324 ,
156 AMD_PP_DisplayConfigType_DP27,
157 AMD_PP_DisplayConfigType_DP243,
158 AMD_PP_DisplayConfigType_DP216,
159 AMD_PP_DisplayConfigType_DP162,
160 AMD_PP_DisplayConfigType_HDMI6G ,
161 AMD_PP_DisplayConfigType_HDMI297 ,
162 AMD_PP_DisplayConfigType_HDMI162,
163 AMD_PP_DisplayConfigType_LVDS,
164 AMD_PP_DisplayConfigType_DVI,
165 AMD_PP_DisplayConfigType_WIRELESS,
166 AMD_PP_DisplayConfigType_VGA
167};
168
169struct single_display_configuration
170{
171 uint32_t controller_index;
172 uint32_t controller_id;
173 uint32_t signal_type;
174 uint32_t display_state;
175 /* phy id for the primary internal transmitter */
176 uint8_t primary_transmitter_phyi_d;
177 /* bitmap with the active lanes */
178 uint8_t primary_transmitter_active_lanemap;
179 /* phy id for the secondary internal transmitter (for dual-link dvi) */
180 uint8_t secondary_transmitter_phy_id;
181 /* bitmap with the active lanes */
182 uint8_t secondary_transmitter_active_lanemap;
183 /* misc phy settings for SMU. */
184 uint32_t config_flags;
185 uint32_t display_type;
186 uint32_t view_resolution_cx;
187 uint32_t view_resolution_cy;
188 enum amd_pp_display_config_type displayconfigtype;
189 uint32_t vertical_refresh; /* for active display */
190};
191
192#define MAX_NUM_DISPLAY 32
193
194struct amd_pp_display_configuration {
195 bool nb_pstate_switch_disable;/* controls NB PState switch */
196 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
197 bool cpu_pstate_disable;
198 uint32_t cpu_pstate_separation_time;
199
200 uint32_t num_display; /* total number of display*/
201 uint32_t num_path_including_non_display;
202 uint32_t crossfire_display_index;
203 uint32_t min_mem_set_clock;
204 uint32_t min_core_set_clock;
205 /* unit 10KHz x bit*/
206 uint32_t min_bus_bandwidth;
207 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
208 uint32_t min_core_set_clock_in_sr;
209
210 struct single_display_configuration displays[MAX_NUM_DISPLAY];
211
212 uint32_t vrefresh; /* for active display*/
213
214 uint32_t min_vblank_time; /* for active display*/
215 bool multi_monitor_in_sync;
216 /* Controller Index of primary display - used in MCLK SMC switching hang
217 * SW Workaround*/
218 uint32_t crtc_index;
219 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
220 uint32_t line_time_in_us;
221 bool invalid_vblank_time;
222
223 uint32_t display_clk;
224 /*
225 * for given display configuration if multimonitormnsync == false then
226 * Memory clock DPMS with this latency or below is allowed, DPMS with
227 * higher latency not allowed.
228 */
229 uint32_t dce_tolerable_mclk_in_active_latency;
230};
231
232struct amd_pp_simple_clock_info {
233 uint32_t engine_max_clock;
234 uint32_t memory_max_clock;
235 uint32_t level;
236};
237
238enum PP_DAL_POWERLEVEL {
239 PP_DAL_POWERLEVEL_INVALID = 0,
240 PP_DAL_POWERLEVEL_ULTRALOW,
241 PP_DAL_POWERLEVEL_LOW,
242 PP_DAL_POWERLEVEL_NOMINAL,
243 PP_DAL_POWERLEVEL_PERFORMANCE,
244
245 PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
246 PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
247 PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
248 PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
249 PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
250 PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
251 PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
252 PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
253};
254
255struct amd_pp_clock_info {
256 uint32_t min_engine_clock;
257 uint32_t max_engine_clock;
258 uint32_t min_memory_clock;
259 uint32_t max_memory_clock;
260 uint32_t min_bus_bandwidth;
261 uint32_t max_bus_bandwidth;
262 uint32_t max_engine_clock_in_sr;
263 uint32_t min_engine_clock_in_sr;
264 enum PP_DAL_POWERLEVEL max_clocks_state;
265};
266
267enum amd_pp_clock_type {
268 amd_pp_disp_clock = 1,
269 amd_pp_sys_clock,
270 amd_pp_mem_clock
271};
272
273#define MAX_NUM_CLOCKS 16
274
275struct amd_pp_clocks {
276 uint32_t count;
277 uint32_t clock[MAX_NUM_CLOCKS];
278 uint32_t latency[MAX_NUM_CLOCKS];
279};
280
281
282enum {
283 PP_GROUP_UNKNOWN = 0,
284 PP_GROUP_GFX = 1,
285 PP_GROUP_SYS,
286 PP_GROUP_MAX
287};
288
289enum pp_clock_type {
290 PP_SCLK,
291 PP_MCLK,
292 PP_PCIE,
293};
294
295struct pp_states_info {
296 uint32_t nums;
297 uint32_t states[16];
298};
299
300#define PP_GROUP_MASK 0xF0000000
301#define PP_GROUP_SHIFT 28
302
303#define PP_BLOCK_MASK 0x0FFFFF00
304#define PP_BLOCK_SHIFT 8
305
306#define PP_BLOCK_GFX_CG 0x01
307#define PP_BLOCK_GFX_MG 0x02
308#define PP_BLOCK_GFX_3D 0x04
309#define PP_BLOCK_GFX_RLC 0x08
310#define PP_BLOCK_GFX_CP 0x10
311#define PP_BLOCK_SYS_BIF 0x01
312#define PP_BLOCK_SYS_MC 0x02
313#define PP_BLOCK_SYS_ROM 0x04
314#define PP_BLOCK_SYS_DRM 0x08
315#define PP_BLOCK_SYS_HDP 0x10
316#define PP_BLOCK_SYS_SDMA 0x20
317
318#define PP_STATE_MASK 0x0000000F
319#define PP_STATE_SHIFT 0
320#define PP_STATE_SUPPORT_MASK 0x000000F0
321#define PP_STATE_SUPPORT_SHIFT 0
322
323#define PP_STATE_CG 0x01
324#define PP_STATE_LS 0x02
325#define PP_STATE_DS 0x04
326#define PP_STATE_SD 0x08
327#define PP_STATE_SUPPORT_CG 0x10
328#define PP_STATE_SUPPORT_LS 0x20
329#define PP_STATE_SUPPORT_DS 0x40
330#define PP_STATE_SUPPORT_SD 0x80
331
332#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
333 block << PP_BLOCK_SHIFT |\
334 support << PP_STATE_SUPPORT_SHIFT |\
335 state << PP_STATE_SHIFT)
336
337struct amd_powerplay_funcs {
338 int (*get_temperature)(void *handle);
339 int (*load_firmware)(void *handle);
340 int (*wait_for_fw_loading_complete)(void *handle);
341 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
342 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
343 enum amd_pm_state_type (*get_current_power_state)(void *handle);
344 int (*get_sclk)(void *handle, bool low);
345 int (*get_mclk)(void *handle, bool low);
346 int (*powergate_vce)(void *handle, bool gate);
347 int (*powergate_uvd)(void *handle, bool gate);
348 int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
349 void *input, void *output);
350 int (*set_fan_control_mode)(void *handle, uint32_t mode);
351 int (*get_fan_control_mode)(void *handle);
352 int (*set_fan_speed_percent)(void *handle, uint32_t percent);
353 int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
354 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
355 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
356 int (*get_pp_table)(void *handle, char **table);
357 int (*set_pp_table)(void *handle, const char *buf, size_t size);
358 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
359 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
360 int (*get_sclk_od)(void *handle);
361 int (*set_sclk_od)(void *handle, uint32_t value);
362 int (*get_mclk_od)(void *handle);
363 int (*set_mclk_od)(void *handle, uint32_t value);
364 int (*read_sensor)(void *handle, int idx, int32_t *value);
365 struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
366};
367
368struct amd_powerplay {
369 void *pp_handle;
370 const struct amd_ip_funcs *ip_funcs;
371 const struct amd_powerplay_funcs *pp_funcs;
372};
373
374int amd_powerplay_init(struct amd_pp_init *pp_init,
375 struct amd_powerplay *amd_pp);
376
377int amd_powerplay_fini(void *handle);
378
379int amd_powerplay_reset(void *handle);
380
381int amd_powerplay_display_configuration_change(void *handle,
382 const struct amd_pp_display_configuration *input);
383
384int amd_powerplay_get_display_power_level(void *handle,
385 struct amd_pp_simple_clock_info *output);
386
387int amd_powerplay_get_current_clocks(void *handle,
388 struct amd_pp_clock_info *output);
389
390int amd_powerplay_get_clock_by_type(void *handle,
391 enum amd_pp_clock_type type,
392 struct amd_pp_clocks *clocks);
393
394int amd_powerplay_get_display_mode_validation_clocks(void *handle,
395 struct amd_pp_simple_clock_info *output);
396
397int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
398
399#endif /* _AMD_POWERPLAY_H_ */