1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef __KFD_TOPOLOGY_H__
 24#define __KFD_TOPOLOGY_H__
 25
 26#include <linux/types.h>
 27#include <linux/list.h>
 28#include "kfd_priv.h"
 29
 30#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
 31
 32#define HSA_CAP_HOT_PLUGGABLE			0x00000001
 33#define HSA_CAP_ATS_PRESENT			0x00000002
 34#define HSA_CAP_SHARED_WITH_GRAPHICS		0x00000004
 35#define HSA_CAP_QUEUE_SIZE_POW2			0x00000008
 36#define HSA_CAP_QUEUE_SIZE_32BIT		0x00000010
 37#define HSA_CAP_QUEUE_IDLE_EVENT		0x00000020
 38#define HSA_CAP_VA_LIMIT			0x00000040
 39#define HSA_CAP_WATCH_POINTS_SUPPORTED		0x00000080
 40#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK	0x00000f00
 41#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT	8
 42#define HSA_CAP_RESERVED			0xfffff000
 43#define HSA_CAP_DOORBELL_PACKET_TYPE		0x00001000
 44
 45struct kfd_node_properties {
 46	uint32_t cpu_cores_count;
 47	uint32_t simd_count;
 48	uint32_t mem_banks_count;
 49	uint32_t caches_count;
 50	uint32_t io_links_count;
 51	uint32_t cpu_core_id_base;
 52	uint32_t simd_id_base;
 53	uint32_t capability;
 54	uint32_t max_waves_per_simd;
 55	uint32_t lds_size_in_kb;
 56	uint32_t gds_size_in_kb;
 57	uint32_t wave_front_size;
 58	uint32_t array_count;
 59	uint32_t simd_arrays_per_engine;
 60	uint32_t cu_per_simd_array;
 61	uint32_t simd_per_cu;
 62	uint32_t max_slots_scratch_cu;
 63	uint32_t engine_id;
 64	uint32_t vendor_id;
 65	uint32_t device_id;
 66	uint32_t location_id;
 67	uint32_t max_engine_clk_fcompute;
 68	uint32_t max_engine_clk_ccompute;
 69	uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
 70};
 71
 72#define HSA_MEM_HEAP_TYPE_SYSTEM	0
 73#define HSA_MEM_HEAP_TYPE_FB_PUBLIC	1
 74#define HSA_MEM_HEAP_TYPE_FB_PRIVATE	2
 75#define HSA_MEM_HEAP_TYPE_GPU_GDS	3
 76#define HSA_MEM_HEAP_TYPE_GPU_LDS	4
 77#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH	5
 78
 79#define HSA_MEM_FLAGS_HOT_PLUGGABLE	0x00000001
 80#define HSA_MEM_FLAGS_NON_VOLATILE	0x00000002
 81#define HSA_MEM_FLAGS_RESERVED		0xfffffffc
 82
 83struct kfd_mem_properties {
 84	struct list_head	list;
 85	uint32_t		heap_type;
 86	uint64_t		size_in_bytes;
 87	uint32_t		flags;
 88	uint32_t		width;
 89	uint32_t		mem_clk_max;
 90	struct kobject		*kobj;
 91	struct attribute	attr;
 92};
 93
 94#define KFD_TOPOLOGY_CPU_SIBLINGS 256
 95
 96#define HSA_CACHE_TYPE_DATA		0x00000001
 97#define HSA_CACHE_TYPE_INSTRUCTION	0x00000002
 98#define HSA_CACHE_TYPE_CPU		0x00000004
 99#define HSA_CACHE_TYPE_HSACU		0x00000008
100#define HSA_CACHE_TYPE_RESERVED		0xfffffff0
101
102struct kfd_cache_properties {
103	struct list_head	list;
104	uint32_t		processor_id_low;
105	uint32_t		cache_level;
106	uint32_t		cache_size;
107	uint32_t		cacheline_size;
108	uint32_t		cachelines_per_tag;
109	uint32_t		cache_assoc;
110	uint32_t		cache_latency;
111	uint32_t		cache_type;
112	uint8_t			sibling_map[KFD_TOPOLOGY_CPU_SIBLINGS];
113	struct kobject		*kobj;
114	struct attribute	attr;
115};
116
117struct kfd_iolink_properties {
118	struct list_head	list;
119	uint32_t		iolink_type;
120	uint32_t		ver_maj;
121	uint32_t		ver_min;
122	uint32_t		node_from;
123	uint32_t		node_to;
124	uint32_t		weight;
125	uint32_t		min_latency;
126	uint32_t		max_latency;
127	uint32_t		min_bandwidth;
128	uint32_t		max_bandwidth;
129	uint32_t		rec_transfer_size;
130	uint32_t		flags;
131	struct kobject		*kobj;
132	struct attribute	attr;
133};
134
135struct kfd_topology_device {
136	struct list_head		list;
137	uint32_t			gpu_id;
138	struct kfd_node_properties	node_props;
139	uint32_t			mem_bank_count;
140	struct list_head		mem_props;
141	uint32_t			cache_count;
142	struct list_head		cache_props;
143	uint32_t			io_link_count;
144	struct list_head		io_link_props;
145	struct kfd_dev			*gpu;
146	struct kobject			*kobj_node;
147	struct kobject			*kobj_mem;
148	struct kobject			*kobj_cache;
149	struct kobject			*kobj_iolink;
150	struct attribute		attr_gpuid;
151	struct attribute		attr_name;
152	struct attribute		attr_props;
153};
154
155struct kfd_system_properties {
156	uint32_t		num_devices;     /* Number of H-NUMA nodes */
157	uint32_t		generation_count;
158	uint64_t		platform_oem;
159	uint64_t		platform_id;
160	uint64_t		platform_rev;
161	struct kobject		*kobj_topology;
162	struct kobject		*kobj_nodes;
163	struct attribute	attr_genid;
164	struct attribute	attr_props;
165};
166
167
168
169#endif /* __KFD_TOPOLOGY_H__ */