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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "vid.h"
27
28#include "oss/oss_2_4_d.h"
29#include "oss/oss_2_4_sh_mask.h"
30
31#include "bif/bif_5_1_d.h"
32#include "bif/bif_5_1_sh_mask.h"
33
34/*
35 * Interrupts
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
47 */
48
49static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev);
50
51/**
52 * iceland_ih_enable_interrupts - Enable the interrupt ring buffer
53 *
54 * @adev: amdgpu_device pointer
55 *
56 * Enable the interrupt ring buffer (VI).
57 */
58static void iceland_ih_enable_interrupts(struct amdgpu_device *adev)
59{
60 u32 ih_cntl = RREG32(mmIH_CNTL);
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
62
63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
65 WREG32(mmIH_CNTL, ih_cntl);
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67 adev->irq.ih.enabled = true;
68}
69
70/**
71 * iceland_ih_disable_interrupts - Disable the interrupt ring buffer
72 *
73 * @adev: amdgpu_device pointer
74 *
75 * Disable the interrupt ring buffer (VI).
76 */
77static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
78{
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80 u32 ih_cntl = RREG32(mmIH_CNTL);
81
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
84 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85 WREG32(mmIH_CNTL, ih_cntl);
86 /* set rptr, wptr to 0 */
87 WREG32(mmIH_RB_RPTR, 0);
88 WREG32(mmIH_RB_WPTR, 0);
89 adev->irq.ih.enabled = false;
90 adev->irq.ih.rptr = 0;
91}
92
93/**
94 * iceland_ih_irq_init - init and enable the interrupt ring
95 *
96 * @adev: amdgpu_device pointer
97 *
98 * Allocate a ring buffer for the interrupt controller,
99 * enable the RLC, disable interrupts, enable the IH
100 * ring buffer and enable it (VI).
101 * Called at device load and reume.
102 * Returns 0 for success, errors for failure.
103 */
104static int iceland_ih_irq_init(struct amdgpu_device *adev)
105{
106 int rb_bufsz;
107 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
108 u64 wptr_off;
109
110 /* disable irqs */
111 iceland_ih_disable_interrupts(adev);
112
113 /* setup interrupt control */
114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
118 */
119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
122 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
123
124 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
126
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
131
132 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
134
135 /* set the writeback address whether it's enabled or not */
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
137 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
138 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
139
140 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
141
142 /* set rptr, wptr to 0 */
143 WREG32(mmIH_RB_RPTR, 0);
144 WREG32(mmIH_RB_WPTR, 0);
145
146 /* Default settings for IH_CNTL (disabled at first) */
147 ih_cntl = RREG32(mmIH_CNTL);
148 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
149
150 if (adev->irq.msi_enabled)
151 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
152 WREG32(mmIH_CNTL, ih_cntl);
153
154 pci_set_master(adev->pdev);
155
156 /* enable interrupts */
157 iceland_ih_enable_interrupts(adev);
158
159 return 0;
160}
161
162/**
163 * iceland_ih_irq_disable - disable interrupts
164 *
165 * @adev: amdgpu_device pointer
166 *
167 * Disable interrupts on the hw (VI).
168 */
169static void iceland_ih_irq_disable(struct amdgpu_device *adev)
170{
171 iceland_ih_disable_interrupts(adev);
172
173 /* Wait and acknowledge irq */
174 mdelay(1);
175}
176
177/**
178 * iceland_ih_get_wptr - get the IH ring buffer wptr
179 *
180 * @adev: amdgpu_device pointer
181 *
182 * Get the IH ring buffer wptr from either the register
183 * or the writeback memory buffer (VI). Also check for
184 * ring buffer overflow and deal with it.
185 * Used by cz_irq_process(VI).
186 * Returns the value of the wptr.
187 */
188static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
189{
190 u32 wptr, tmp;
191
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
193
194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
196 /* When a ring buffer overflow happen start parsing interrupt
197 * from the last not overwritten vector (wptr + 16). Hopefully
198 * this should allow us to catchup.
199 */
200 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
203 tmp = RREG32(mmIH_RB_CNTL);
204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
205 WREG32(mmIH_RB_CNTL, tmp);
206 }
207 return (wptr & adev->irq.ih.ptr_mask);
208}
209
210/**
211 * iceland_ih_decode_iv - decode an interrupt vector
212 *
213 * @adev: amdgpu_device pointer
214 *
215 * Decodes the interrupt vector at the current rptr
216 * position and also advance the position.
217 */
218static void iceland_ih_decode_iv(struct amdgpu_device *adev,
219 struct amdgpu_iv_entry *entry)
220{
221 /* wptr/rptr are in bytes! */
222 u32 ring_index = adev->irq.ih.rptr >> 2;
223 uint32_t dw[4];
224
225 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
226 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
227 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
228 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
229
230 entry->src_id = dw[0] & 0xff;
231 entry->src_data = dw[1] & 0xfffffff;
232 entry->ring_id = dw[2] & 0xff;
233 entry->vm_id = (dw[2] >> 8) & 0xff;
234 entry->pas_id = (dw[2] >> 16) & 0xffff;
235
236 /* wptr/rptr are in bytes! */
237 adev->irq.ih.rptr += 16;
238}
239
240/**
241 * iceland_ih_set_rptr - set the IH ring buffer rptr
242 *
243 * @adev: amdgpu_device pointer
244 *
245 * Set the IH ring buffer rptr.
246 */
247static void iceland_ih_set_rptr(struct amdgpu_device *adev)
248{
249 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
250}
251
252static int iceland_ih_early_init(void *handle)
253{
254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
255 int ret;
256
257 ret = amdgpu_irq_add_domain(adev);
258 if (ret)
259 return ret;
260
261 iceland_ih_set_interrupt_funcs(adev);
262
263 return 0;
264}
265
266static int iceland_ih_sw_init(void *handle)
267{
268 int r;
269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
270
271 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
272 if (r)
273 return r;
274
275 r = amdgpu_irq_init(adev);
276
277 return r;
278}
279
280static int iceland_ih_sw_fini(void *handle)
281{
282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283
284 amdgpu_irq_fini(adev);
285 amdgpu_ih_ring_fini(adev);
286 amdgpu_irq_remove_domain(adev);
287
288 return 0;
289}
290
291static int iceland_ih_hw_init(void *handle)
292{
293 int r;
294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
295
296 r = iceland_ih_irq_init(adev);
297 if (r)
298 return r;
299
300 return 0;
301}
302
303static int iceland_ih_hw_fini(void *handle)
304{
305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
306
307 iceland_ih_irq_disable(adev);
308
309 return 0;
310}
311
312static int iceland_ih_suspend(void *handle)
313{
314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
315
316 return iceland_ih_hw_fini(adev);
317}
318
319static int iceland_ih_resume(void *handle)
320{
321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
322
323 return iceland_ih_hw_init(adev);
324}
325
326static bool iceland_ih_is_idle(void *handle)
327{
328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
329 u32 tmp = RREG32(mmSRBM_STATUS);
330
331 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
332 return false;
333
334 return true;
335}
336
337static int iceland_ih_wait_for_idle(void *handle)
338{
339 unsigned i;
340 u32 tmp;
341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
342
343 for (i = 0; i < adev->usec_timeout; i++) {
344 /* read MC_STATUS */
345 tmp = RREG32(mmSRBM_STATUS);
346 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
347 return 0;
348 udelay(1);
349 }
350 return -ETIMEDOUT;
351}
352
353static int iceland_ih_soft_reset(void *handle)
354{
355 u32 srbm_soft_reset = 0;
356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
357 u32 tmp = RREG32(mmSRBM_STATUS);
358
359 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
360 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
361 SOFT_RESET_IH, 1);
362
363 if (srbm_soft_reset) {
364 tmp = RREG32(mmSRBM_SOFT_RESET);
365 tmp |= srbm_soft_reset;
366 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
367 WREG32(mmSRBM_SOFT_RESET, tmp);
368 tmp = RREG32(mmSRBM_SOFT_RESET);
369
370 udelay(50);
371
372 tmp &= ~srbm_soft_reset;
373 WREG32(mmSRBM_SOFT_RESET, tmp);
374 tmp = RREG32(mmSRBM_SOFT_RESET);
375
376 /* Wait a little for things to settle down */
377 udelay(50);
378 }
379
380 return 0;
381}
382
383static int iceland_ih_set_clockgating_state(void *handle,
384 enum amd_clockgating_state state)
385{
386 return 0;
387}
388
389static int iceland_ih_set_powergating_state(void *handle,
390 enum amd_powergating_state state)
391{
392 return 0;
393}
394
395static const struct amd_ip_funcs iceland_ih_ip_funcs = {
396 .name = "iceland_ih",
397 .early_init = iceland_ih_early_init,
398 .late_init = NULL,
399 .sw_init = iceland_ih_sw_init,
400 .sw_fini = iceland_ih_sw_fini,
401 .hw_init = iceland_ih_hw_init,
402 .hw_fini = iceland_ih_hw_fini,
403 .suspend = iceland_ih_suspend,
404 .resume = iceland_ih_resume,
405 .is_idle = iceland_ih_is_idle,
406 .wait_for_idle = iceland_ih_wait_for_idle,
407 .soft_reset = iceland_ih_soft_reset,
408 .set_clockgating_state = iceland_ih_set_clockgating_state,
409 .set_powergating_state = iceland_ih_set_powergating_state,
410};
411
412static const struct amdgpu_ih_funcs iceland_ih_funcs = {
413 .get_wptr = iceland_ih_get_wptr,
414 .decode_iv = iceland_ih_decode_iv,
415 .set_rptr = iceland_ih_set_rptr
416};
417
418static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
419{
420 if (adev->irq.ih_funcs == NULL)
421 adev->irq.ih_funcs = &iceland_ih_funcs;
422}
423
424const struct amdgpu_ip_block_version iceland_ih_ip_block =
425{
426 .type = AMD_IP_BLOCK_TYPE_IH,
427 .major = 2,
428 .minor = 4,
429 .rev = 0,
430 .funcs = &iceland_ih_ip_funcs,
431};