1/*
  2 * Copyright 2011 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Alex Deucher
 23 *
 24 */
 25#include <drm/drmP.h>
 26#include <drm/amdgpu_drm.h>
 27#include "amdgpu.h"
 28#include "atom.h"
 29#include "amdgpu_atombios.h"
 30#include "atombios_i2c.h"
 31
 32#define TARGET_HW_I2C_CLOCK 50
 33
 34/* these are a limitation of ProcessI2cChannelTransaction not the hw */
 35#define ATOM_MAX_HW_I2C_WRITE 3
 36#define ATOM_MAX_HW_I2C_READ  255
 37
 38static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
 39				       u8 slave_addr, u8 flags,
 40				       u8 *buf, u8 num)
 41{
 42	struct drm_device *dev = chan->dev;
 43	struct amdgpu_device *adev = dev->dev_private;
 44	PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
 45	int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
 46	unsigned char *base;
 47	u16 out = cpu_to_le16(0);
 48	int r = 0;
 49
 50	memset(&args, 0, sizeof(args));
 51
 52	mutex_lock(&chan->mutex);
 53
 54	base = (unsigned char *)adev->mode_info.atom_context->scratch;
 55
 56	if (flags & HW_I2C_WRITE) {
 57		if (num > ATOM_MAX_HW_I2C_WRITE) {
 58			DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
 59			r = -EINVAL;
 60			goto done;
 61		}
 62		if (buf == NULL)
 63			args.ucRegIndex = 0;
 64		else
 65			args.ucRegIndex = buf[0];
 66		if (num)
 67			num--;
 68		if (num)
 69			memcpy(&out, &buf[1], num);
 70		args.lpI2CDataOut = cpu_to_le16(out);
 71	} else {
 72		if (num > ATOM_MAX_HW_I2C_READ) {
 73			DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
 74			r = -EINVAL;
 75			goto done;
 76		}
 77		args.ucRegIndex = 0;
 78		args.lpI2CDataOut = 0;
 79	}
 80
 81	args.ucFlag = flags;
 82	args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
 83	args.ucTransBytes = num;
 84	args.ucSlaveAddr = slave_addr << 1;
 85	args.ucLineNumber = chan->rec.i2c_id;
 86
 87	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 88
 89	/* error */
 90	if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
 91		DRM_DEBUG_KMS("hw_i2c error\n");
 92		r = -EIO;
 93		goto done;
 94	}
 95
 96	if (!(flags & HW_I2C_WRITE))
 97		amdgpu_atombios_copy_swap(buf, base, num, false);
 98
 99done:
100	mutex_unlock(&chan->mutex);
101
102	return r;
103}
104
105int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
106		      struct i2c_msg *msgs, int num)
107{
108	struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
109	struct i2c_msg *p;
110	int i, remaining, current_count, buffer_offset, max_bytes, ret;
111	u8 flags;
112
113	/* check for bus probe */
114	p = &msgs[0];
115	if ((num == 1) && (p->len == 0)) {
116		ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
117						  p->addr, HW_I2C_WRITE,
118						  NULL, 0);
119		if (ret)
120			return ret;
121		else
122			return num;
123	}
124
125	for (i = 0; i < num; i++) {
126		p = &msgs[i];
127		remaining = p->len;
128		buffer_offset = 0;
129		/* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
130		if (p->flags & I2C_M_RD) {
131			max_bytes = ATOM_MAX_HW_I2C_READ;
132			flags = HW_I2C_READ;
133		} else {
134			max_bytes = ATOM_MAX_HW_I2C_WRITE;
135			flags = HW_I2C_WRITE;
136		}
137		while (remaining) {
138			if (remaining > max_bytes)
139				current_count = max_bytes;
140			else
141				current_count = remaining;
142			ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
143							  p->addr, flags,
144							  &p->buf[buffer_offset], current_count);
145			if (ret)
146				return ret;
147			remaining -= current_count;
148			buffer_offset += current_count;
149		}
150	}
151
152	return num;
153}
154
155u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
156{
157	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
158}
159
160void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
161{
162	PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
163	int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
164
165	args.ucRegIndex = offset;
166	args.lpI2CDataOut = data;
167	args.ucFlag = 1;
168	args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
169	args.ucTransBytes = 1;
170	args.ucSlaveAddr = slave_addr;
171	args.ucLineNumber = line_number;
172
173	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
174}