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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "bif/bif_4_1_d.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53
54/*
55 * Global memory.
56 */
57static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
58{
59 return ttm_mem_global_init(ref->object);
60}
61
62static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
63{
64 ttm_mem_global_release(ref->object);
65}
66
67static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
68{
69 struct drm_global_reference *global_ref;
70 struct amdgpu_ring *ring;
71 struct amd_sched_rq *rq;
72 int r;
73
74 adev->mman.mem_global_referenced = false;
75 global_ref = &adev->mman.mem_global_ref;
76 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
77 global_ref->size = sizeof(struct ttm_mem_global);
78 global_ref->init = &amdgpu_ttm_mem_global_init;
79 global_ref->release = &amdgpu_ttm_mem_global_release;
80 r = drm_global_item_ref(global_ref);
81 if (r) {
82 DRM_ERROR("Failed setting up TTM memory accounting "
83 "subsystem.\n");
84 goto error_mem;
85 }
86
87 adev->mman.bo_global_ref.mem_glob =
88 adev->mman.mem_global_ref.object;
89 global_ref = &adev->mman.bo_global_ref.ref;
90 global_ref->global_type = DRM_GLOBAL_TTM_BO;
91 global_ref->size = sizeof(struct ttm_bo_global);
92 global_ref->init = &ttm_bo_global_init;
93 global_ref->release = &ttm_bo_global_release;
94 r = drm_global_item_ref(global_ref);
95 if (r) {
96 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
97 goto error_bo;
98 }
99
100 ring = adev->mman.buffer_funcs_ring;
101 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
102 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
103 rq, amdgpu_sched_jobs);
104 if (r) {
105 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
106 goto error_entity;
107 }
108
109 adev->mman.mem_global_referenced = true;
110
111 return 0;
112
113error_entity:
114 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
115error_bo:
116 drm_global_item_unref(&adev->mman.mem_global_ref);
117error_mem:
118 return r;
119}
120
121static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
122{
123 if (adev->mman.mem_global_referenced) {
124 amd_sched_entity_fini(adev->mman.entity.sched,
125 &adev->mman.entity);
126 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
127 drm_global_item_unref(&adev->mman.mem_global_ref);
128 adev->mman.mem_global_referenced = false;
129 }
130}
131
132static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
133{
134 return 0;
135}
136
137static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
138 struct ttm_mem_type_manager *man)
139{
140 struct amdgpu_device *adev;
141
142 adev = amdgpu_ttm_adev(bdev);
143
144 switch (type) {
145 case TTM_PL_SYSTEM:
146 /* System memory */
147 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
148 man->available_caching = TTM_PL_MASK_CACHING;
149 man->default_caching = TTM_PL_FLAG_CACHED;
150 break;
151 case TTM_PL_TT:
152 man->func = &amdgpu_gtt_mgr_func;
153 man->gpu_offset = adev->mc.gtt_start;
154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
157 break;
158 case TTM_PL_VRAM:
159 /* "On-card" video ram */
160 man->func = &amdgpu_vram_mgr_func;
161 man->gpu_offset = adev->mc.vram_start;
162 man->flags = TTM_MEMTYPE_FLAG_FIXED |
163 TTM_MEMTYPE_FLAG_MAPPABLE;
164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
165 man->default_caching = TTM_PL_FLAG_WC;
166 break;
167 case AMDGPU_PL_GDS:
168 case AMDGPU_PL_GWS:
169 case AMDGPU_PL_OA:
170 /* On-chip GDS memory*/
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = 0;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
174 man->available_caching = TTM_PL_FLAG_UNCACHED;
175 man->default_caching = TTM_PL_FLAG_UNCACHED;
176 break;
177 default:
178 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
179 return -EINVAL;
180 }
181 return 0;
182}
183
184static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
185 struct ttm_placement *placement)
186{
187 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
188 struct amdgpu_bo *abo;
189 static struct ttm_place placements = {
190 .fpfn = 0,
191 .lpfn = 0,
192 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
193 };
194 unsigned i;
195
196 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
197 placement->placement = &placements;
198 placement->busy_placement = &placements;
199 placement->num_placement = 1;
200 placement->num_busy_placement = 1;
201 return;
202 }
203 abo = container_of(bo, struct amdgpu_bo, tbo);
204 switch (bo->mem.mem_type) {
205 case TTM_PL_VRAM:
206 if (adev->mman.buffer_funcs_ring->ready == false) {
207 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
208 } else {
209 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
210 for (i = 0; i < abo->placement.num_placement; ++i) {
211 if (!(abo->placements[i].flags &
212 TTM_PL_FLAG_TT))
213 continue;
214
215 if (abo->placements[i].lpfn)
216 continue;
217
218 /* set an upper limit to force directly
219 * allocating address space for the BO.
220 */
221 abo->placements[i].lpfn =
222 adev->mc.gtt_size >> PAGE_SHIFT;
223 }
224 }
225 break;
226 case TTM_PL_TT:
227 default:
228 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
229 }
230 *placement = abo->placement;
231}
232
233static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
234{
235 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
236
237 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
238 return -EPERM;
239 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
240 filp->private_data);
241}
242
243static void amdgpu_move_null(struct ttm_buffer_object *bo,
244 struct ttm_mem_reg *new_mem)
245{
246 struct ttm_mem_reg *old_mem = &bo->mem;
247
248 BUG_ON(old_mem->mm_node != NULL);
249 *old_mem = *new_mem;
250 new_mem->mm_node = NULL;
251}
252
253static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
254 struct drm_mm_node *mm_node,
255 struct ttm_mem_reg *mem,
256 uint64_t *addr)
257{
258 int r;
259
260 switch (mem->mem_type) {
261 case TTM_PL_TT:
262 r = amdgpu_ttm_bind(bo, mem);
263 if (r)
264 return r;
265
266 case TTM_PL_VRAM:
267 *addr = mm_node->start << PAGE_SHIFT;
268 *addr += bo->bdev->man[mem->mem_type].gpu_offset;
269 break;
270 default:
271 DRM_ERROR("Unknown placement %d\n", mem->mem_type);
272 return -EINVAL;
273 }
274
275 return 0;
276}
277
278static int amdgpu_move_blit(struct ttm_buffer_object *bo,
279 bool evict, bool no_wait_gpu,
280 struct ttm_mem_reg *new_mem,
281 struct ttm_mem_reg *old_mem)
282{
283 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
284 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
285
286 struct drm_mm_node *old_mm, *new_mm;
287 uint64_t old_start, old_size, new_start, new_size;
288 unsigned long num_pages;
289 struct dma_fence *fence = NULL;
290 int r;
291
292 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
293
294 if (!ring->ready) {
295 DRM_ERROR("Trying to move memory with ring turned off.\n");
296 return -EINVAL;
297 }
298
299 old_mm = old_mem->mm_node;
300 r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start);
301 if (r)
302 return r;
303 old_size = old_mm->size;
304
305
306 new_mm = new_mem->mm_node;
307 r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start);
308 if (r)
309 return r;
310 new_size = new_mm->size;
311
312 num_pages = new_mem->num_pages;
313 while (num_pages) {
314 unsigned long cur_pages = min(old_size, new_size);
315 struct dma_fence *next;
316
317 r = amdgpu_copy_buffer(ring, old_start, new_start,
318 cur_pages * PAGE_SIZE,
319 bo->resv, &next, false);
320 if (r)
321 goto error;
322
323 dma_fence_put(fence);
324 fence = next;
325
326 num_pages -= cur_pages;
327 if (!num_pages)
328 break;
329
330 old_size -= cur_pages;
331 if (!old_size) {
332 r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
333 &old_start);
334 if (r)
335 goto error;
336 old_size = old_mm->size;
337 } else {
338 old_start += cur_pages * PAGE_SIZE;
339 }
340
341 new_size -= cur_pages;
342 if (!new_size) {
343 r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
344 &new_start);
345 if (r)
346 goto error;
347
348 new_size = new_mm->size;
349 } else {
350 new_start += cur_pages * PAGE_SIZE;
351 }
352 }
353
354 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
355 dma_fence_put(fence);
356 return r;
357
358error:
359 if (fence)
360 dma_fence_wait(fence, false);
361 dma_fence_put(fence);
362 return r;
363}
364
365static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
366 bool evict, bool interruptible,
367 bool no_wait_gpu,
368 struct ttm_mem_reg *new_mem)
369{
370 struct amdgpu_device *adev;
371 struct ttm_mem_reg *old_mem = &bo->mem;
372 struct ttm_mem_reg tmp_mem;
373 struct ttm_place placements;
374 struct ttm_placement placement;
375 int r;
376
377 adev = amdgpu_ttm_adev(bo->bdev);
378 tmp_mem = *new_mem;
379 tmp_mem.mm_node = NULL;
380 placement.num_placement = 1;
381 placement.placement = &placements;
382 placement.num_busy_placement = 1;
383 placement.busy_placement = &placements;
384 placements.fpfn = 0;
385 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
386 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
387 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
388 interruptible, no_wait_gpu);
389 if (unlikely(r)) {
390 return r;
391 }
392
393 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
394 if (unlikely(r)) {
395 goto out_cleanup;
396 }
397
398 r = ttm_tt_bind(bo->ttm, &tmp_mem);
399 if (unlikely(r)) {
400 goto out_cleanup;
401 }
402 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
403 if (unlikely(r)) {
404 goto out_cleanup;
405 }
406 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
407out_cleanup:
408 ttm_bo_mem_put(bo, &tmp_mem);
409 return r;
410}
411
412static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
413 bool evict, bool interruptible,
414 bool no_wait_gpu,
415 struct ttm_mem_reg *new_mem)
416{
417 struct amdgpu_device *adev;
418 struct ttm_mem_reg *old_mem = &bo->mem;
419 struct ttm_mem_reg tmp_mem;
420 struct ttm_placement placement;
421 struct ttm_place placements;
422 int r;
423
424 adev = amdgpu_ttm_adev(bo->bdev);
425 tmp_mem = *new_mem;
426 tmp_mem.mm_node = NULL;
427 placement.num_placement = 1;
428 placement.placement = &placements;
429 placement.num_busy_placement = 1;
430 placement.busy_placement = &placements;
431 placements.fpfn = 0;
432 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
433 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
434 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
435 interruptible, no_wait_gpu);
436 if (unlikely(r)) {
437 return r;
438 }
439 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
440 if (unlikely(r)) {
441 goto out_cleanup;
442 }
443 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
444 if (unlikely(r)) {
445 goto out_cleanup;
446 }
447out_cleanup:
448 ttm_bo_mem_put(bo, &tmp_mem);
449 return r;
450}
451
452static int amdgpu_bo_move(struct ttm_buffer_object *bo,
453 bool evict, bool interruptible,
454 bool no_wait_gpu,
455 struct ttm_mem_reg *new_mem)
456{
457 struct amdgpu_device *adev;
458 struct amdgpu_bo *abo;
459 struct ttm_mem_reg *old_mem = &bo->mem;
460 int r;
461
462 /* Can't move a pinned BO */
463 abo = container_of(bo, struct amdgpu_bo, tbo);
464 if (WARN_ON_ONCE(abo->pin_count > 0))
465 return -EINVAL;
466
467 adev = amdgpu_ttm_adev(bo->bdev);
468
469 /* remember the eviction */
470 if (evict)
471 atomic64_inc(&adev->num_evictions);
472
473 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
474 amdgpu_move_null(bo, new_mem);
475 return 0;
476 }
477 if ((old_mem->mem_type == TTM_PL_TT &&
478 new_mem->mem_type == TTM_PL_SYSTEM) ||
479 (old_mem->mem_type == TTM_PL_SYSTEM &&
480 new_mem->mem_type == TTM_PL_TT)) {
481 /* bind is enough */
482 amdgpu_move_null(bo, new_mem);
483 return 0;
484 }
485 if (adev->mman.buffer_funcs == NULL ||
486 adev->mman.buffer_funcs_ring == NULL ||
487 !adev->mman.buffer_funcs_ring->ready) {
488 /* use memcpy */
489 goto memcpy;
490 }
491
492 if (old_mem->mem_type == TTM_PL_VRAM &&
493 new_mem->mem_type == TTM_PL_SYSTEM) {
494 r = amdgpu_move_vram_ram(bo, evict, interruptible,
495 no_wait_gpu, new_mem);
496 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
497 new_mem->mem_type == TTM_PL_VRAM) {
498 r = amdgpu_move_ram_vram(bo, evict, interruptible,
499 no_wait_gpu, new_mem);
500 } else {
501 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
502 }
503
504 if (r) {
505memcpy:
506 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
507 if (r) {
508 return r;
509 }
510 }
511
512 /* update statistics */
513 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
514 return 0;
515}
516
517static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
518{
519 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
520 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
521
522 mem->bus.addr = NULL;
523 mem->bus.offset = 0;
524 mem->bus.size = mem->num_pages << PAGE_SHIFT;
525 mem->bus.base = 0;
526 mem->bus.is_iomem = false;
527 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
528 return -EINVAL;
529 switch (mem->mem_type) {
530 case TTM_PL_SYSTEM:
531 /* system memory */
532 return 0;
533 case TTM_PL_TT:
534 break;
535 case TTM_PL_VRAM:
536 mem->bus.offset = mem->start << PAGE_SHIFT;
537 /* check if it's visible */
538 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
539 return -EINVAL;
540 mem->bus.base = adev->mc.aper_base;
541 mem->bus.is_iomem = true;
542#ifdef __alpha__
543 /*
544 * Alpha: use bus.addr to hold the ioremap() return,
545 * so we can modify bus.base below.
546 */
547 if (mem->placement & TTM_PL_FLAG_WC)
548 mem->bus.addr =
549 ioremap_wc(mem->bus.base + mem->bus.offset,
550 mem->bus.size);
551 else
552 mem->bus.addr =
553 ioremap_nocache(mem->bus.base + mem->bus.offset,
554 mem->bus.size);
555
556 /*
557 * Alpha: Use just the bus offset plus
558 * the hose/domain memory base for bus.base.
559 * It then can be used to build PTEs for VRAM
560 * access, as done in ttm_bo_vm_fault().
561 */
562 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
563 adev->ddev->hose->dense_mem_base;
564#endif
565 break;
566 default:
567 return -EINVAL;
568 }
569 return 0;
570}
571
572static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
573{
574}
575
576/*
577 * TTM backend functions.
578 */
579struct amdgpu_ttm_gup_task_list {
580 struct list_head list;
581 struct task_struct *task;
582};
583
584struct amdgpu_ttm_tt {
585 struct ttm_dma_tt ttm;
586 struct amdgpu_device *adev;
587 u64 offset;
588 uint64_t userptr;
589 struct mm_struct *usermm;
590 uint32_t userflags;
591 spinlock_t guptasklock;
592 struct list_head guptasks;
593 atomic_t mmu_invalidations;
594 struct list_head list;
595};
596
597int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
598{
599 struct amdgpu_ttm_tt *gtt = (void *)ttm;
600 unsigned int flags = 0;
601 unsigned pinned = 0;
602 int r;
603
604 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
605 flags |= FOLL_WRITE;
606
607 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
608 /* check that we only use anonymous memory
609 to prevent problems with writeback */
610 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
611 struct vm_area_struct *vma;
612
613 vma = find_vma(gtt->usermm, gtt->userptr);
614 if (!vma || vma->vm_file || vma->vm_end < end)
615 return -EPERM;
616 }
617
618 do {
619 unsigned num_pages = ttm->num_pages - pinned;
620 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
621 struct page **p = pages + pinned;
622 struct amdgpu_ttm_gup_task_list guptask;
623
624 guptask.task = current;
625 spin_lock(>t->guptasklock);
626 list_add(&guptask.list, >t->guptasks);
627 spin_unlock(>t->guptasklock);
628
629 r = get_user_pages(userptr, num_pages, flags, p, NULL);
630
631 spin_lock(>t->guptasklock);
632 list_del(&guptask.list);
633 spin_unlock(>t->guptasklock);
634
635 if (r < 0)
636 goto release_pages;
637
638 pinned += r;
639
640 } while (pinned < ttm->num_pages);
641
642 return 0;
643
644release_pages:
645 release_pages(pages, pinned, 0);
646 return r;
647}
648
649/* prepare the sg table with the user pages */
650static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
651{
652 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
653 struct amdgpu_ttm_tt *gtt = (void *)ttm;
654 unsigned nents;
655 int r;
656
657 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
658 enum dma_data_direction direction = write ?
659 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
660
661 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
662 ttm->num_pages << PAGE_SHIFT,
663 GFP_KERNEL);
664 if (r)
665 goto release_sg;
666
667 r = -ENOMEM;
668 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
669 if (nents != ttm->sg->nents)
670 goto release_sg;
671
672 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
673 gtt->ttm.dma_address, ttm->num_pages);
674
675 return 0;
676
677release_sg:
678 kfree(ttm->sg);
679 return r;
680}
681
682static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
683{
684 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
685 struct amdgpu_ttm_tt *gtt = (void *)ttm;
686 struct sg_page_iter sg_iter;
687
688 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
689 enum dma_data_direction direction = write ?
690 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
691
692 /* double check that we don't free the table twice */
693 if (!ttm->sg->sgl)
694 return;
695
696 /* free the sg table and pages again */
697 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
698
699 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
700 struct page *page = sg_page_iter_page(&sg_iter);
701 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
702 set_page_dirty(page);
703
704 mark_page_accessed(page);
705 put_page(page);
706 }
707
708 sg_free_table(ttm->sg);
709}
710
711static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
712 struct ttm_mem_reg *bo_mem)
713{
714 struct amdgpu_ttm_tt *gtt = (void*)ttm;
715 int r;
716
717 if (gtt->userptr) {
718 r = amdgpu_ttm_tt_pin_userptr(ttm);
719 if (r) {
720 DRM_ERROR("failed to pin userptr\n");
721 return r;
722 }
723 }
724 if (!ttm->num_pages) {
725 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
726 ttm->num_pages, bo_mem, ttm);
727 }
728
729 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
730 bo_mem->mem_type == AMDGPU_PL_GWS ||
731 bo_mem->mem_type == AMDGPU_PL_OA)
732 return -EINVAL;
733
734 return 0;
735}
736
737bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
738{
739 struct amdgpu_ttm_tt *gtt = (void *)ttm;
740
741 return gtt && !list_empty(>t->list);
742}
743
744int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
745{
746 struct ttm_tt *ttm = bo->ttm;
747 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
748 uint32_t flags;
749 int r;
750
751 if (!ttm || amdgpu_ttm_is_bound(ttm))
752 return 0;
753
754 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
755 NULL, bo_mem);
756 if (r) {
757 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
758 return r;
759 }
760
761 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
762 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
763 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
764 ttm->pages, gtt->ttm.dma_address, flags);
765
766 if (r) {
767 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
768 ttm->num_pages, gtt->offset);
769 return r;
770 }
771 spin_lock(>t->adev->gtt_list_lock);
772 list_add_tail(>t->list, >t->adev->gtt_list);
773 spin_unlock(>t->adev->gtt_list_lock);
774 return 0;
775}
776
777int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
778{
779 struct amdgpu_ttm_tt *gtt, *tmp;
780 struct ttm_mem_reg bo_mem;
781 uint32_t flags;
782 int r;
783
784 bo_mem.mem_type = TTM_PL_TT;
785 spin_lock(&adev->gtt_list_lock);
786 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
787 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
788 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
789 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
790 flags);
791 if (r) {
792 spin_unlock(&adev->gtt_list_lock);
793 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
794 gtt->ttm.ttm.num_pages, gtt->offset);
795 return r;
796 }
797 }
798 spin_unlock(&adev->gtt_list_lock);
799 return 0;
800}
801
802static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
803{
804 struct amdgpu_ttm_tt *gtt = (void *)ttm;
805
806 if (gtt->userptr)
807 amdgpu_ttm_tt_unpin_userptr(ttm);
808
809 if (!amdgpu_ttm_is_bound(ttm))
810 return 0;
811
812 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
813 if (gtt->adev->gart.ready)
814 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
815
816 spin_lock(>t->adev->gtt_list_lock);
817 list_del_init(>t->list);
818 spin_unlock(>t->adev->gtt_list_lock);
819
820 return 0;
821}
822
823static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
824{
825 struct amdgpu_ttm_tt *gtt = (void *)ttm;
826
827 ttm_dma_tt_fini(>t->ttm);
828 kfree(gtt);
829}
830
831static struct ttm_backend_func amdgpu_backend_func = {
832 .bind = &amdgpu_ttm_backend_bind,
833 .unbind = &amdgpu_ttm_backend_unbind,
834 .destroy = &amdgpu_ttm_backend_destroy,
835};
836
837static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
838 unsigned long size, uint32_t page_flags,
839 struct page *dummy_read_page)
840{
841 struct amdgpu_device *adev;
842 struct amdgpu_ttm_tt *gtt;
843
844 adev = amdgpu_ttm_adev(bdev);
845
846 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
847 if (gtt == NULL) {
848 return NULL;
849 }
850 gtt->ttm.ttm.func = &amdgpu_backend_func;
851 gtt->adev = adev;
852 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
853 kfree(gtt);
854 return NULL;
855 }
856 INIT_LIST_HEAD(>t->list);
857 return >t->ttm.ttm;
858}
859
860static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
861{
862 struct amdgpu_device *adev;
863 struct amdgpu_ttm_tt *gtt = (void *)ttm;
864 unsigned i;
865 int r;
866 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
867
868 if (ttm->state != tt_unpopulated)
869 return 0;
870
871 if (gtt && gtt->userptr) {
872 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
873 if (!ttm->sg)
874 return -ENOMEM;
875
876 ttm->page_flags |= TTM_PAGE_FLAG_SG;
877 ttm->state = tt_unbound;
878 return 0;
879 }
880
881 if (slave && ttm->sg) {
882 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
883 gtt->ttm.dma_address, ttm->num_pages);
884 ttm->state = tt_unbound;
885 return 0;
886 }
887
888 adev = amdgpu_ttm_adev(ttm->bdev);
889
890#ifdef CONFIG_SWIOTLB
891 if (swiotlb_nr_tbl()) {
892 return ttm_dma_populate(>t->ttm, adev->dev);
893 }
894#endif
895
896 r = ttm_pool_populate(ttm);
897 if (r) {
898 return r;
899 }
900
901 for (i = 0; i < ttm->num_pages; i++) {
902 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
903 0, PAGE_SIZE,
904 PCI_DMA_BIDIRECTIONAL);
905 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
906 while (i--) {
907 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
908 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
909 gtt->ttm.dma_address[i] = 0;
910 }
911 ttm_pool_unpopulate(ttm);
912 return -EFAULT;
913 }
914 }
915 return 0;
916}
917
918static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
919{
920 struct amdgpu_device *adev;
921 struct amdgpu_ttm_tt *gtt = (void *)ttm;
922 unsigned i;
923 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
924
925 if (gtt && gtt->userptr) {
926 kfree(ttm->sg);
927 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
928 return;
929 }
930
931 if (slave)
932 return;
933
934 adev = amdgpu_ttm_adev(ttm->bdev);
935
936#ifdef CONFIG_SWIOTLB
937 if (swiotlb_nr_tbl()) {
938 ttm_dma_unpopulate(>t->ttm, adev->dev);
939 return;
940 }
941#endif
942
943 for (i = 0; i < ttm->num_pages; i++) {
944 if (gtt->ttm.dma_address[i]) {
945 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
946 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
947 }
948 }
949
950 ttm_pool_unpopulate(ttm);
951}
952
953int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
954 uint32_t flags)
955{
956 struct amdgpu_ttm_tt *gtt = (void *)ttm;
957
958 if (gtt == NULL)
959 return -EINVAL;
960
961 gtt->userptr = addr;
962 gtt->usermm = current->mm;
963 gtt->userflags = flags;
964 spin_lock_init(>t->guptasklock);
965 INIT_LIST_HEAD(>t->guptasks);
966 atomic_set(>t->mmu_invalidations, 0);
967
968 return 0;
969}
970
971struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
972{
973 struct amdgpu_ttm_tt *gtt = (void *)ttm;
974
975 if (gtt == NULL)
976 return NULL;
977
978 return gtt->usermm;
979}
980
981bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
982 unsigned long end)
983{
984 struct amdgpu_ttm_tt *gtt = (void *)ttm;
985 struct amdgpu_ttm_gup_task_list *entry;
986 unsigned long size;
987
988 if (gtt == NULL || !gtt->userptr)
989 return false;
990
991 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
992 if (gtt->userptr > end || gtt->userptr + size <= start)
993 return false;
994
995 spin_lock(>t->guptasklock);
996 list_for_each_entry(entry, >t->guptasks, list) {
997 if (entry->task == current) {
998 spin_unlock(>t->guptasklock);
999 return false;
1000 }
1001 }
1002 spin_unlock(>t->guptasklock);
1003
1004 atomic_inc(>t->mmu_invalidations);
1005
1006 return true;
1007}
1008
1009bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1010 int *last_invalidated)
1011{
1012 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1013 int prev_invalidated = *last_invalidated;
1014
1015 *last_invalidated = atomic_read(>t->mmu_invalidations);
1016 return prev_invalidated != *last_invalidated;
1017}
1018
1019bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1020{
1021 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1022
1023 if (gtt == NULL)
1024 return false;
1025
1026 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1027}
1028
1029uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1030 struct ttm_mem_reg *mem)
1031{
1032 uint32_t flags = 0;
1033
1034 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1035 flags |= AMDGPU_PTE_VALID;
1036
1037 if (mem && mem->mem_type == TTM_PL_TT) {
1038 flags |= AMDGPU_PTE_SYSTEM;
1039
1040 if (ttm->caching_state == tt_cached)
1041 flags |= AMDGPU_PTE_SNOOPED;
1042 }
1043
1044 if (adev->asic_type >= CHIP_TONGA)
1045 flags |= AMDGPU_PTE_EXECUTABLE;
1046
1047 flags |= AMDGPU_PTE_READABLE;
1048
1049 if (!amdgpu_ttm_tt_is_readonly(ttm))
1050 flags |= AMDGPU_PTE_WRITEABLE;
1051
1052 return flags;
1053}
1054
1055static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1056{
1057 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1058 unsigned i, j;
1059
1060 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1061 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1062
1063 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1064 if (&tbo->lru == lru->lru[j])
1065 lru->lru[j] = tbo->lru.prev;
1066
1067 if (&tbo->swap == lru->swap_lru)
1068 lru->swap_lru = tbo->swap.prev;
1069 }
1070}
1071
1072static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1073{
1074 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1075 unsigned log2_size = min(ilog2(tbo->num_pages),
1076 AMDGPU_TTM_LRU_SIZE - 1);
1077
1078 return &adev->mman.log2_size[log2_size];
1079}
1080
1081static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1082{
1083 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1084 struct list_head *res = lru->lru[tbo->mem.mem_type];
1085
1086 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1087 while ((++lru)->lru[tbo->mem.mem_type] == res)
1088 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1089
1090 return res;
1091}
1092
1093static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1094{
1095 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1096 struct list_head *res = lru->swap_lru;
1097
1098 lru->swap_lru = &tbo->swap;
1099 while ((++lru)->swap_lru == res)
1100 lru->swap_lru = &tbo->swap;
1101
1102 return res;
1103}
1104
1105static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1106 const struct ttm_place *place)
1107{
1108 if (bo->mem.mem_type == TTM_PL_VRAM &&
1109 bo->mem.start == AMDGPU_BO_INVALID_OFFSET) {
1110 unsigned long num_pages = bo->mem.num_pages;
1111 struct drm_mm_node *node = bo->mem.mm_node;
1112
1113 /* Check each drm MM node individually */
1114 while (num_pages) {
1115 if (place->fpfn < (node->start + node->size) &&
1116 !(place->lpfn && place->lpfn <= node->start))
1117 return true;
1118
1119 num_pages -= node->size;
1120 ++node;
1121 }
1122
1123 return false;
1124 }
1125
1126 return ttm_bo_eviction_valuable(bo, place);
1127}
1128
1129static struct ttm_bo_driver amdgpu_bo_driver = {
1130 .ttm_tt_create = &amdgpu_ttm_tt_create,
1131 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1132 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1133 .invalidate_caches = &amdgpu_invalidate_caches,
1134 .init_mem_type = &amdgpu_init_mem_type,
1135 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1136 .evict_flags = &amdgpu_evict_flags,
1137 .move = &amdgpu_bo_move,
1138 .verify_access = &amdgpu_verify_access,
1139 .move_notify = &amdgpu_bo_move_notify,
1140 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1141 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1142 .io_mem_free = &amdgpu_ttm_io_mem_free,
1143 .lru_removal = &amdgpu_ttm_lru_removal,
1144 .lru_tail = &amdgpu_ttm_lru_tail,
1145 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1146};
1147
1148int amdgpu_ttm_init(struct amdgpu_device *adev)
1149{
1150 unsigned i, j;
1151 int r;
1152
1153 r = amdgpu_ttm_global_init(adev);
1154 if (r) {
1155 return r;
1156 }
1157 /* No others user of address space so set it to 0 */
1158 r = ttm_bo_device_init(&adev->mman.bdev,
1159 adev->mman.bo_global_ref.ref.object,
1160 &amdgpu_bo_driver,
1161 adev->ddev->anon_inode->i_mapping,
1162 DRM_FILE_PAGE_OFFSET,
1163 adev->need_dma32);
1164 if (r) {
1165 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1166 return r;
1167 }
1168
1169 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1170 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1171
1172 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1173 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1174 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1175 }
1176
1177 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1178 adev->mman.guard.lru[j] = NULL;
1179 adev->mman.guard.swap_lru = NULL;
1180
1181 adev->mman.initialized = true;
1182 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1183 adev->mc.real_vram_size >> PAGE_SHIFT);
1184 if (r) {
1185 DRM_ERROR("Failed initializing VRAM heap.\n");
1186 return r;
1187 }
1188 /* Change the size here instead of the init above so only lpfn is affected */
1189 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1190
1191 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1192 AMDGPU_GEM_DOMAIN_VRAM,
1193 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1194 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1195 NULL, NULL, &adev->stollen_vga_memory);
1196 if (r) {
1197 return r;
1198 }
1199 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1200 if (r)
1201 return r;
1202 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1203 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1204 if (r) {
1205 amdgpu_bo_unref(&adev->stollen_vga_memory);
1206 return r;
1207 }
1208 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1209 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1210 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1211 adev->mc.gtt_size >> PAGE_SHIFT);
1212 if (r) {
1213 DRM_ERROR("Failed initializing GTT heap.\n");
1214 return r;
1215 }
1216 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1217 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1218
1219 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1220 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1221 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1222 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1223 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1224 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1225 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1226 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1227 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1228 /* GDS Memory */
1229 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1230 adev->gds.mem.total_size >> PAGE_SHIFT);
1231 if (r) {
1232 DRM_ERROR("Failed initializing GDS heap.\n");
1233 return r;
1234 }
1235
1236 /* GWS */
1237 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1238 adev->gds.gws.total_size >> PAGE_SHIFT);
1239 if (r) {
1240 DRM_ERROR("Failed initializing gws heap.\n");
1241 return r;
1242 }
1243
1244 /* OA */
1245 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1246 adev->gds.oa.total_size >> PAGE_SHIFT);
1247 if (r) {
1248 DRM_ERROR("Failed initializing oa heap.\n");
1249 return r;
1250 }
1251
1252 r = amdgpu_ttm_debugfs_init(adev);
1253 if (r) {
1254 DRM_ERROR("Failed to init debugfs\n");
1255 return r;
1256 }
1257 return 0;
1258}
1259
1260void amdgpu_ttm_fini(struct amdgpu_device *adev)
1261{
1262 int r;
1263
1264 if (!adev->mman.initialized)
1265 return;
1266 amdgpu_ttm_debugfs_fini(adev);
1267 if (adev->stollen_vga_memory) {
1268 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1269 if (r == 0) {
1270 amdgpu_bo_unpin(adev->stollen_vga_memory);
1271 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1272 }
1273 amdgpu_bo_unref(&adev->stollen_vga_memory);
1274 }
1275 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1276 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1277 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1278 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1279 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1280 ttm_bo_device_release(&adev->mman.bdev);
1281 amdgpu_gart_fini(adev);
1282 amdgpu_ttm_global_fini(adev);
1283 adev->mman.initialized = false;
1284 DRM_INFO("amdgpu: ttm finalized\n");
1285}
1286
1287/* this should only be called at bootup or when userspace
1288 * isn't running */
1289void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1290{
1291 struct ttm_mem_type_manager *man;
1292
1293 if (!adev->mman.initialized)
1294 return;
1295
1296 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1297 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1298 man->size = size >> PAGE_SHIFT;
1299}
1300
1301int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1302{
1303 struct drm_file *file_priv;
1304 struct amdgpu_device *adev;
1305
1306 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1307 return -EINVAL;
1308
1309 file_priv = filp->private_data;
1310 adev = file_priv->minor->dev->dev_private;
1311 if (adev == NULL)
1312 return -EINVAL;
1313
1314 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1315}
1316
1317int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1318 uint64_t src_offset,
1319 uint64_t dst_offset,
1320 uint32_t byte_count,
1321 struct reservation_object *resv,
1322 struct dma_fence **fence, bool direct_submit)
1323{
1324 struct amdgpu_device *adev = ring->adev;
1325 struct amdgpu_job *job;
1326
1327 uint32_t max_bytes;
1328 unsigned num_loops, num_dw;
1329 unsigned i;
1330 int r;
1331
1332 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1333 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1334 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1335
1336 /* for IB padding */
1337 while (num_dw & 0x7)
1338 num_dw++;
1339
1340 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1341 if (r)
1342 return r;
1343
1344 if (resv) {
1345 r = amdgpu_sync_resv(adev, &job->sync, resv,
1346 AMDGPU_FENCE_OWNER_UNDEFINED);
1347 if (r) {
1348 DRM_ERROR("sync failed (%d).\n", r);
1349 goto error_free;
1350 }
1351 }
1352
1353 for (i = 0; i < num_loops; i++) {
1354 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1355
1356 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1357 dst_offset, cur_size_in_bytes);
1358
1359 src_offset += cur_size_in_bytes;
1360 dst_offset += cur_size_in_bytes;
1361 byte_count -= cur_size_in_bytes;
1362 }
1363
1364 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1365 WARN_ON(job->ibs[0].length_dw > num_dw);
1366 if (direct_submit) {
1367 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1368 NULL, NULL, fence);
1369 job->fence = dma_fence_get(*fence);
1370 if (r)
1371 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1372 amdgpu_job_free(job);
1373 } else {
1374 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1375 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1376 if (r)
1377 goto error_free;
1378 }
1379
1380 return r;
1381
1382error_free:
1383 amdgpu_job_free(job);
1384 return r;
1385}
1386
1387int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1388 uint32_t src_data,
1389 struct reservation_object *resv,
1390 struct dma_fence **fence)
1391{
1392 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1393 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1394 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1395
1396 struct drm_mm_node *mm_node;
1397 unsigned long num_pages;
1398 unsigned int num_loops, num_dw;
1399
1400 struct amdgpu_job *job;
1401 int r;
1402
1403 if (!ring->ready) {
1404 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1405 return -EINVAL;
1406 }
1407
1408 num_pages = bo->tbo.num_pages;
1409 mm_node = bo->tbo.mem.mm_node;
1410 num_loops = 0;
1411 while (num_pages) {
1412 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1413
1414 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1415 num_pages -= mm_node->size;
1416 ++mm_node;
1417 }
1418 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1419
1420 /* for IB padding */
1421 num_dw += 64;
1422
1423 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1424 if (r)
1425 return r;
1426
1427 if (resv) {
1428 r = amdgpu_sync_resv(adev, &job->sync, resv,
1429 AMDGPU_FENCE_OWNER_UNDEFINED);
1430 if (r) {
1431 DRM_ERROR("sync failed (%d).\n", r);
1432 goto error_free;
1433 }
1434 }
1435
1436 num_pages = bo->tbo.num_pages;
1437 mm_node = bo->tbo.mem.mm_node;
1438
1439 while (num_pages) {
1440 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1441 uint64_t dst_addr;
1442
1443 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1444 &bo->tbo.mem, &dst_addr);
1445 if (r)
1446 return r;
1447
1448 while (byte_count) {
1449 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1450
1451 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1452 dst_addr, cur_size_in_bytes);
1453
1454 dst_addr += cur_size_in_bytes;
1455 byte_count -= cur_size_in_bytes;
1456 }
1457
1458 num_pages -= mm_node->size;
1459 ++mm_node;
1460 }
1461
1462 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1463 WARN_ON(job->ibs[0].length_dw > num_dw);
1464 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1465 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1466 if (r)
1467 goto error_free;
1468
1469 return 0;
1470
1471error_free:
1472 amdgpu_job_free(job);
1473 return r;
1474}
1475
1476#if defined(CONFIG_DEBUG_FS)
1477
1478static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1479{
1480 struct drm_info_node *node = (struct drm_info_node *)m->private;
1481 unsigned ttm_pl = *(int *)node->info_ent->data;
1482 struct drm_device *dev = node->minor->dev;
1483 struct amdgpu_device *adev = dev->dev_private;
1484 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1485 int ret;
1486 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1487
1488 spin_lock(&glob->lru_lock);
1489 ret = drm_mm_dump_table(m, mm);
1490 spin_unlock(&glob->lru_lock);
1491 if (ttm_pl == TTM_PL_VRAM)
1492 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1493 adev->mman.bdev.man[ttm_pl].size,
1494 (u64)atomic64_read(&adev->vram_usage) >> 20,
1495 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1496 return ret;
1497}
1498
1499static int ttm_pl_vram = TTM_PL_VRAM;
1500static int ttm_pl_tt = TTM_PL_TT;
1501
1502static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1503 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1504 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1505 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1506#ifdef CONFIG_SWIOTLB
1507 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1508#endif
1509};
1510
1511static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1512 size_t size, loff_t *pos)
1513{
1514 struct amdgpu_device *adev = file_inode(f)->i_private;
1515 ssize_t result = 0;
1516 int r;
1517
1518 if (size & 0x3 || *pos & 0x3)
1519 return -EINVAL;
1520
1521 while (size) {
1522 unsigned long flags;
1523 uint32_t value;
1524
1525 if (*pos >= adev->mc.mc_vram_size)
1526 return result;
1527
1528 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1529 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1530 WREG32(mmMM_INDEX_HI, *pos >> 31);
1531 value = RREG32(mmMM_DATA);
1532 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1533
1534 r = put_user(value, (uint32_t *)buf);
1535 if (r)
1536 return r;
1537
1538 result += 4;
1539 buf += 4;
1540 *pos += 4;
1541 size -= 4;
1542 }
1543
1544 return result;
1545}
1546
1547static const struct file_operations amdgpu_ttm_vram_fops = {
1548 .owner = THIS_MODULE,
1549 .read = amdgpu_ttm_vram_read,
1550 .llseek = default_llseek
1551};
1552
1553#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1554
1555static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1556 size_t size, loff_t *pos)
1557{
1558 struct amdgpu_device *adev = file_inode(f)->i_private;
1559 ssize_t result = 0;
1560 int r;
1561
1562 while (size) {
1563 loff_t p = *pos / PAGE_SIZE;
1564 unsigned off = *pos & ~PAGE_MASK;
1565 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1566 struct page *page;
1567 void *ptr;
1568
1569 if (p >= adev->gart.num_cpu_pages)
1570 return result;
1571
1572 page = adev->gart.pages[p];
1573 if (page) {
1574 ptr = kmap(page);
1575 ptr += off;
1576
1577 r = copy_to_user(buf, ptr, cur_size);
1578 kunmap(adev->gart.pages[p]);
1579 } else
1580 r = clear_user(buf, cur_size);
1581
1582 if (r)
1583 return -EFAULT;
1584
1585 result += cur_size;
1586 buf += cur_size;
1587 *pos += cur_size;
1588 size -= cur_size;
1589 }
1590
1591 return result;
1592}
1593
1594static const struct file_operations amdgpu_ttm_gtt_fops = {
1595 .owner = THIS_MODULE,
1596 .read = amdgpu_ttm_gtt_read,
1597 .llseek = default_llseek
1598};
1599
1600#endif
1601
1602#endif
1603
1604static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1605{
1606#if defined(CONFIG_DEBUG_FS)
1607 unsigned count;
1608
1609 struct drm_minor *minor = adev->ddev->primary;
1610 struct dentry *ent, *root = minor->debugfs_root;
1611
1612 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1613 adev, &amdgpu_ttm_vram_fops);
1614 if (IS_ERR(ent))
1615 return PTR_ERR(ent);
1616 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1617 adev->mman.vram = ent;
1618
1619#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1620 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1621 adev, &amdgpu_ttm_gtt_fops);
1622 if (IS_ERR(ent))
1623 return PTR_ERR(ent);
1624 i_size_write(ent->d_inode, adev->mc.gtt_size);
1625 adev->mman.gtt = ent;
1626
1627#endif
1628 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1629
1630#ifdef CONFIG_SWIOTLB
1631 if (!swiotlb_nr_tbl())
1632 --count;
1633#endif
1634
1635 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1636#else
1637
1638 return 0;
1639#endif
1640}
1641
1642static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1643{
1644#if defined(CONFIG_DEBUG_FS)
1645
1646 debugfs_remove(adev->mman.vram);
1647 adev->mman.vram = NULL;
1648
1649#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1650 debugfs_remove(adev->mman.gtt);
1651 adev->mman.gtt = NULL;
1652#endif
1653
1654#endif
1655}