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1/*
2 * Broadcom Kona GPIO Driver
3 *
4 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
5 * Copyright (C) 2012-2014 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/init.h>
24#include <linux/irqdomain.h>
25#include <linux/irqchip/chained_irq.h>
26
27#define BCM_GPIO_PASSWD 0x00a5a501
28#define GPIO_PER_BANK 32
29#define GPIO_MAX_BANK_NUM 8
30
31#define GPIO_BANK(gpio) ((gpio) >> 5)
32#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
33
34/* There is a GPIO control register for each GPIO */
35#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
36
37/* The remaining registers are per GPIO bank */
38#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
39#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
40#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
41#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
42#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
43#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
44#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
45#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
46
47#define GPIO_GPPWR_OFFSET 0x00000520
48
49#define GPIO_GPCTR0_DBR_SHIFT 5
50#define GPIO_GPCTR0_DBR_MASK 0x000001e0
51
52#define GPIO_GPCTR0_ITR_SHIFT 3
53#define GPIO_GPCTR0_ITR_MASK 0x00000018
54#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
55#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
56#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
57
58#define GPIO_GPCTR0_IOTR_MASK 0x00000001
59#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
60#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
61
62#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
63
64#define LOCK_CODE 0xffffffff
65#define UNLOCK_CODE 0x00000000
66
67struct bcm_kona_gpio {
68 void __iomem *reg_base;
69 int num_bank;
70 spinlock_t lock;
71 struct gpio_chip gpio_chip;
72 struct irq_domain *irq_domain;
73 struct bcm_kona_gpio_bank *banks;
74 struct platform_device *pdev;
75};
76
77struct bcm_kona_gpio_bank {
78 int id;
79 int irq;
80 /* Used in the interrupt handler */
81 struct bcm_kona_gpio *kona_gpio;
82};
83
84static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
85 int bank_id, u32 lockcode)
86{
87 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
88 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
89}
90
91static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
92 unsigned gpio)
93{
94 u32 val;
95 unsigned long flags;
96 int bank_id = GPIO_BANK(gpio);
97
98 spin_lock_irqsave(&kona_gpio->lock, flags);
99
100 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
101 val |= BIT(gpio);
102 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
103
104 spin_unlock_irqrestore(&kona_gpio->lock, flags);
105}
106
107static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
108 unsigned gpio)
109{
110 u32 val;
111 unsigned long flags;
112 int bank_id = GPIO_BANK(gpio);
113
114 spin_lock_irqsave(&kona_gpio->lock, flags);
115
116 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
117 val &= ~BIT(gpio);
118 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
119
120 spin_unlock_irqrestore(&kona_gpio->lock, flags);
121}
122
123static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
124{
125 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
126 void __iomem *reg_base = kona_gpio->reg_base;
127 u32 val;
128
129 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
130 return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
131}
132
133static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
134{
135 struct bcm_kona_gpio *kona_gpio;
136 void __iomem *reg_base;
137 int bank_id = GPIO_BANK(gpio);
138 int bit = GPIO_BIT(gpio);
139 u32 val, reg_offset;
140 unsigned long flags;
141
142 kona_gpio = gpiochip_get_data(chip);
143 reg_base = kona_gpio->reg_base;
144 spin_lock_irqsave(&kona_gpio->lock, flags);
145
146 /* this function only applies to output pin */
147 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
148 goto out;
149
150 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
151
152 val = readl(reg_base + reg_offset);
153 val |= BIT(bit);
154 writel(val, reg_base + reg_offset);
155
156out:
157 spin_unlock_irqrestore(&kona_gpio->lock, flags);
158}
159
160static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
161{
162 struct bcm_kona_gpio *kona_gpio;
163 void __iomem *reg_base;
164 int bank_id = GPIO_BANK(gpio);
165 int bit = GPIO_BIT(gpio);
166 u32 val, reg_offset;
167 unsigned long flags;
168
169 kona_gpio = gpiochip_get_data(chip);
170 reg_base = kona_gpio->reg_base;
171 spin_lock_irqsave(&kona_gpio->lock, flags);
172
173 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
174 reg_offset = GPIO_IN_STATUS(bank_id);
175 else
176 reg_offset = GPIO_OUT_STATUS(bank_id);
177
178 /* read the GPIO bank status */
179 val = readl(reg_base + reg_offset);
180
181 spin_unlock_irqrestore(&kona_gpio->lock, flags);
182
183 /* return the specified bit status */
184 return !!(val & BIT(bit));
185}
186
187static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
188{
189 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
190
191 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
192 return 0;
193}
194
195static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
196{
197 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
198
199 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
200}
201
202static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
203{
204 struct bcm_kona_gpio *kona_gpio;
205 void __iomem *reg_base;
206 u32 val;
207 unsigned long flags;
208
209 kona_gpio = gpiochip_get_data(chip);
210 reg_base = kona_gpio->reg_base;
211 spin_lock_irqsave(&kona_gpio->lock, flags);
212
213 val = readl(reg_base + GPIO_CONTROL(gpio));
214 val &= ~GPIO_GPCTR0_IOTR_MASK;
215 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
216 writel(val, reg_base + GPIO_CONTROL(gpio));
217
218 spin_unlock_irqrestore(&kona_gpio->lock, flags);
219
220 return 0;
221}
222
223static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
224 unsigned gpio, int value)
225{
226 struct bcm_kona_gpio *kona_gpio;
227 void __iomem *reg_base;
228 int bank_id = GPIO_BANK(gpio);
229 int bit = GPIO_BIT(gpio);
230 u32 val, reg_offset;
231 unsigned long flags;
232
233 kona_gpio = gpiochip_get_data(chip);
234 reg_base = kona_gpio->reg_base;
235 spin_lock_irqsave(&kona_gpio->lock, flags);
236
237 val = readl(reg_base + GPIO_CONTROL(gpio));
238 val &= ~GPIO_GPCTR0_IOTR_MASK;
239 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
240 writel(val, reg_base + GPIO_CONTROL(gpio));
241 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
242
243 val = readl(reg_base + reg_offset);
244 val |= BIT(bit);
245 writel(val, reg_base + reg_offset);
246
247 spin_unlock_irqrestore(&kona_gpio->lock, flags);
248
249 return 0;
250}
251
252static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
253{
254 struct bcm_kona_gpio *kona_gpio;
255
256 kona_gpio = gpiochip_get_data(chip);
257 if (gpio >= kona_gpio->gpio_chip.ngpio)
258 return -ENXIO;
259 return irq_create_mapping(kona_gpio->irq_domain, gpio);
260}
261
262static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
263 unsigned debounce)
264{
265 struct bcm_kona_gpio *kona_gpio;
266 void __iomem *reg_base;
267 u32 val, res;
268 unsigned long flags;
269
270 kona_gpio = gpiochip_get_data(chip);
271 reg_base = kona_gpio->reg_base;
272 /* debounce must be 1-128ms (or 0) */
273 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
274 dev_err(chip->parent, "Debounce value %u not in range\n",
275 debounce);
276 return -EINVAL;
277 }
278
279 /* calculate debounce bit value */
280 if (debounce != 0) {
281 /* Convert to ms */
282 debounce /= 1000;
283 /* find the MSB */
284 res = fls(debounce) - 1;
285 /* Check if MSB-1 is set (round up or down) */
286 if (res > 0 && (debounce & BIT(res - 1)))
287 res++;
288 }
289
290 /* spin lock for read-modify-write of the GPIO register */
291 spin_lock_irqsave(&kona_gpio->lock, flags);
292
293 val = readl(reg_base + GPIO_CONTROL(gpio));
294 val &= ~GPIO_GPCTR0_DBR_MASK;
295
296 if (debounce == 0) {
297 /* disable debounce */
298 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
299 } else {
300 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
301 (res << GPIO_GPCTR0_DBR_SHIFT);
302 }
303
304 writel(val, reg_base + GPIO_CONTROL(gpio));
305
306 spin_unlock_irqrestore(&kona_gpio->lock, flags);
307
308 return 0;
309}
310
311static const struct gpio_chip template_chip = {
312 .label = "bcm-kona-gpio",
313 .owner = THIS_MODULE,
314 .request = bcm_kona_gpio_request,
315 .free = bcm_kona_gpio_free,
316 .get_direction = bcm_kona_gpio_get_dir,
317 .direction_input = bcm_kona_gpio_direction_input,
318 .get = bcm_kona_gpio_get,
319 .direction_output = bcm_kona_gpio_direction_output,
320 .set = bcm_kona_gpio_set,
321 .set_debounce = bcm_kona_gpio_set_debounce,
322 .to_irq = bcm_kona_gpio_to_irq,
323 .base = 0,
324};
325
326static void bcm_kona_gpio_irq_ack(struct irq_data *d)
327{
328 struct bcm_kona_gpio *kona_gpio;
329 void __iomem *reg_base;
330 unsigned gpio = d->hwirq;
331 int bank_id = GPIO_BANK(gpio);
332 int bit = GPIO_BIT(gpio);
333 u32 val;
334 unsigned long flags;
335
336 kona_gpio = irq_data_get_irq_chip_data(d);
337 reg_base = kona_gpio->reg_base;
338 spin_lock_irqsave(&kona_gpio->lock, flags);
339
340 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
341 val |= BIT(bit);
342 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
343
344 spin_unlock_irqrestore(&kona_gpio->lock, flags);
345}
346
347static void bcm_kona_gpio_irq_mask(struct irq_data *d)
348{
349 struct bcm_kona_gpio *kona_gpio;
350 void __iomem *reg_base;
351 unsigned gpio = d->hwirq;
352 int bank_id = GPIO_BANK(gpio);
353 int bit = GPIO_BIT(gpio);
354 u32 val;
355 unsigned long flags;
356
357 kona_gpio = irq_data_get_irq_chip_data(d);
358 reg_base = kona_gpio->reg_base;
359 spin_lock_irqsave(&kona_gpio->lock, flags);
360
361 val = readl(reg_base + GPIO_INT_MASK(bank_id));
362 val |= BIT(bit);
363 writel(val, reg_base + GPIO_INT_MASK(bank_id));
364
365 spin_unlock_irqrestore(&kona_gpio->lock, flags);
366}
367
368static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
369{
370 struct bcm_kona_gpio *kona_gpio;
371 void __iomem *reg_base;
372 unsigned gpio = d->hwirq;
373 int bank_id = GPIO_BANK(gpio);
374 int bit = GPIO_BIT(gpio);
375 u32 val;
376 unsigned long flags;
377
378 kona_gpio = irq_data_get_irq_chip_data(d);
379 reg_base = kona_gpio->reg_base;
380 spin_lock_irqsave(&kona_gpio->lock, flags);
381
382 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
383 val |= BIT(bit);
384 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
385
386 spin_unlock_irqrestore(&kona_gpio->lock, flags);
387}
388
389static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
390{
391 struct bcm_kona_gpio *kona_gpio;
392 void __iomem *reg_base;
393 unsigned gpio = d->hwirq;
394 u32 lvl_type;
395 u32 val;
396 unsigned long flags;
397
398 kona_gpio = irq_data_get_irq_chip_data(d);
399 reg_base = kona_gpio->reg_base;
400 switch (type & IRQ_TYPE_SENSE_MASK) {
401 case IRQ_TYPE_EDGE_RISING:
402 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
403 break;
404
405 case IRQ_TYPE_EDGE_FALLING:
406 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
407 break;
408
409 case IRQ_TYPE_EDGE_BOTH:
410 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
411 break;
412
413 case IRQ_TYPE_LEVEL_HIGH:
414 case IRQ_TYPE_LEVEL_LOW:
415 /* BCM GPIO doesn't support level triggering */
416 default:
417 dev_err(kona_gpio->gpio_chip.parent,
418 "Invalid BCM GPIO irq type 0x%x\n", type);
419 return -EINVAL;
420 }
421
422 spin_lock_irqsave(&kona_gpio->lock, flags);
423
424 val = readl(reg_base + GPIO_CONTROL(gpio));
425 val &= ~GPIO_GPCTR0_ITR_MASK;
426 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
427 writel(val, reg_base + GPIO_CONTROL(gpio));
428
429 spin_unlock_irqrestore(&kona_gpio->lock, flags);
430
431 return 0;
432}
433
434static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
435{
436 void __iomem *reg_base;
437 int bit, bank_id;
438 unsigned long sta;
439 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
440 struct irq_chip *chip = irq_desc_get_chip(desc);
441
442 chained_irq_enter(chip, desc);
443
444 /*
445 * For bank interrupts, we can't use chip_data to store the kona_gpio
446 * pointer, since GIC needs it for its own purposes. Therefore, we get
447 * our pointer from the bank structure.
448 */
449 reg_base = bank->kona_gpio->reg_base;
450 bank_id = bank->id;
451
452 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
453 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
454 for_each_set_bit(bit, &sta, 32) {
455 int hwirq = GPIO_PER_BANK * bank_id + bit;
456 int child_irq =
457 irq_find_mapping(bank->kona_gpio->irq_domain,
458 hwirq);
459 /*
460 * Clear interrupt before handler is called so we don't
461 * miss any interrupt occurred during executing them.
462 */
463 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
464 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
465 /* Invoke interrupt handler */
466 generic_handle_irq(child_irq);
467 }
468 }
469
470 chained_irq_exit(chip, desc);
471}
472
473static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
474{
475 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
476
477 if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
478 dev_err(kona_gpio->gpio_chip.parent,
479 "unable to lock HW IRQ %lu for IRQ\n",
480 d->hwirq);
481 return -EINVAL;
482 }
483 return 0;
484}
485
486static void bcm_kona_gpio_irq_relres(struct irq_data *d)
487{
488 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
489
490 gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
491}
492
493static struct irq_chip bcm_gpio_irq_chip = {
494 .name = "bcm-kona-gpio",
495 .irq_ack = bcm_kona_gpio_irq_ack,
496 .irq_mask = bcm_kona_gpio_irq_mask,
497 .irq_unmask = bcm_kona_gpio_irq_unmask,
498 .irq_set_type = bcm_kona_gpio_irq_set_type,
499 .irq_request_resources = bcm_kona_gpio_irq_reqres,
500 .irq_release_resources = bcm_kona_gpio_irq_relres,
501};
502
503static struct of_device_id const bcm_kona_gpio_of_match[] = {
504 { .compatible = "brcm,kona-gpio" },
505 {}
506};
507
508/*
509 * This lock class tells lockdep that GPIO irqs are in a different
510 * category than their parents, so it won't report false recursion.
511 */
512static struct lock_class_key gpio_lock_class;
513
514static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
515 irq_hw_number_t hwirq)
516{
517 int ret;
518
519 ret = irq_set_chip_data(irq, d->host_data);
520 if (ret < 0)
521 return ret;
522 irq_set_lockdep_class(irq, &gpio_lock_class);
523 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
524 irq_set_noprobe(irq);
525
526 return 0;
527}
528
529static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
530{
531 irq_set_chip_and_handler(irq, NULL, NULL);
532 irq_set_chip_data(irq, NULL);
533}
534
535static const struct irq_domain_ops bcm_kona_irq_ops = {
536 .map = bcm_kona_gpio_irq_map,
537 .unmap = bcm_kona_gpio_irq_unmap,
538 .xlate = irq_domain_xlate_twocell,
539};
540
541static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
542{
543 void __iomem *reg_base;
544 int i;
545
546 reg_base = kona_gpio->reg_base;
547 /* disable interrupts and clear status */
548 for (i = 0; i < kona_gpio->num_bank; i++) {
549 /* Unlock the entire bank first */
550 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
551 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
552 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
553 /* Now re-lock the bank */
554 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
555 }
556}
557
558static int bcm_kona_gpio_probe(struct platform_device *pdev)
559{
560 struct device *dev = &pdev->dev;
561 const struct of_device_id *match;
562 struct resource *res;
563 struct bcm_kona_gpio_bank *bank;
564 struct bcm_kona_gpio *kona_gpio;
565 struct gpio_chip *chip;
566 int ret;
567 int i;
568
569 match = of_match_device(bcm_kona_gpio_of_match, dev);
570 if (!match) {
571 dev_err(dev, "Failed to find gpio controller\n");
572 return -ENODEV;
573 }
574
575 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
576 if (!kona_gpio)
577 return -ENOMEM;
578
579 kona_gpio->gpio_chip = template_chip;
580 chip = &kona_gpio->gpio_chip;
581 kona_gpio->num_bank = of_irq_count(dev->of_node);
582 if (kona_gpio->num_bank == 0) {
583 dev_err(dev, "Couldn't determine # GPIO banks\n");
584 return -ENOENT;
585 }
586 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
587 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
588 GPIO_MAX_BANK_NUM);
589 return -ENXIO;
590 }
591 kona_gpio->banks = devm_kzalloc(dev,
592 kona_gpio->num_bank *
593 sizeof(*kona_gpio->banks), GFP_KERNEL);
594 if (!kona_gpio->banks)
595 return -ENOMEM;
596
597 kona_gpio->pdev = pdev;
598 platform_set_drvdata(pdev, kona_gpio);
599 chip->of_node = dev->of_node;
600 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
601
602 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
603 chip->ngpio,
604 &bcm_kona_irq_ops,
605 kona_gpio);
606 if (!kona_gpio->irq_domain) {
607 dev_err(dev, "Couldn't allocate IRQ domain\n");
608 return -ENXIO;
609 }
610
611 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
612 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
613 if (IS_ERR(kona_gpio->reg_base)) {
614 ret = -ENXIO;
615 goto err_irq_domain;
616 }
617
618 for (i = 0; i < kona_gpio->num_bank; i++) {
619 bank = &kona_gpio->banks[i];
620 bank->id = i;
621 bank->irq = platform_get_irq(pdev, i);
622 bank->kona_gpio = kona_gpio;
623 if (bank->irq < 0) {
624 dev_err(dev, "Couldn't get IRQ for bank %d", i);
625 ret = -ENOENT;
626 goto err_irq_domain;
627 }
628 }
629
630 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
631
632 bcm_kona_gpio_reset(kona_gpio);
633
634 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
635 if (ret < 0) {
636 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
637 goto err_irq_domain;
638 }
639 for (i = 0; i < kona_gpio->num_bank; i++) {
640 bank = &kona_gpio->banks[i];
641 irq_set_chained_handler_and_data(bank->irq,
642 bcm_kona_gpio_irq_handler,
643 bank);
644 }
645
646 spin_lock_init(&kona_gpio->lock);
647
648 return 0;
649
650err_irq_domain:
651 irq_domain_remove(kona_gpio->irq_domain);
652
653 return ret;
654}
655
656static struct platform_driver bcm_kona_gpio_driver = {
657 .driver = {
658 .name = "bcm-kona-gpio",
659 .of_match_table = bcm_kona_gpio_of_match,
660 },
661 .probe = bcm_kona_gpio_probe,
662};
663builtin_platform_driver(bcm_kona_gpio_driver);