1/*
  2 * Copyright (C) Maxime Coquelin 2015
  3 * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
  4 * License terms:  GNU General Public License (GPL), version 2
  5 *
  6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
  7 */
  8
  9#include <linux/kernel.h>
 10#include <linux/clocksource.h>
 11#include <linux/clockchips.h>
 12#include <linux/irq.h>
 13#include <linux/interrupt.h>
 14#include <linux/of.h>
 15#include <linux/of_address.h>
 16#include <linux/of_irq.h>
 17#include <linux/clk.h>
 18#include <linux/reset.h>
 19
 20#define TIM_CR1		0x00
 21#define TIM_DIER	0x0c
 22#define TIM_SR		0x10
 23#define TIM_EGR		0x14
 24#define TIM_PSC		0x28
 25#define TIM_ARR		0x2c
 26
 27#define TIM_CR1_CEN	BIT(0)
 28#define TIM_CR1_OPM	BIT(3)
 29#define TIM_CR1_ARPE	BIT(7)
 30
 31#define TIM_DIER_UIE	BIT(0)
 32
 33#define TIM_SR_UIF	BIT(0)
 34
 35#define TIM_EGR_UG	BIT(0)
 36
 37struct stm32_clock_event_ddata {
 38	struct clock_event_device evtdev;
 39	unsigned periodic_top;
 40	void __iomem *base;
 41};
 42
 43static int stm32_clock_event_shutdown(struct clock_event_device *evtdev)
 44{
 45	struct stm32_clock_event_ddata *data =
 46		container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
 47	void *base = data->base;
 48
 49	writel_relaxed(0, base + TIM_CR1);
 50	return 0;
 51}
 52
 53static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)
 54{
 55	struct stm32_clock_event_ddata *data =
 56		container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
 57	void *base = data->base;
 58
 59	writel_relaxed(data->periodic_top, base + TIM_ARR);
 60	writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);
 61	return 0;
 62}
 63
 64static int stm32_clock_event_set_next_event(unsigned long evt,
 65					    struct clock_event_device *evtdev)
 66{
 67	struct stm32_clock_event_ddata *data =
 68		container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
 69
 70	writel_relaxed(evt, data->base + TIM_ARR);
 71	writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,
 72		       data->base + TIM_CR1);
 73
 74	return 0;
 75}
 76
 77static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
 78{
 79	struct stm32_clock_event_ddata *data = dev_id;
 80
 81	writel_relaxed(0, data->base + TIM_SR);
 82
 83	data->evtdev.event_handler(&data->evtdev);
 84
 85	return IRQ_HANDLED;
 86}
 87
 88static struct stm32_clock_event_ddata clock_event_ddata = {
 89	.evtdev = {
 90		.name = "stm32 clockevent",
 91		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 92		.set_state_shutdown = stm32_clock_event_shutdown,
 93		.set_state_periodic = stm32_clock_event_set_periodic,
 94		.set_state_oneshot = stm32_clock_event_shutdown,
 95		.tick_resume = stm32_clock_event_shutdown,
 96		.set_next_event = stm32_clock_event_set_next_event,
 97		.rating = 200,
 98	},
 99};
100
101static int __init stm32_clockevent_init(struct device_node *np)
102{
103	struct stm32_clock_event_ddata *data = &clock_event_ddata;
104	struct clk *clk;
105	struct reset_control *rstc;
106	unsigned long rate, max_delta;
107	int irq, ret, bits, prescaler = 1;
108
109	clk = of_clk_get(np, 0);
110	if (IS_ERR(clk)) {
111		ret = PTR_ERR(clk);
112		pr_err("failed to get clock for clockevent (%d)\n", ret);
113		goto err_clk_get;
114	}
115
116	ret = clk_prepare_enable(clk);
117	if (ret) {
118		pr_err("failed to enable timer clock for clockevent (%d)\n",
119		       ret);
120		goto err_clk_enable;
121	}
122
123	rate = clk_get_rate(clk);
124
125	rstc = of_reset_control_get(np, NULL);
126	if (!IS_ERR(rstc)) {
127		reset_control_assert(rstc);
128		reset_control_deassert(rstc);
129	}
130
131	data->base = of_iomap(np, 0);
132	if (!data->base) {
133		ret = -ENXIO;
134		pr_err("failed to map registers for clockevent\n");
135		goto err_iomap;
136	}
137
138	irq = irq_of_parse_and_map(np, 0);
139	if (!irq) {
140		ret = -EINVAL;
141		pr_err("%s: failed to get irq.\n", np->full_name);
142		goto err_get_irq;
143	}
144
145	/* Detect whether the timer is 16 or 32 bits */
146	writel_relaxed(~0U, data->base + TIM_ARR);
147	max_delta = readl_relaxed(data->base + TIM_ARR);
148	if (max_delta == ~0U) {
149		prescaler = 1;
150		bits = 32;
151	} else {
152		prescaler = 1024;
153		bits = 16;
154	}
155	writel_relaxed(0, data->base + TIM_ARR);
156
157	writel_relaxed(prescaler - 1, data->base + TIM_PSC);
158	writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);
159	writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);
160	writel_relaxed(0, data->base + TIM_SR);
161
162	data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);
163
164	clockevents_config_and_register(&data->evtdev,
165					DIV_ROUND_CLOSEST(rate, prescaler),
166					0x1, max_delta);
167
168	ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,
169			"stm32 clockevent", data);
170	if (ret) {
171		pr_err("%s: failed to request irq.\n", np->full_name);
172		goto err_get_irq;
173	}
174
175	pr_info("%s: STM32 clockevent driver initialized (%d bits)\n",
176			np->full_name, bits);
177
178	return ret;
179
180err_get_irq:
181	iounmap(data->base);
182err_iomap:
183	clk_disable_unprepare(clk);
184err_clk_enable:
185	clk_put(clk);
186err_clk_get:
187	return ret;
188}
189
190CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init);