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1/*
2 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
3 * We wrap the custom interface from <asm/hardware/icst.h> into the generic
4 * clock framework.
5 *
6 * Copyright (C) 2012-2015 Linus Walleij
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO: when all ARM reference designs are migrated to generic clocks, the
13 * ICST clock code from the ARM tree should probably be merged into this
14 * file.
15 */
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/export.h>
19#include <linux/err.h>
20#include <linux/clk-provider.h>
21#include <linux/io.h>
22#include <linux/regmap.h>
23#include <linux/mfd/syscon.h>
24
25#include "clk-icst.h"
26
27/* Magic unlocking token used on all Versatile boards */
28#define VERSATILE_LOCK_VAL 0xA05F
29
30#define VERSATILE_AUX_OSC_BITS 0x7FFFF
31#define INTEGRATOR_AP_CM_BITS 0xFF
32#define INTEGRATOR_AP_SYS_BITS 0xFF
33#define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
34#define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
35
36#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
37
38/**
39 * enum icst_control_type - the type of ICST control register
40 */
41enum icst_control_type {
42 ICST_VERSATILE, /* The standard type, all control bits available */
43 ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */
44 ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */
45 ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */
46 ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */
47 ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */
48};
49
50/**
51 * struct clk_icst - ICST VCO clock wrapper
52 * @hw: corresponding clock hardware entry
53 * @vcoreg: VCO register address
54 * @lockreg: VCO lock register address
55 * @params: parameters for this ICST instance
56 * @rate: current rate
57 * @ctype: the type of control register for the ICST
58 */
59struct clk_icst {
60 struct clk_hw hw;
61 struct regmap *map;
62 u32 vcoreg_off;
63 u32 lockreg_off;
64 struct icst_params *params;
65 unsigned long rate;
66 enum icst_control_type ctype;
67};
68
69#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
70
71/**
72 * vco_get() - get ICST VCO settings from a certain ICST
73 * @icst: the ICST clock to get
74 * @vco: the VCO struct to return the value in
75 */
76static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
77{
78 u32 val;
79 int ret;
80
81 ret = regmap_read(icst->map, icst->vcoreg_off, &val);
82 if (ret)
83 return ret;
84
85 /*
86 * The Integrator/AP core clock can only access the low eight
87 * bits of the v PLL divider. Bit 8 is tied low and always zero,
88 * r is hardwired to 22 and output divider s is hardwired to 1
89 * (divide by 2) according to the document
90 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
91 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
92 */
93 if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
94 vco->v = val & INTEGRATOR_AP_CM_BITS;
95 vco->r = 22;
96 vco->s = 1;
97 return 0;
98 }
99
100 /*
101 * The Integrator/AP system clock on the base board can only
102 * access the low eight bits of the v PLL divider. Bit 8 is tied low
103 * and always zero, r is hardwired to 46, and the output divider is
104 * hardwired to 3 (divide by 4) according to the document
105 * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
106 * page 3-16.
107 */
108 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
109 vco->v = val & INTEGRATOR_AP_SYS_BITS;
110 vco->r = 46;
111 vco->s = 3;
112 return 0;
113 }
114
115 /*
116 * The Integrator/AP PCI clock is using an odd pattern to create
117 * the child clock, basically a single bit called DIVX/Y is used
118 * to select between two different hardwired values: setting the
119 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
120 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
121 * 33 or 25 MHz respectively.
122 */
123 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
124 bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
125
126 vco->v = divxy ? 17 : 14;
127 vco->r = divxy ? 22 : 14;
128 vco->s = 1;
129 return 0;
130 }
131
132 /*
133 * The Integrator/CP core clock can access the low eight bits
134 * of the v PLL divider. Bit 8 is tied low and always zero,
135 * r is hardwired to 22 and the output divider s is accessible
136 * in bits 8 thru 10 according to the document
137 * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
138 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
139 */
140 if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
141 vco->v = val & 0xFF;
142 vco->r = 22;
143 vco->s = (val >> 8) & 7;
144 return 0;
145 }
146
147 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
148 vco->v = (val >> 12) & 0xFF;
149 vco->r = 22;
150 vco->s = (val >> 20) & 7;
151 return 0;
152 }
153
154 vco->v = val & 0x1ff;
155 vco->r = (val >> 9) & 0x7f;
156 vco->s = (val >> 16) & 03;
157 return 0;
158}
159
160/**
161 * vco_set() - commit changes to an ICST VCO
162 * @icst: the ICST clock to set
163 * @vco: the VCO struct to set the changes from
164 */
165static int vco_set(struct clk_icst *icst, struct icst_vco vco)
166{
167 u32 mask;
168 u32 val;
169 int ret;
170
171 /* Mask the bits used by the VCO */
172 switch (icst->ctype) {
173 case ICST_INTEGRATOR_AP_CM:
174 mask = INTEGRATOR_AP_CM_BITS;
175 val = vco.v & 0xFF;
176 if (vco.v & 0x100)
177 pr_err("ICST error: tried to set bit 8 of VDW\n");
178 if (vco.s != 1)
179 pr_err("ICST error: tried to use VOD != 1\n");
180 if (vco.r != 22)
181 pr_err("ICST error: tried to use RDW != 22\n");
182 break;
183 case ICST_INTEGRATOR_AP_SYS:
184 mask = INTEGRATOR_AP_SYS_BITS;
185 val = vco.v & 0xFF;
186 if (vco.v & 0x100)
187 pr_err("ICST error: tried to set bit 8 of VDW\n");
188 if (vco.s != 3)
189 pr_err("ICST error: tried to use VOD != 1\n");
190 if (vco.r != 46)
191 pr_err("ICST error: tried to use RDW != 22\n");
192 break;
193 case ICST_INTEGRATOR_CP_CM_CORE:
194 mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
195 val = (vco.v & 0xFF) | vco.s << 8;
196 if (vco.v & 0x100)
197 pr_err("ICST error: tried to set bit 8 of VDW\n");
198 if (vco.r != 22)
199 pr_err("ICST error: tried to use RDW != 22\n");
200 break;
201 case ICST_INTEGRATOR_CP_CM_MEM:
202 mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
203 val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
204 if (vco.v & 0x100)
205 pr_err("ICST error: tried to set bit 8 of VDW\n");
206 if (vco.r != 22)
207 pr_err("ICST error: tried to use RDW != 22\n");
208 break;
209 default:
210 /* Regular auxilary oscillator */
211 mask = VERSATILE_AUX_OSC_BITS;
212 val = vco.v | (vco.r << 9) | (vco.s << 16);
213 break;
214 }
215
216 pr_debug("ICST: new val = 0x%08x\n", val);
217
218 /* This magic unlocks the VCO so it can be controlled */
219 ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
220 if (ret)
221 return ret;
222 ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
223 if (ret)
224 return ret;
225 /* This locks the VCO again */
226 ret = regmap_write(icst->map, icst->lockreg_off, 0);
227 if (ret)
228 return ret;
229 return 0;
230}
231
232static unsigned long icst_recalc_rate(struct clk_hw *hw,
233 unsigned long parent_rate)
234{
235 struct clk_icst *icst = to_icst(hw);
236 struct icst_vco vco;
237 int ret;
238
239 if (parent_rate)
240 icst->params->ref = parent_rate;
241 ret = vco_get(icst, &vco);
242 if (ret) {
243 pr_err("ICST: could not get VCO setting\n");
244 return 0;
245 }
246 icst->rate = icst_hz(icst->params, vco);
247 return icst->rate;
248}
249
250static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
251 unsigned long *prate)
252{
253 struct clk_icst *icst = to_icst(hw);
254 struct icst_vco vco;
255
256 if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
257 icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
258 if (rate <= 12000000)
259 return 12000000;
260 if (rate >= 160000000)
261 return 160000000;
262 /* Slam to closest megahertz */
263 return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000;
264 }
265
266 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
267 if (rate <= 6000000)
268 return 6000000;
269 if (rate >= 66000000)
270 return 66000000;
271 /* Slam to closest 0.5 megahertz */
272 return DIV_ROUND_CLOSEST(rate, 500000) * 500000;
273 }
274
275 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
276 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */
277 if (rate <= 3000000)
278 return 3000000;
279 if (rate >= 50000000)
280 return 5000000;
281 /* Slam to closest 0.25 MHz */
282 return DIV_ROUND_CLOSEST(rate, 250000) * 250000;
283 }
284
285 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
286 /*
287 * If we're below or less than halfway from 25 to 33 MHz
288 * select 25 MHz
289 */
290 if (rate <= 25000000 || rate < 29000000)
291 return 25000000;
292 /* Else just return the default frequency */
293 return 33000000;
294 }
295
296 vco = icst_hz_to_vco(icst->params, rate);
297 return icst_hz(icst->params, vco);
298}
299
300static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
301 unsigned long parent_rate)
302{
303 struct clk_icst *icst = to_icst(hw);
304 struct icst_vco vco;
305
306 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
307 /* This clock is especially primitive */
308 unsigned int val;
309 int ret;
310
311 if (rate == 25000000) {
312 val = 0;
313 } else if (rate == 33000000) {
314 val = INTEGRATOR_AP_PCI_25_33_MHZ;
315 } else {
316 pr_err("ICST: cannot set PCI frequency %lu\n",
317 rate);
318 return -EINVAL;
319 }
320 ret = regmap_write(icst->map, icst->lockreg_off,
321 VERSATILE_LOCK_VAL);
322 if (ret)
323 return ret;
324 ret = regmap_update_bits(icst->map, icst->vcoreg_off,
325 INTEGRATOR_AP_PCI_25_33_MHZ,
326 val);
327 if (ret)
328 return ret;
329 /* This locks the VCO again */
330 ret = regmap_write(icst->map, icst->lockreg_off, 0);
331 if (ret)
332 return ret;
333 return 0;
334 }
335
336 if (parent_rate)
337 icst->params->ref = parent_rate;
338 vco = icst_hz_to_vco(icst->params, rate);
339 icst->rate = icst_hz(icst->params, vco);
340 return vco_set(icst, vco);
341}
342
343static const struct clk_ops icst_ops = {
344 .recalc_rate = icst_recalc_rate,
345 .round_rate = icst_round_rate,
346 .set_rate = icst_set_rate,
347};
348
349static struct clk *icst_clk_setup(struct device *dev,
350 const struct clk_icst_desc *desc,
351 const char *name,
352 const char *parent_name,
353 struct regmap *map,
354 enum icst_control_type ctype)
355{
356 struct clk *clk;
357 struct clk_icst *icst;
358 struct clk_init_data init;
359 struct icst_params *pclone;
360
361 icst = kzalloc(sizeof(struct clk_icst), GFP_KERNEL);
362 if (!icst) {
363 pr_err("could not allocate ICST clock!\n");
364 return ERR_PTR(-ENOMEM);
365 }
366
367 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
368 if (!pclone) {
369 kfree(icst);
370 pr_err("could not clone ICST params\n");
371 return ERR_PTR(-ENOMEM);
372 }
373
374 init.name = name;
375 init.ops = &icst_ops;
376 init.flags = 0;
377 init.parent_names = (parent_name ? &parent_name : NULL);
378 init.num_parents = (parent_name ? 1 : 0);
379 icst->map = map;
380 icst->hw.init = &init;
381 icst->params = pclone;
382 icst->vcoreg_off = desc->vco_offset;
383 icst->lockreg_off = desc->lock_offset;
384 icst->ctype = ctype;
385
386 clk = clk_register(dev, &icst->hw);
387 if (IS_ERR(clk)) {
388 kfree(pclone);
389 kfree(icst);
390 }
391
392 return clk;
393}
394
395struct clk *icst_clk_register(struct device *dev,
396 const struct clk_icst_desc *desc,
397 const char *name,
398 const char *parent_name,
399 void __iomem *base)
400{
401 struct regmap_config icst_regmap_conf = {
402 .reg_bits = 32,
403 .val_bits = 32,
404 .reg_stride = 4,
405 };
406 struct regmap *map;
407
408 map = regmap_init_mmio(dev, base, &icst_regmap_conf);
409 if (IS_ERR(map)) {
410 pr_err("could not initialize ICST regmap\n");
411 return ERR_CAST(map);
412 }
413 return icst_clk_setup(dev, desc, name, parent_name, map,
414 ICST_VERSATILE);
415}
416EXPORT_SYMBOL_GPL(icst_clk_register);
417
418#ifdef CONFIG_OF
419/*
420 * In a device tree, an memory-mapped ICST clock appear as a child
421 * of a syscon node. Assume this and probe it only as a child of a
422 * syscon.
423 */
424
425static const struct icst_params icst525_params = {
426 .vco_max = ICST525_VCO_MAX_5V,
427 .vco_min = ICST525_VCO_MIN,
428 .vd_min = 8,
429 .vd_max = 263,
430 .rd_min = 3,
431 .rd_max = 65,
432 .s2div = icst525_s2div,
433 .idx2s = icst525_idx2s,
434};
435
436static const struct icst_params icst307_params = {
437 .vco_max = ICST307_VCO_MAX,
438 .vco_min = ICST307_VCO_MIN,
439 .vd_min = 4 + 8,
440 .vd_max = 511 + 8,
441 .rd_min = 1 + 2,
442 .rd_max = 127 + 2,
443 .s2div = icst307_s2div,
444 .idx2s = icst307_idx2s,
445};
446
447/**
448 * The core modules on the Integrator/AP and Integrator/CP have
449 * especially crippled ICST525 control.
450 */
451static const struct icst_params icst525_apcp_cm_params = {
452 .vco_max = ICST525_VCO_MAX_5V,
453 .vco_min = ICST525_VCO_MIN,
454 /* Minimum 12 MHz, VDW = 4 */
455 .vd_min = 12,
456 /*
457 * Maximum 160 MHz, VDW = 152 for all core modules, but
458 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
459 * go to 200 MHz (max VDW = 192).
460 */
461 .vd_max = 192,
462 /* r is hardcoded to 22 and this is the actual divisor, +2 */
463 .rd_min = 24,
464 .rd_max = 24,
465 .s2div = icst525_s2div,
466 .idx2s = icst525_idx2s,
467};
468
469static const struct icst_params icst525_ap_sys_params = {
470 .vco_max = ICST525_VCO_MAX_5V,
471 .vco_min = ICST525_VCO_MIN,
472 /* Minimum 3 MHz, VDW = 4 */
473 .vd_min = 3,
474 /* Maximum 50 MHz, VDW = 192 */
475 .vd_max = 50,
476 /* r is hardcoded to 46 and this is the actual divisor, +2 */
477 .rd_min = 48,
478 .rd_max = 48,
479 .s2div = icst525_s2div,
480 .idx2s = icst525_idx2s,
481};
482
483static const struct icst_params icst525_ap_pci_params = {
484 .vco_max = ICST525_VCO_MAX_5V,
485 .vco_min = ICST525_VCO_MIN,
486 /* Minimum 25 MHz */
487 .vd_min = 25,
488 /* Maximum 33 MHz */
489 .vd_max = 33,
490 /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
491 .rd_min = 16,
492 .rd_max = 24,
493 .s2div = icst525_s2div,
494 .idx2s = icst525_idx2s,
495};
496
497static void __init of_syscon_icst_setup(struct device_node *np)
498{
499 struct device_node *parent;
500 struct regmap *map;
501 struct clk_icst_desc icst_desc;
502 const char *name = np->name;
503 const char *parent_name;
504 struct clk *regclk;
505 enum icst_control_type ctype;
506
507 /* We do not release this reference, we are using it perpetually */
508 parent = of_get_parent(np);
509 if (!parent) {
510 pr_err("no parent node for syscon ICST clock\n");
511 return;
512 }
513 map = syscon_node_to_regmap(parent);
514 if (IS_ERR(map)) {
515 pr_err("no regmap for syscon ICST clock parent\n");
516 return;
517 }
518
519 if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
520 pr_err("no VCO register offset for ICST clock\n");
521 return;
522 }
523 if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
524 pr_err("no lock register offset for ICST clock\n");
525 return;
526 }
527
528 if (of_device_is_compatible(np, "arm,syscon-icst525")) {
529 icst_desc.params = &icst525_params;
530 ctype = ICST_VERSATILE;
531 } else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
532 icst_desc.params = &icst307_params;
533 ctype = ICST_VERSATILE;
534 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
535 icst_desc.params = &icst525_apcp_cm_params;
536 ctype = ICST_INTEGRATOR_AP_CM;
537 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
538 icst_desc.params = &icst525_ap_sys_params;
539 ctype = ICST_INTEGRATOR_AP_SYS;
540 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
541 icst_desc.params = &icst525_ap_pci_params;
542 ctype = ICST_INTEGRATOR_AP_PCI;
543 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
544 icst_desc.params = &icst525_apcp_cm_params;
545 ctype = ICST_INTEGRATOR_CP_CM_CORE;
546 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
547 icst_desc.params = &icst525_apcp_cm_params;
548 ctype = ICST_INTEGRATOR_CP_CM_MEM;
549 } else {
550 pr_err("unknown ICST clock %s\n", name);
551 return;
552 }
553
554 /* Parent clock name is not the same as node parent */
555 parent_name = of_clk_get_parent_name(np, 0);
556
557 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
558 if (IS_ERR(regclk)) {
559 pr_err("error setting up syscon ICST clock %s\n", name);
560 return;
561 }
562 of_clk_add_provider(np, of_clk_src_simple_get, regclk);
563 pr_debug("registered syscon ICST clock %s\n", name);
564}
565
566CLK_OF_DECLARE(arm_syscon_icst525_clk,
567 "arm,syscon-icst525", of_syscon_icst_setup);
568CLK_OF_DECLARE(arm_syscon_icst307_clk,
569 "arm,syscon-icst307", of_syscon_icst_setup);
570CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
571 "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
572CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
573 "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
574CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
575 "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
576CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
577 "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
578CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
579 "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);
580#endif