1/*
  2 * Copyright 2012 Freescale Semiconductor, Inc.
  3 *
  4 * The code contained herein is licensed under the GNU General Public
  5 * License. You may obtain a copy of the GNU General Public License
  6 * Version 2 or later at the following locations:
  7 *
  8 * http://www.opensource.org/licenses/gpl-license.html
  9 * http://www.gnu.org/copyleft/gpl.html
 10 */
 11
 12#include <linux/clk-provider.h>
 13#include <linux/delay.h>
 14#include <linux/err.h>
 15#include <linux/io.h>
 16#include <linux/slab.h>
 17#include "clk.h"
 18
 19/**
 20 * struct clk_pll - mxs pll clock
 21 * @hw: clk_hw for the pll
 22 * @base: base address of the pll
 23 * @power: the shift of power bit
 24 * @rate: the clock rate of the pll
 25 *
 26 * The mxs pll is a fixed rate clock with power and gate control,
 27 * and the shift of gate bit is always 31.
 28 */
 29struct clk_pll {
 30	struct clk_hw hw;
 31	void __iomem *base;
 32	u8 power;
 33	unsigned long rate;
 34};
 35
 36#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 37
 38static int clk_pll_prepare(struct clk_hw *hw)
 39{
 40	struct clk_pll *pll = to_clk_pll(hw);
 41
 42	writel_relaxed(1 << pll->power, pll->base + SET);
 43
 44	udelay(10);
 45
 46	return 0;
 47}
 48
 49static void clk_pll_unprepare(struct clk_hw *hw)
 50{
 51	struct clk_pll *pll = to_clk_pll(hw);
 52
 53	writel_relaxed(1 << pll->power, pll->base + CLR);
 54}
 55
 56static int clk_pll_enable(struct clk_hw *hw)
 57{
 58	struct clk_pll *pll = to_clk_pll(hw);
 59
 60	writel_relaxed(1 << 31, pll->base + CLR);
 61
 62	return 0;
 63}
 64
 65static void clk_pll_disable(struct clk_hw *hw)
 66{
 67	struct clk_pll *pll = to_clk_pll(hw);
 68
 69	writel_relaxed(1 << 31, pll->base + SET);
 70}
 71
 72static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 73					 unsigned long parent_rate)
 74{
 75	struct clk_pll *pll = to_clk_pll(hw);
 76
 77	return pll->rate;
 78}
 79
 80static const struct clk_ops clk_pll_ops = {
 81	.prepare = clk_pll_prepare,
 82	.unprepare = clk_pll_unprepare,
 83	.enable = clk_pll_enable,
 84	.disable = clk_pll_disable,
 85	.recalc_rate = clk_pll_recalc_rate,
 86};
 87
 88struct clk *mxs_clk_pll(const char *name, const char *parent_name,
 89			void __iomem *base, u8 power, unsigned long rate)
 90{
 91	struct clk_pll *pll;
 92	struct clk *clk;
 93	struct clk_init_data init;
 94
 95	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 96	if (!pll)
 97		return ERR_PTR(-ENOMEM);
 98
 99	init.name = name;
100	init.ops = &clk_pll_ops;
101	init.flags = 0;
102	init.parent_names = (parent_name ? &parent_name: NULL);
103	init.num_parents = (parent_name ? 1 : 0);
104
105	pll->base = base;
106	pll->rate = rate;
107	pll->power = power;
108	pll->hw.init = &init;
109
110	clk = clk_register(NULL, &pll->hw);
111	if (IS_ERR(clk))
112		kfree(pll);
113
114	return clk;
115}