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1/*
2 * Ralink MT7620A SoC PCI support
3 *
4 * Copyright (C) 2007-2013 Bruce Chang (Mediatek)
5 * Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_pci.h>
21#include <linux/reset.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-ralink/ralink_regs.h>
25#include <asm/mach-ralink/mt7620.h>
26
27#define RALINK_PCI_IO_MAP_BASE 0x10160000
28#define RALINK_PCI_MEMORY_BASE 0x0
29
30#define RALINK_INT_PCIE0 4
31
32#define RALINK_CLKCFG1 0x30
33#define RALINK_GPIOMODE 0x60
34
35#define PPLL_CFG1 0x9c
36#define PDRV_SW_SET BIT(23)
37
38#define PPLL_DRV 0xa0
39#define PDRV_SW_SET (1<<31)
40#define LC_CKDRVPD (1<<19)
41#define LC_CKDRVOHZ (1<<18)
42#define LC_CKDRVHZ (1<<17)
43#define LC_CKTEST (1<<16)
44
45/* PCI Bridge registers */
46#define RALINK_PCI_PCICFG_ADDR 0x00
47#define PCIRST BIT(1)
48
49#define RALINK_PCI_PCIENA 0x0C
50#define PCIINT2 BIT(20)
51
52#define RALINK_PCI_CONFIG_ADDR 0x20
53#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
54#define RALINK_PCI_MEMBASE 0x28
55#define RALINK_PCI_IOBASE 0x2C
56
57/* PCI RC registers */
58#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
59#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
60#define RALINK_PCI0_ID 0x30
61#define RALINK_PCI0_CLASS 0x34
62#define RALINK_PCI0_SUBID 0x38
63#define RALINK_PCI0_STATUS 0x50
64#define PCIE_LINK_UP_ST BIT(0)
65
66#define PCIEPHY0_CFG 0x90
67
68#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
69#define RALINK_PCIE0_CLK_EN (1 << 26)
70
71#define BUSY 0x80000000
72#define WAITRETRY_MAX 10
73#define WRITE_MODE (1UL << 23)
74#define DATA_SHIFT 0
75#define ADDR_SHIFT 8
76
77
78static void __iomem *bridge_base;
79static void __iomem *pcie_base;
80
81static struct reset_control *rstpcie0;
82
83static inline void bridge_w32(u32 val, unsigned reg)
84{
85 iowrite32(val, bridge_base + reg);
86}
87
88static inline u32 bridge_r32(unsigned reg)
89{
90 return ioread32(bridge_base + reg);
91}
92
93static inline void pcie_w32(u32 val, unsigned reg)
94{
95 iowrite32(val, pcie_base + reg);
96}
97
98static inline u32 pcie_r32(unsigned reg)
99{
100 return ioread32(pcie_base + reg);
101}
102
103static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
104{
105 u32 val = pcie_r32(reg);
106
107 val &= ~clr;
108 val |= set;
109 pcie_w32(val, reg);
110}
111
112static int wait_pciephy_busy(void)
113{
114 unsigned long reg_value = 0x0, retry = 0;
115
116 while (1) {
117 reg_value = pcie_r32(PCIEPHY0_CFG);
118
119 if (reg_value & BUSY)
120 mdelay(100);
121 else
122 break;
123 if (retry++ > WAITRETRY_MAX) {
124 printk(KERN_WARN "PCIE-PHY retry failed.\n");
125 return -1;
126 }
127 }
128 return 0;
129}
130
131static void pcie_phy(unsigned long addr, unsigned long val)
132{
133 wait_pciephy_busy();
134 pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
135 PCIEPHY0_CFG);
136 mdelay(1);
137 wait_pciephy_busy();
138}
139
140static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
141 int size, u32 *val)
142{
143 unsigned int slot = PCI_SLOT(devfn);
144 u8 func = PCI_FUNC(devfn);
145 u32 address;
146 u32 data;
147 u32 num = 0;
148
149 if (bus)
150 num = bus->number;
151
152 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
153 (func << 8) | (where & 0xfc) | 0x80000000;
154 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
155 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
156
157 switch (size) {
158 case 1:
159 *val = (data >> ((where & 3) << 3)) & 0xff;
160 break;
161 case 2:
162 *val = (data >> ((where & 3) << 3)) & 0xffff;
163 break;
164 case 4:
165 *val = data;
166 break;
167 }
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
173 int size, u32 val)
174{
175 unsigned int slot = PCI_SLOT(devfn);
176 u8 func = PCI_FUNC(devfn);
177 u32 address;
178 u32 data;
179 u32 num = 0;
180
181 if (bus)
182 num = bus->number;
183
184 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
185 (func << 8) | (where & 0xfc) | 0x80000000;
186 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
187 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
188
189 switch (size) {
190 case 1:
191 data = (data & ~(0xff << ((where & 3) << 3))) |
192 (val << ((where & 3) << 3));
193 break;
194 case 2:
195 data = (data & ~(0xffff << ((where & 3) << 3))) |
196 (val << ((where & 3) << 3));
197 break;
198 case 4:
199 data = val;
200 break;
201 }
202
203 bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
204
205 return PCIBIOS_SUCCESSFUL;
206}
207
208struct pci_ops mt7620_pci_ops = {
209 .read = pci_config_read,
210 .write = pci_config_write,
211};
212
213static struct resource mt7620_res_pci_mem1;
214static struct resource mt7620_res_pci_io1;
215struct pci_controller mt7620_controller = {
216 .pci_ops = &mt7620_pci_ops,
217 .mem_resource = &mt7620_res_pci_mem1,
218 .mem_offset = 0x00000000UL,
219 .io_resource = &mt7620_res_pci_io1,
220 .io_offset = 0x00000000UL,
221 .io_map_base = 0xa0000000,
222};
223
224static int mt7620_pci_hw_init(struct platform_device *pdev)
225{
226 /* bypass PCIe DLL */
227 pcie_phy(0x0, 0x80);
228 pcie_phy(0x1, 0x04);
229
230 /* Elastic buffer control */
231 pcie_phy(0x68, 0xB4);
232
233 /* put core into reset */
234 pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
235 reset_control_assert(rstpcie0);
236
237 /* disable power and all clocks */
238 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
239 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
240
241 /* bring core out of reset */
242 reset_control_deassert(rstpcie0);
243 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
244 mdelay(100);
245
246 if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
247 dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
248 reset_control_assert(rstpcie0);
249 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
250 return -1;
251 }
252
253 /* power up the bus */
254 rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
255 PPLL_DRV);
256
257 return 0;
258}
259
260static int mt7628_pci_hw_init(struct platform_device *pdev)
261{
262 u32 val = 0;
263
264 /* bring the core out of reset */
265 rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
266 reset_control_deassert(rstpcie0);
267
268 /* enable the pci clk */
269 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
270 mdelay(100);
271
272 /* voodoo from the SDK driver */
273 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
274
275 pci_config_read(NULL, 0, 0x70c, 4, &val);
276 val &= ~(0xff) << 8;
277 val |= 0x50 << 8;
278 pci_config_write(NULL, 0, 0x70c, 4, val);
279
280 pci_config_read(NULL, 0, 0x70c, 4, &val);
281 dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
282
283 return 0;
284}
285
286static int mt7620_pci_probe(struct platform_device *pdev)
287{
288 struct resource *bridge_res = platform_get_resource(pdev,
289 IORESOURCE_MEM, 0);
290 struct resource *pcie_res = platform_get_resource(pdev,
291 IORESOURCE_MEM, 1);
292 u32 val = 0;
293
294 rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
295 if (IS_ERR(rstpcie0))
296 return PTR_ERR(rstpcie0);
297
298 bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
299 if (IS_ERR(bridge_base))
300 return PTR_ERR(bridge_base);
301
302 pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
303 if (IS_ERR(pcie_base))
304 return PTR_ERR(pcie_base);
305
306 iomem_resource.start = 0;
307 iomem_resource.end = ~0;
308 ioport_resource.start = 0;
309 ioport_resource.end = ~0;
310
311 /* bring up the pci core */
312 switch (ralink_soc) {
313 case MT762X_SOC_MT7620A:
314 if (mt7620_pci_hw_init(pdev))
315 return -1;
316 break;
317
318 case MT762X_SOC_MT7628AN:
319 if (mt7628_pci_hw_init(pdev))
320 return -1;
321 break;
322
323 default:
324 dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
325 return -1;
326 }
327 mdelay(50);
328
329 /* enable write access */
330 pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
331 mdelay(100);
332
333 /* check if there is a card present */
334 if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
335 reset_control_assert(rstpcie0);
336 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
337 if (ralink_soc == MT762X_SOC_MT7620A)
338 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
339 dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
340 return -1;
341 }
342
343 /* setup ranges */
344 bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
345 bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
346
347 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
348 pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
349 pcie_w32(0x06040001, RALINK_PCI0_CLASS);
350
351 /* enable interrupts */
352 pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
353
354 /* voodoo from the SDK driver */
355 pci_config_read(NULL, 0, 4, 4, &val);
356 pci_config_write(NULL, 0, 4, 4, val | 0x7);
357
358 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
359 register_pci_controller(&mt7620_controller);
360
361 return 0;
362}
363
364int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
365{
366 u16 cmd;
367 u32 val;
368 int irq = 0;
369
370 if ((dev->bus->number == 0) && (slot == 0)) {
371 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
372 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
373 RALINK_PCI_MEMORY_BASE);
374 pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
375 } else if ((dev->bus->number == 1) && (slot == 0x0)) {
376 irq = RALINK_INT_PCIE0;
377 } else {
378 dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
379 dev->bus->number, slot);
380 return 0;
381 }
382 dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
383 dev->bus->number, slot, irq);
384
385 /* configure the cache line size to 0x14 */
386 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
387
388 /* configure latency timer to 0xff */
389 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
390 pci_read_config_word(dev, PCI_COMMAND, &cmd);
391
392 /* setup the slot */
393 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
394 pci_write_config_word(dev, PCI_COMMAND, cmd);
395 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
396
397 return irq;
398}
399
400int pcibios_plat_dev_init(struct pci_dev *dev)
401{
402 return 0;
403}
404
405static const struct of_device_id mt7620_pci_ids[] = {
406 { .compatible = "mediatek,mt7620-pci" },
407 {},
408};
409
410static struct platform_driver mt7620_pci_driver = {
411 .probe = mt7620_pci_probe,
412 .driver = {
413 .name = "mt7620-pci",
414 .of_match_table = of_match_ptr(mt7620_pci_ids),
415 },
416};
417
418static int __init mt7620_pci_init(void)
419{
420 return platform_driver_register(&mt7620_pci_driver);
421}
422
423arch_initcall(mt7620_pci_init);