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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38#include <asm/cpu-features.h>
39
40static int __maybe_unused max_cpus = 1;
41
42/* these may be configured by the platform code */
43int bmips_smp_enabled = 1;
44int bmips_cpu_offset;
45cpumask_t bmips_booted_mask;
46unsigned long bmips_tp1_irqs = IE_IRQ1;
47
48#define RESET_FROM_KSEG0 0x80080800
49#define RESET_FROM_KSEG1 0xa0080800
50
51static void bmips_set_reset_vec(int cpu, u32 val);
52
53#ifdef CONFIG_SMP
54
55/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
56unsigned long bmips_smp_boot_sp;
57unsigned long bmips_smp_boot_gp;
58
59static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
60static void bmips5000_send_ipi_single(int cpu, unsigned int action);
61static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
62static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
63
64/* SW interrupts 0,1 are used for interprocessor signaling */
65#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
66#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
67
68#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
69#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
70#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
71#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
72
73static void __init bmips_smp_setup(void)
74{
75 int i, cpu = 1, boot_cpu = 0;
76 int cpu_hw_intr;
77
78 switch (current_cpu_type()) {
79 case CPU_BMIPS4350:
80 case CPU_BMIPS4380:
81 /* arbitration priority */
82 clear_c0_brcm_cmt_ctrl(0x30);
83
84 /* NBK and weak order flags */
85 set_c0_brcm_config_0(0x30000);
86
87 /* Find out if we are running on TP0 or TP1 */
88 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
89
90 /*
91 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
92 * thread
93 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
94 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
95 */
96 if (boot_cpu == 0)
97 cpu_hw_intr = 0x02;
98 else
99 cpu_hw_intr = 0x1d;
100
101 change_c0_brcm_cmt_intr(0xf8018000,
102 (cpu_hw_intr << 27) | (0x03 << 15));
103
104 /* single core, 2 threads (2 pipelines) */
105 max_cpus = 2;
106
107 break;
108 case CPU_BMIPS5000:
109 /* enable raceless SW interrupts */
110 set_c0_brcm_config(0x03 << 22);
111
112 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
113 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
114
115 /* N cores, 2 threads per core */
116 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
117
118 /* clear any pending SW interrupts */
119 for (i = 0; i < max_cpus; i++) {
120 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
121 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
122 }
123
124 break;
125 default:
126 max_cpus = 1;
127 }
128
129 if (!bmips_smp_enabled)
130 max_cpus = 1;
131
132 /* this can be overridden by the BSP */
133 if (!board_ebase_setup)
134 board_ebase_setup = &bmips_ebase_setup;
135
136 __cpu_number_map[boot_cpu] = 0;
137 __cpu_logical_map[0] = boot_cpu;
138
139 for (i = 0; i < max_cpus; i++) {
140 if (i != boot_cpu) {
141 __cpu_number_map[i] = cpu;
142 __cpu_logical_map[cpu] = i;
143 cpu++;
144 }
145 set_cpu_possible(i, 1);
146 set_cpu_present(i, 1);
147 }
148}
149
150/*
151 * IPI IRQ setup - runs on CPU0
152 */
153static void bmips_prepare_cpus(unsigned int max_cpus)
154{
155 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
156
157 switch (current_cpu_type()) {
158 case CPU_BMIPS4350:
159 case CPU_BMIPS4380:
160 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
161 break;
162 case CPU_BMIPS5000:
163 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
164 break;
165 default:
166 return;
167 }
168
169 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
170 "smp_ipi0", NULL))
171 panic("Can't request IPI0 interrupt");
172 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
173 "smp_ipi1", NULL))
174 panic("Can't request IPI1 interrupt");
175}
176
177/*
178 * Tell the hardware to boot CPUx - runs on CPU0
179 */
180static void bmips_boot_secondary(int cpu, struct task_struct *idle)
181{
182 bmips_smp_boot_sp = __KSTK_TOS(idle);
183 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
184 mb();
185
186 /*
187 * Initial boot sequence for secondary CPU:
188 * bmips_reset_nmi_vec @ a000_0000 ->
189 * bmips_smp_entry ->
190 * plat_wired_tlb_setup (cached function call; optional) ->
191 * start_secondary (cached jump)
192 *
193 * Warm restart sequence:
194 * play_dead WAIT loop ->
195 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
196 * eret to play_dead ->
197 * bmips_secondary_reentry ->
198 * start_secondary
199 */
200
201 pr_info("SMP: Booting CPU%d...\n", cpu);
202
203 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
204 /* kseg1 might not exist if this CPU enabled XKS01 */
205 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
206
207 switch (current_cpu_type()) {
208 case CPU_BMIPS4350:
209 case CPU_BMIPS4380:
210 bmips43xx_send_ipi_single(cpu, 0);
211 break;
212 case CPU_BMIPS5000:
213 bmips5000_send_ipi_single(cpu, 0);
214 break;
215 }
216 } else {
217 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
218
219 switch (current_cpu_type()) {
220 case CPU_BMIPS4350:
221 case CPU_BMIPS4380:
222 /* Reset slave TP1 if booting from TP0 */
223 if (cpu_logical_map(cpu) == 1)
224 set_c0_brcm_cmt_ctrl(0x01);
225 break;
226 case CPU_BMIPS5000:
227 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
228 break;
229 }
230 cpumask_set_cpu(cpu, &bmips_booted_mask);
231 }
232}
233
234/*
235 * Early setup - runs on secondary CPU after cache probe
236 */
237static void bmips_init_secondary(void)
238{
239 switch (current_cpu_type()) {
240 case CPU_BMIPS4350:
241 case CPU_BMIPS4380:
242 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
243 break;
244 case CPU_BMIPS5000:
245 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
246 current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
247 break;
248 }
249}
250
251/*
252 * Late setup - runs on secondary CPU before entering the idle loop
253 */
254static void bmips_smp_finish(void)
255{
256 pr_info("SMP: CPU%d is running\n", smp_processor_id());
257
258 /* make sure there won't be a timer interrupt for a little while */
259 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
260
261 irq_enable_hazard();
262 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
263 irq_enable_hazard();
264}
265
266/*
267 * BMIPS5000 raceless IPIs
268 *
269 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
270 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
271 * IPI1 is used for SMP_CALL_FUNCTION
272 */
273
274static void bmips5000_send_ipi_single(int cpu, unsigned int action)
275{
276 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
277}
278
279static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
280{
281 int action = irq - IPI0_IRQ;
282
283 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
284
285 if (action == 0)
286 scheduler_ipi();
287 else
288 generic_smp_call_function_interrupt();
289
290 return IRQ_HANDLED;
291}
292
293static void bmips5000_send_ipi_mask(const struct cpumask *mask,
294 unsigned int action)
295{
296 unsigned int i;
297
298 for_each_cpu(i, mask)
299 bmips5000_send_ipi_single(i, action);
300}
301
302/*
303 * BMIPS43xx racey IPIs
304 *
305 * We use one inbound SW IRQ for each CPU.
306 *
307 * A spinlock must be held in order to keep CPUx from accidentally clearing
308 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
309 * same spinlock is used to protect the action masks.
310 */
311
312static DEFINE_SPINLOCK(ipi_lock);
313static DEFINE_PER_CPU(int, ipi_action_mask);
314
315static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
316{
317 unsigned long flags;
318
319 spin_lock_irqsave(&ipi_lock, flags);
320 set_c0_cause(cpu ? C_SW1 : C_SW0);
321 per_cpu(ipi_action_mask, cpu) |= action;
322 irq_enable_hazard();
323 spin_unlock_irqrestore(&ipi_lock, flags);
324}
325
326static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
327{
328 unsigned long flags;
329 int action, cpu = irq - IPI0_IRQ;
330
331 spin_lock_irqsave(&ipi_lock, flags);
332 action = __this_cpu_read(ipi_action_mask);
333 per_cpu(ipi_action_mask, cpu) = 0;
334 clear_c0_cause(cpu ? C_SW1 : C_SW0);
335 spin_unlock_irqrestore(&ipi_lock, flags);
336
337 if (action & SMP_RESCHEDULE_YOURSELF)
338 scheduler_ipi();
339 if (action & SMP_CALL_FUNCTION)
340 generic_smp_call_function_interrupt();
341
342 return IRQ_HANDLED;
343}
344
345static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
346 unsigned int action)
347{
348 unsigned int i;
349
350 for_each_cpu(i, mask)
351 bmips43xx_send_ipi_single(i, action);
352}
353
354#ifdef CONFIG_HOTPLUG_CPU
355
356static int bmips_cpu_disable(void)
357{
358 unsigned int cpu = smp_processor_id();
359
360 if (cpu == 0)
361 return -EBUSY;
362
363 pr_info("SMP: CPU%d is offline\n", cpu);
364
365 set_cpu_online(cpu, false);
366 calculate_cpu_foreign_map();
367 cpumask_clear_cpu(cpu, &cpu_callin_map);
368 clear_c0_status(IE_IRQ5);
369
370 local_flush_tlb_all();
371 local_flush_icache_range(0, ~0);
372
373 return 0;
374}
375
376static void bmips_cpu_die(unsigned int cpu)
377{
378}
379
380void __ref play_dead(void)
381{
382 idle_task_exit();
383
384 /* flush data cache */
385 _dma_cache_wback_inv(0, ~0);
386
387 /*
388 * Wakeup is on SW0 or SW1; disable everything else
389 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
390 * IRQ handlers; this clears ST0_IE and returns immediately.
391 */
392 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
393 change_c0_status(
394 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
395 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
396 irq_disable_hazard();
397
398 /*
399 * wait for SW interrupt from bmips_boot_secondary(), then jump
400 * back to start_secondary()
401 */
402 __asm__ __volatile__(
403 " wait\n"
404 " j bmips_secondary_reentry\n"
405 : : : "memory");
406}
407
408#endif /* CONFIG_HOTPLUG_CPU */
409
410struct plat_smp_ops bmips43xx_smp_ops = {
411 .smp_setup = bmips_smp_setup,
412 .prepare_cpus = bmips_prepare_cpus,
413 .boot_secondary = bmips_boot_secondary,
414 .smp_finish = bmips_smp_finish,
415 .init_secondary = bmips_init_secondary,
416 .send_ipi_single = bmips43xx_send_ipi_single,
417 .send_ipi_mask = bmips43xx_send_ipi_mask,
418#ifdef CONFIG_HOTPLUG_CPU
419 .cpu_disable = bmips_cpu_disable,
420 .cpu_die = bmips_cpu_die,
421#endif
422};
423
424struct plat_smp_ops bmips5000_smp_ops = {
425 .smp_setup = bmips_smp_setup,
426 .prepare_cpus = bmips_prepare_cpus,
427 .boot_secondary = bmips_boot_secondary,
428 .smp_finish = bmips_smp_finish,
429 .init_secondary = bmips_init_secondary,
430 .send_ipi_single = bmips5000_send_ipi_single,
431 .send_ipi_mask = bmips5000_send_ipi_mask,
432#ifdef CONFIG_HOTPLUG_CPU
433 .cpu_disable = bmips_cpu_disable,
434 .cpu_die = bmips_cpu_die,
435#endif
436};
437
438#endif /* CONFIG_SMP */
439
440/***********************************************************************
441 * BMIPS vector relocation
442 * This is primarily used for SMP boot, but it is applicable to some
443 * UP BMIPS systems as well.
444 ***********************************************************************/
445
446static void bmips_wr_vec(unsigned long dst, char *start, char *end)
447{
448 memcpy((void *)dst, start, end - start);
449 dma_cache_wback(dst, end - start);
450 local_flush_icache_range(dst, dst + (end - start));
451 instruction_hazard();
452}
453
454static inline void bmips_nmi_handler_setup(void)
455{
456 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
457 &bmips_reset_nmi_vec_end);
458 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
459 &bmips_smp_int_vec_end);
460}
461
462struct reset_vec_info {
463 int cpu;
464 u32 val;
465};
466
467static void bmips_set_reset_vec_remote(void *vinfo)
468{
469 struct reset_vec_info *info = vinfo;
470 int shift = info->cpu & 0x01 ? 16 : 0;
471 u32 mask = ~(0xffff << shift), val = info->val >> 16;
472
473 preempt_disable();
474 if (smp_processor_id() > 0) {
475 smp_call_function_single(0, &bmips_set_reset_vec_remote,
476 info, 1);
477 } else {
478 if (info->cpu & 0x02) {
479 /* BMIPS5200 "should" use mask/shift, but it's buggy */
480 bmips_write_zscm_reg(0xa0, (val << 16) | val);
481 bmips_read_zscm_reg(0xa0);
482 } else {
483 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
484 (val << shift));
485 }
486 }
487 preempt_enable();
488}
489
490static void bmips_set_reset_vec(int cpu, u32 val)
491{
492 struct reset_vec_info info;
493
494 if (current_cpu_type() == CPU_BMIPS5000) {
495 /* this needs to run from CPU0 (which is always online) */
496 info.cpu = cpu;
497 info.val = val;
498 bmips_set_reset_vec_remote(&info);
499 } else {
500 void __iomem *cbr = BMIPS_GET_CBR();
501
502 if (cpu == 0)
503 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
504 else {
505 if (current_cpu_type() != CPU_BMIPS4380)
506 return;
507 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
508 }
509 }
510 __sync();
511 back_to_back_c0_hazard();
512}
513
514void bmips_ebase_setup(void)
515{
516 unsigned long new_ebase = ebase;
517
518 BUG_ON(ebase != CKSEG0);
519
520 switch (current_cpu_type()) {
521 case CPU_BMIPS4350:
522 /*
523 * BMIPS4350 cannot relocate the normal vectors, but it
524 * can relocate the BEV=1 vectors. So CPU1 starts up at
525 * the relocated BEV=1, IV=0 general exception vector @
526 * 0xa000_0380.
527 *
528 * set_uncached_handler() is used here because:
529 * - CPU1 will run this from uncached space
530 * - None of the cacheflush functions are set up yet
531 */
532 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
533 &bmips_smp_int_vec, 0x80);
534 __sync();
535 return;
536 case CPU_BMIPS3300:
537 case CPU_BMIPS4380:
538 /*
539 * 0x8000_0000: reset/NMI (initially in kseg1)
540 * 0x8000_0400: normal vectors
541 */
542 new_ebase = 0x80000400;
543 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
544 break;
545 case CPU_BMIPS5000:
546 /*
547 * 0x8000_0000: reset/NMI (initially in kseg1)
548 * 0x8000_1000: normal vectors
549 */
550 new_ebase = 0x80001000;
551 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
552 write_c0_ebase(new_ebase);
553 break;
554 default:
555 return;
556 }
557
558 board_nmi_handler_setup = &bmips_nmi_handler_setup;
559 ebase = new_ebase;
560}
561
562asmlinkage void __weak plat_wired_tlb_setup(void)
563{
564 /*
565 * Called when starting/restarting a secondary CPU.
566 * Kernel stacks and other important data might only be accessible
567 * once the wired entries are present.
568 */
569}
570
571void __init bmips_cpu_setup(void)
572{
573 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
574 u32 __maybe_unused cfg;
575
576 switch (current_cpu_type()) {
577 case CPU_BMIPS3300:
578 /* Set BIU to async mode */
579 set_c0_brcm_bus_pll(BIT(22));
580 __sync();
581
582 /* put the BIU back in sync mode */
583 clear_c0_brcm_bus_pll(BIT(22));
584
585 /* clear BHTD to enable branch history table */
586 clear_c0_brcm_reset(BIT(16));
587
588 /* Flush and enable RAC */
589 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
590 __raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG);
591 __raw_readl(cbr + BMIPS_RAC_CONFIG);
592
593 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
594 __raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG);
595 __raw_readl(cbr + BMIPS_RAC_CONFIG);
596
597 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
598 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
599 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
600 break;
601
602 case CPU_BMIPS4380:
603 /* CBG workaround for early BMIPS4380 CPUs */
604 switch (read_c0_prid()) {
605 case 0x2a040:
606 case 0x2a042:
607 case 0x2a044:
608 case 0x2a060:
609 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
610 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
611 __raw_readl(cbr + BMIPS_L2_CONFIG);
612 }
613
614 /* clear BHTD to enable branch history table */
615 clear_c0_brcm_config_0(BIT(21));
616
617 /* XI/ROTR enable */
618 set_c0_brcm_config_0(BIT(23));
619 set_c0_brcm_cmt_ctrl(BIT(15));
620 break;
621
622 case CPU_BMIPS5000:
623 /* enable RDHWR, BRDHWR */
624 set_c0_brcm_config(BIT(17) | BIT(21));
625
626 /* Disable JTB */
627 __asm__ __volatile__(
628 " .set noreorder\n"
629 " li $8, 0x5a455048\n"
630 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
631 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
632 " li $9, 0x00008000\n"
633 " or $8, $8, $9\n"
634 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
635 " sync\n"
636 " li $8, 0x0\n"
637 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
638 " .set reorder\n"
639 : : : "$8", "$9");
640
641 /* XI enable */
642 set_c0_brcm_config(BIT(27));
643
644 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
645 __asm__ __volatile__(
646 " li $8, 0x5a455048\n"
647 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
648 " nop; nop; nop\n"
649 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
650 " lui $9, 0x0100\n"
651 " or $8, $9\n"
652 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
653 : : : "$8", "$9");
654 break;
655 }
656}