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1/*
2 * Copyright 2007-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF542_H
8#define _DEF_BF542_H
9
10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
11#include "defBF54x_base.h"
12
13/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
14
15/* ATAPI Registers */
16
17#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
18#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
19#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
20#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
21#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
22#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
23#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
24#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
25#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
26#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
27#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
28#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
29#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
30#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
31#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
32#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
33#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
34#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
35#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
36#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
37#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
38#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
39#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
40#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
41#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
42
43/* SDH Registers */
44
45#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
46#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
47#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
48#define SDH_COMMAND 0xffc0390c /* SDH Command */
49#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
50#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
51#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
52#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
53#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
54#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
55#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
56#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
57#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
58#define SDH_STATUS 0xffc03934 /* SDH Status */
59#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
60#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
61#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
62#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
63#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
64#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
65#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
66#define SDH_CFG 0xffc039c8 /* SDH Configuration */
67#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
68#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
69#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
70#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
71#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
72#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
73#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
74#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
75#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
76
77/* USB Control Registers */
78
79#define USB_FADDR 0xffc03c00 /* Function address register */
80#define USB_POWER 0xffc03c04 /* Power management register */
81#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
82#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
83#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
84#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
85#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
86#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
87#define USB_FRAME 0xffc03c20 /* USB frame number */
88#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
89#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
90#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
91#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
92
93/* USB Packet Control Registers */
94
95#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
96#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
97#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
98#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
99#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
100#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
101#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
102#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
103#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
104#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
105#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
106#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
107#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
108
109/* USB Endpoint FIFO Registers */
110
111#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
112#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
113#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
114#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
115#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
116#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
117#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
118#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
119
120/* USB OTG Control Registers */
121
122#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
123#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
124#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
125
126/* USB Phy Control Registers */
127
128#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
129#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
130#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
131#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
132#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
133
134/* (APHY_CNTRL is for ADI usage only) */
135
136#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
137
138/* (APHY_CALIB is for ADI usage only) */
139
140#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
141#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
142
143/* (PHY_TEST is for ADI usage only) */
144
145#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
146#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
147#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
148
149/* USB Endpoint 0 Control Registers */
150
151#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
152#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
153#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
154#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
155#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
156#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
157#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
158#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
159#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
160
161/* USB Endpoint 1 Control Registers */
162
163#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
164#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
165#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
166#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
167#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
168#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
169#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
170#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
171#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
172#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
173
174/* USB Endpoint 2 Control Registers */
175
176#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
177#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
178#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
179#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
180#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
181#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
182#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
183#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
184#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
185#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
186
187/* USB Endpoint 3 Control Registers */
188
189#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
190#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
191#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
192#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
193#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
194#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
195#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
196#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
197#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
198#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
199
200/* USB Endpoint 4 Control Registers */
201
202#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
203#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
204#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
205#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
206#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
207#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
208#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
209#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
210#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
211#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
212
213/* USB Endpoint 5 Control Registers */
214
215#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
216#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
217#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
218#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
219#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
220#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
221#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
222#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
223#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
224#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
225
226/* USB Endpoint 6 Control Registers */
227
228#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
229#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
230#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
231#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
232#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
233#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
234#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
235#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
236#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
237#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
238
239/* USB Endpoint 7 Control Registers */
240
241#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
242#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
243#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
244#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
245#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
246#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
247#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
248#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
249#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
250#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
251#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
252#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
253
254/* USB Channel 0 Config Registers */
255
256#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
257#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
258#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
259#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
260#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
261
262/* USB Channel 1 Config Registers */
263
264#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
265#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
266#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
267#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
268#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
269
270/* USB Channel 2 Config Registers */
271
272#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
273#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
274#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
275#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
276#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
277
278/* USB Channel 3 Config Registers */
279
280#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
281#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
282#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
283#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
284#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
285
286/* USB Channel 4 Config Registers */
287
288#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
289#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
290#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
291#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
292#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
293
294/* USB Channel 5 Config Registers */
295
296#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
297#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
298#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
299#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
300#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
301
302/* USB Channel 6 Config Registers */
303
304#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
305#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
306#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
307#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
308#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
309
310/* USB Channel 7 Config Registers */
311
312#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
313#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
314#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
315#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
316#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
317
318/* Keypad Registers */
319
320#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
321#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
322#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
323#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
324#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
325#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
326
327
328/* ********************************************************** */
329/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
330/* and MULTI BIT READ MACROS */
331/* ********************************************************** */
332
333/* Bit masks for KPAD_CTL */
334
335#define KPAD_EN 0x1 /* Keypad Enable */
336#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
337#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
338#define KPAD_COLEN 0xe000 /* Column Enable Width */
339
340/* Bit masks for KPAD_PRESCALE */
341
342#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
343
344/* Bit masks for KPAD_MSEL */
345
346#define DBON_SCALE 0xff /* Debounce Scale Value */
347#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
348
349/* Bit masks for KPAD_ROWCOL */
350
351#define KPAD_ROW 0xff /* Rows Pressed */
352#define KPAD_COL 0xff00 /* Columns Pressed */
353
354/* Bit masks for KPAD_STAT */
355
356#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
357#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
358#define KPAD_PRESSED 0x8 /* Key press current status */
359
360/* Bit masks for KPAD_SOFTEVAL */
361
362#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
363
364/* Bit masks for ATAPI_CONTROL */
365
366#define PIO_START 0x1 /* Start PIO/Reg Op */
367#define MULTI_START 0x2 /* Start Multi-DMA Op */
368#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
369#define XFER_DIR 0x8 /* Transfer Direction */
370#define IORDY_EN 0x10 /* IORDY Enable */
371#define FIFO_FLUSH 0x20 /* Flush FIFOs */
372#define SOFT_RST 0x40 /* Soft Reset */
373#define DEV_RST 0x80 /* Device Reset */
374#define TFRCNT_RST 0x100 /* Trans Count Reset */
375#define END_ON_TERM 0x200 /* End/Terminate Select */
376#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
377#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
378
379/* Bit masks for ATAPI_STATUS */
380
381#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
382#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
383#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
384#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
385
386/* Bit masks for ATAPI_DEV_ADDR */
387
388#define DEV_ADDR 0x1f /* Device Address */
389
390/* Bit masks for ATAPI_INT_MASK */
391
392#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
393#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
394#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
395#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
396#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
397#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
398#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
399#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
400#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
401
402/* Bit masks for ATAPI_INT_STATUS */
403
404#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
405#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
406#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
407#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
408#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
409#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
410#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
411#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
412#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
413
414/* Bit masks for ATAPI_LINE_STATUS */
415
416#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
417#define ATAPI_DASP 0x2 /* Device dasp to host line status */
418#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
419#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
420#define ATAPI_ADDR 0x70 /* ATAPI address line status */
421#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
422#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
423#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
424#define ATAPI_DIORN 0x400 /* ATAPI read line status */
425#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
426
427/* Bit masks for ATAPI_SM_STATE */
428
429#define PIO_CSTATE 0xf /* PIO mode state machine current state */
430#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
431#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
432#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
433
434/* Bit masks for ATAPI_TERMINATE */
435
436#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
437
438/* Bit masks for ATAPI_REG_TIM_0 */
439
440#define T2_REG 0xff /* End of cycle time for register access transfers */
441#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
442
443/* Bit masks for ATAPI_PIO_TIM_0 */
444
445#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
446#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
447#define T4_REG 0xf000 /* DIOW data hold */
448
449/* Bit masks for ATAPI_PIO_TIM_1 */
450
451#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
452
453/* Bit masks for ATAPI_MULTI_TIM_0 */
454
455#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
456#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
457
458/* Bit masks for ATAPI_MULTI_TIM_1 */
459
460#define TKW 0xff /* Selects DIOW negated pulsewidth */
461#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
462
463/* Bit masks for ATAPI_MULTI_TIM_2 */
464
465#define TH 0xff /* Selects DIOW data hold */
466#define TEOC 0xff00 /* Selects end of cycle for DMA */
467
468/* Bit masks for ATAPI_ULTRA_TIM_0 */
469
470#define TACK 0xff /* Selects setup and hold times for TACK */
471#define TENV 0xff00 /* Selects envelope time */
472
473/* Bit masks for ATAPI_ULTRA_TIM_1 */
474
475#define TDVS 0xff /* Selects data valid setup time */
476#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
477
478/* Bit masks for ATAPI_ULTRA_TIM_2 */
479
480#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
481#define TMLI 0xff00 /* Selects interlock time */
482
483/* Bit masks for ATAPI_ULTRA_TIM_3 */
484
485#define TZAH 0xff /* Selects minimum delay required for output */
486#define READY_PAUSE 0xff00 /* Selects ready to pause */
487
488/* Bit masks for USB_FADDR */
489
490#define FUNCTION_ADDRESS 0x7f /* Function address */
491
492/* Bit masks for USB_POWER */
493
494#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
495#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
496#define RESUME_MODE 0x4 /* DMA Mode */
497#define RESET 0x8 /* Reset indicator */
498#define HS_MODE 0x10 /* High Speed mode indicator */
499#define HS_ENABLE 0x20 /* high Speed Enable */
500#define SOFT_CONN 0x40 /* Soft connect */
501#define ISO_UPDATE 0x80 /* Isochronous update */
502
503/* Bit masks for USB_INTRTX */
504
505#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
506#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
507#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
508#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
509#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
510#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
511#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
512#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
513
514/* Bit masks for USB_INTRRX */
515
516#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
517#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
518#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
519#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
520#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
521#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
522#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
523
524/* Bit masks for USB_INTRTXE */
525
526#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
527#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
528#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
529#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
530#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
531#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
532#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
533#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
534
535/* Bit masks for USB_INTRRXE */
536
537#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
538#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
539#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
540#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
541#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
542#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
543#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
544
545/* Bit masks for USB_INTRUSB */
546
547#define SUSPEND_B 0x1 /* Suspend indicator */
548#define RESUME_B 0x2 /* Resume indicator */
549#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
550#define SOF_B 0x8 /* Start of frame */
551#define CONN_B 0x10 /* Connection indicator */
552#define DISCON_B 0x20 /* Disconnect indicator */
553#define SESSION_REQ_B 0x40 /* Session Request */
554#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
555
556/* Bit masks for USB_INTRUSBE */
557
558#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
559#define RESUME_BE 0x2 /* Resume indicator int enable */
560#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
561#define SOF_BE 0x8 /* Start of frame int enable */
562#define CONN_BE 0x10 /* Connection indicator int enable */
563#define DISCON_BE 0x20 /* Disconnect indicator int enable */
564#define SESSION_REQ_BE 0x40 /* Session Request int enable */
565#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
566
567/* Bit masks for USB_FRAME */
568
569#define FRAME_NUMBER 0x7ff /* Frame number */
570
571/* Bit masks for USB_INDEX */
572
573#define SELECTED_ENDPOINT 0xf /* selected endpoint */
574
575/* Bit masks for USB_GLOBAL_CTL */
576
577#define GLOBAL_ENA 0x1 /* enables USB module */
578#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
579#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
580#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
581#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
582#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
583#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
584#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
585#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
586#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
587#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
588#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
589#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
590#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
591#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
592
593/* Bit masks for USB_OTG_DEV_CTL */
594
595#define SESSION 0x1 /* session indicator */
596#define HOST_REQ 0x2 /* Host negotiation request */
597#define HOST_MODE 0x4 /* indicates USBDRC is a host */
598#define VBUS0 0x8 /* Vbus level indicator[0] */
599#define VBUS1 0x10 /* Vbus level indicator[1] */
600#define LSDEV 0x20 /* Low-speed indicator */
601#define FSDEV 0x40 /* Full or High-speed indicator */
602#define B_DEVICE 0x80 /* A' or 'B' device indicator */
603
604/* Bit masks for USB_OTG_VBUS_IRQ */
605
606#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
607#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
608#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
609#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
610#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
611#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
612
613/* Bit masks for USB_OTG_VBUS_MASK */
614
615#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
616#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
617#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
618#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
619#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
620#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
621
622/* Bit masks for USB_CSR0 */
623
624#define RXPKTRDY 0x1 /* data packet receive indicator */
625#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
626#define STALL_SENT 0x4 /* STALL handshake sent */
627#define DATAEND 0x8 /* Data end indicator */
628#define SETUPEND 0x10 /* Setup end */
629#define SENDSTALL 0x20 /* Send STALL handshake */
630#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
631#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
632#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
633#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
634#define SETUPPKT_H 0x8 /* send Setup token host mode */
635#define ERROR_H 0x10 /* timeout error indicator host mode */
636#define REQPKT_H 0x20 /* Request an IN transaction host mode */
637#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
638#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
639
640/* Bit masks for USB_COUNT0 */
641
642#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
643
644/* Bit masks for USB_NAKLIMIT0 */
645
646#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
647
648/* Bit masks for USB_TX_MAX_PACKET */
649
650#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
651
652/* Bit masks for USB_RX_MAX_PACKET */
653
654#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
655
656/* Bit masks for USB_TXCSR */
657
658#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
659#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
660#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
661#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
662#define STALL_SEND_T 0x10 /* issue a Stall handshake */
663#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
664#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
665#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
666#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
667#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
668#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
669#define ISO_T 0x4000 /* enable Isochronous transfers */
670#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
671#define ERROR_TH 0x4 /* error condition host mode */
672#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
673#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
674
675/* Bit masks for USB_TXCOUNT */
676
677#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
678
679/* Bit masks for USB_RXCSR */
680
681#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
682#define FIFO_FULL_R 0x2 /* FIFO not empty */
683#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
684#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
685#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
686#define STALL_SEND_R 0x20 /* issue a Stall handshake */
687#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
688#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
689#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
690#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
691#define DISNYET_R 0x1000 /* disable Nyet handshakes */
692#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
693#define ISO_R 0x4000 /* enable Isochronous transfers */
694#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
695#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
696#define REQPKT_RH 0x20 /* request an IN transaction host mode */
697#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
698#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
699#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
700#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
701
702/* Bit masks for USB_RXCOUNT */
703
704#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
705
706/* Bit masks for USB_TXTYPE */
707
708#define TARGET_EP_NO_T 0xf /* EP number */
709#define PROTOCOL_T 0xc /* transfer type */
710
711/* Bit masks for USB_TXINTERVAL */
712
713#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
714
715/* Bit masks for USB_RXTYPE */
716
717#define TARGET_EP_NO_R 0xf /* EP number */
718#define PROTOCOL_R 0xc /* transfer type */
719
720/* Bit masks for USB_RXINTERVAL */
721
722#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
723
724/* Bit masks for USB_DMA_INTERRUPT */
725
726#define DMA0_INT 0x1 /* DMA0 pending interrupt */
727#define DMA1_INT 0x2 /* DMA1 pending interrupt */
728#define DMA2_INT 0x4 /* DMA2 pending interrupt */
729#define DMA3_INT 0x8 /* DMA3 pending interrupt */
730#define DMA4_INT 0x10 /* DMA4 pending interrupt */
731#define DMA5_INT 0x20 /* DMA5 pending interrupt */
732#define DMA6_INT 0x40 /* DMA6 pending interrupt */
733#define DMA7_INT 0x80 /* DMA7 pending interrupt */
734
735/* Bit masks for USB_DMAxCONTROL */
736
737#define DMA_ENA 0x1 /* DMA enable */
738#define DIRECTION 0x2 /* direction of DMA transfer */
739#define MODE 0x4 /* DMA Bus error */
740#define INT_ENA 0x8 /* Interrupt enable */
741#define EPNUM 0xf0 /* EP number */
742#define BUSERROR 0x100 /* DMA Bus error */
743
744/* Bit masks for USB_DMAxADDRHIGH */
745
746#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
747
748/* Bit masks for USB_DMAxADDRLOW */
749
750#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
751
752/* Bit masks for USB_DMAxCOUNTHIGH */
753
754#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
755
756/* Bit masks for USB_DMAxCOUNTLOW */
757
758#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
759
760
761/* ******************************************* */
762/* MULTI BIT MACRO ENUMERATIONS */
763/* ******************************************* */
764
765
766#endif /* _DEF_BF542_H */
1/*
2 * Copyright 2007-2010 Analog Devices Inc.
3 *
4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF542_H
8#define _DEF_BF542_H
9
10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
11#include "defBF54x_base.h"
12
13/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
14
15/* ATAPI Registers */
16
17#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
18#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
19#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
20#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
21#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
22#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
23#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
24#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
25#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
26#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
27#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
28#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
29#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
30#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
31#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
32#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
33#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
34#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
35#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
36#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
37#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
38#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
39#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
40#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
41#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
42
43/* SDH Registers */
44
45#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
46#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
47#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
48#define SDH_COMMAND 0xffc0390c /* SDH Command */
49#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
50#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
51#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
52#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
53#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
54#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
55#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
56#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
57#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
58#define SDH_STATUS 0xffc03934 /* SDH Status */
59#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
60#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
61#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
62#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
63#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
64#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
65#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
66#define SDH_CFG 0xffc039c8 /* SDH Configuration */
67#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
68#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
69#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
70#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
71#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
72#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
73#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
74#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
75#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
76
77/* USB Control Registers */
78
79#define USB_FADDR 0xffc03c00 /* Function address register */
80#define USB_POWER 0xffc03c04 /* Power management register */
81#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
82#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
83#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
84#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
85#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
86#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
87#define USB_FRAME 0xffc03c20 /* USB frame number */
88#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
89#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
90#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
91#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
92
93/* USB Packet Control Registers */
94
95#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
96#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
97#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
98#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
99#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
100#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
101#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
102#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
103#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
104#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
105#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
106#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
107#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
108
109/* USB Endpoint FIFO Registers */
110
111#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
112#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
113#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
114#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
115#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
116#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
117#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
118#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
119
120/* USB OTG Control Registers */
121
122#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
123#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
124#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
125
126/* USB Phy Control Registers */
127
128#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
129#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
130#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
131#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
132#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
133
134/* (APHY_CNTRL is for ADI usage only) */
135
136#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
137
138/* (APHY_CALIB is for ADI usage only) */
139
140#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
141#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
142
143#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
144#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
145
146/* USB Endpoint 0 Control Registers */
147
148#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
149#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
150#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
151#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
152#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
153#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
154#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
155#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
156#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
157
158/* USB Endpoint 1 Control Registers */
159
160#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
161#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
162#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
163#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
164#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
165#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
166#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
167#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
168#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
169#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
170
171/* USB Endpoint 2 Control Registers */
172
173#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
174#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
175#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
176#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
177#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
178#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
179#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
180#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
181#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
182#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
183
184/* USB Endpoint 3 Control Registers */
185
186#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
187#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
188#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
189#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
190#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
191#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
192#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
193#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
194#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
195#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
196
197/* USB Endpoint 4 Control Registers */
198
199#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
200#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
201#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
202#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
203#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
204#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
205#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
206#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
207#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
208#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
209
210/* USB Endpoint 5 Control Registers */
211
212#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
213#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
214#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
215#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
216#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
217#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
218#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
219#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
220#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
221#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
222
223/* USB Endpoint 6 Control Registers */
224
225#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
226#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
227#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
228#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
229#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
230#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
231#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
232#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
233#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
234#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
235
236/* USB Endpoint 7 Control Registers */
237
238#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
239#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
240#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
241#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
242#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
243#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
244#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
245#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
246#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
247#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
248#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
249#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
250
251/* USB Channel 0 Config Registers */
252
253#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
254#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
255#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
256#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
257#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
258
259/* USB Channel 1 Config Registers */
260
261#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
262#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
263#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
264#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
265#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
266
267/* USB Channel 2 Config Registers */
268
269#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
270#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
271#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
272#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
273#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
274
275/* USB Channel 3 Config Registers */
276
277#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
278#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
279#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
280#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
281#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
282
283/* USB Channel 4 Config Registers */
284
285#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
286#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
287#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
288#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
289#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
290
291/* USB Channel 5 Config Registers */
292
293#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
294#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
295#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
296#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
297#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
298
299/* USB Channel 6 Config Registers */
300
301#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
302#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
303#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
304#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
305#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
306
307/* USB Channel 7 Config Registers */
308
309#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
310#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
311#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
312#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
313#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
314
315/* Keypad Registers */
316
317#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
318#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
319#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
320#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
321#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
322#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
323
324
325/* ********************************************************** */
326/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
327/* and MULTI BIT READ MACROS */
328/* ********************************************************** */
329
330/* Bit masks for KPAD_CTL */
331
332#define KPAD_EN 0x1 /* Keypad Enable */
333#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
334#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
335#define KPAD_COLEN 0xe000 /* Column Enable Width */
336
337/* Bit masks for KPAD_PRESCALE */
338
339#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
340
341/* Bit masks for KPAD_MSEL */
342
343#define DBON_SCALE 0xff /* Debounce Scale Value */
344#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
345
346/* Bit masks for KPAD_ROWCOL */
347
348#define KPAD_ROW 0xff /* Rows Pressed */
349#define KPAD_COL 0xff00 /* Columns Pressed */
350
351/* Bit masks for KPAD_STAT */
352
353#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
354#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
355#define KPAD_PRESSED 0x8 /* Key press current status */
356
357/* Bit masks for KPAD_SOFTEVAL */
358
359#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
360
361/* Bit masks for ATAPI_CONTROL */
362
363#define PIO_START 0x1 /* Start PIO/Reg Op */
364#define MULTI_START 0x2 /* Start Multi-DMA Op */
365#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
366#define XFER_DIR 0x8 /* Transfer Direction */
367#define IORDY_EN 0x10 /* IORDY Enable */
368#define FIFO_FLUSH 0x20 /* Flush FIFOs */
369#define SOFT_RST 0x40 /* Soft Reset */
370#define DEV_RST 0x80 /* Device Reset */
371#define TFRCNT_RST 0x100 /* Trans Count Reset */
372#define END_ON_TERM 0x200 /* End/Terminate Select */
373#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
374#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
375
376/* Bit masks for ATAPI_STATUS */
377
378#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
379#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
380#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
381#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
382
383/* Bit masks for ATAPI_DEV_ADDR */
384
385#define DEV_ADDR 0x1f /* Device Address */
386
387/* Bit masks for ATAPI_INT_MASK */
388
389#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
390#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
391#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
392#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
393#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
394#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
395#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
396#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
397#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
398
399/* Bit masks for ATAPI_INT_STATUS */
400
401#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
402#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
403#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
404#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
405#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
406#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
407#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
408#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
409#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
410
411/* Bit masks for ATAPI_LINE_STATUS */
412
413#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
414#define ATAPI_DASP 0x2 /* Device dasp to host line status */
415#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
416#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
417#define ATAPI_ADDR 0x70 /* ATAPI address line status */
418#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
419#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
420#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
421#define ATAPI_DIORN 0x400 /* ATAPI read line status */
422#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
423
424/* Bit masks for ATAPI_SM_STATE */
425
426#define PIO_CSTATE 0xf /* PIO mode state machine current state */
427#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
428#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
429#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
430
431/* Bit masks for ATAPI_TERMINATE */
432
433#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
434
435/* Bit masks for ATAPI_REG_TIM_0 */
436
437#define T2_REG 0xff /* End of cycle time for register access transfers */
438#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
439
440/* Bit masks for ATAPI_PIO_TIM_0 */
441
442#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
443#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
444#define T4_REG 0xf000 /* DIOW data hold */
445
446/* Bit masks for ATAPI_PIO_TIM_1 */
447
448#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
449
450/* Bit masks for ATAPI_MULTI_TIM_0 */
451
452#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
453#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
454
455/* Bit masks for ATAPI_MULTI_TIM_1 */
456
457#define TKW 0xff /* Selects DIOW negated pulsewidth */
458#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
459
460/* Bit masks for ATAPI_MULTI_TIM_2 */
461
462#define TH 0xff /* Selects DIOW data hold */
463#define TEOC 0xff00 /* Selects end of cycle for DMA */
464
465/* Bit masks for ATAPI_ULTRA_TIM_0 */
466
467#define TACK 0xff /* Selects setup and hold times for TACK */
468#define TENV 0xff00 /* Selects envelope time */
469
470/* Bit masks for ATAPI_ULTRA_TIM_1 */
471
472#define TDVS 0xff /* Selects data valid setup time */
473#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
474
475/* Bit masks for ATAPI_ULTRA_TIM_2 */
476
477#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
478#define TMLI 0xff00 /* Selects interlock time */
479
480/* Bit masks for ATAPI_ULTRA_TIM_3 */
481
482#define TZAH 0xff /* Selects minimum delay required for output */
483#define READY_PAUSE 0xff00 /* Selects ready to pause */
484
485/* Bit masks for USB_FADDR */
486
487#define FUNCTION_ADDRESS 0x7f /* Function address */
488
489/* Bit masks for USB_POWER */
490
491#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
492#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
493#define RESUME_MODE 0x4 /* DMA Mode */
494#define RESET 0x8 /* Reset indicator */
495#define HS_MODE 0x10 /* High Speed mode indicator */
496#define HS_ENABLE 0x20 /* high Speed Enable */
497#define SOFT_CONN 0x40 /* Soft connect */
498#define ISO_UPDATE 0x80 /* Isochronous update */
499
500/* Bit masks for USB_INTRTX */
501
502#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
503#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
504#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
505#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
506#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
507#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
508#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
509#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
510
511/* Bit masks for USB_INTRRX */
512
513#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
514#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
515#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
516#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
517#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
518#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
519#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
520
521/* Bit masks for USB_INTRTXE */
522
523#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
524#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
525#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
526#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
527#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
528#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
529#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
530#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
531
532/* Bit masks for USB_INTRRXE */
533
534#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
535#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
536#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
537#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
538#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
539#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
540#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
541
542/* Bit masks for USB_INTRUSB */
543
544#define SUSPEND_B 0x1 /* Suspend indicator */
545#define RESUME_B 0x2 /* Resume indicator */
546#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
547#define SOF_B 0x8 /* Start of frame */
548#define CONN_B 0x10 /* Connection indicator */
549#define DISCON_B 0x20 /* Disconnect indicator */
550#define SESSION_REQ_B 0x40 /* Session Request */
551#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
552
553/* Bit masks for USB_INTRUSBE */
554
555#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
556#define RESUME_BE 0x2 /* Resume indicator int enable */
557#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
558#define SOF_BE 0x8 /* Start of frame int enable */
559#define CONN_BE 0x10 /* Connection indicator int enable */
560#define DISCON_BE 0x20 /* Disconnect indicator int enable */
561#define SESSION_REQ_BE 0x40 /* Session Request int enable */
562#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
563
564/* Bit masks for USB_FRAME */
565
566#define FRAME_NUMBER 0x7ff /* Frame number */
567
568/* Bit masks for USB_INDEX */
569
570#define SELECTED_ENDPOINT 0xf /* selected endpoint */
571
572/* Bit masks for USB_GLOBAL_CTL */
573
574#define GLOBAL_ENA 0x1 /* enables USB module */
575#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
576#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
577#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
578#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
579#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
580#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
581#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
582#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
583#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
584#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
585#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
586#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
587#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
588#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
589
590/* Bit masks for USB_OTG_DEV_CTL */
591
592#define SESSION 0x1 /* session indicator */
593#define HOST_REQ 0x2 /* Host negotiation request */
594#define HOST_MODE 0x4 /* indicates USBDRC is a host */
595#define VBUS0 0x8 /* Vbus level indicator[0] */
596#define VBUS1 0x10 /* Vbus level indicator[1] */
597#define LSDEV 0x20 /* Low-speed indicator */
598#define FSDEV 0x40 /* Full or High-speed indicator */
599#define B_DEVICE 0x80 /* A' or 'B' device indicator */
600
601/* Bit masks for USB_OTG_VBUS_IRQ */
602
603#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
604#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
605#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
606#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
607#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
608#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
609
610/* Bit masks for USB_OTG_VBUS_MASK */
611
612#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
613#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
614#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
615#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
616#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
617#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
618
619/* Bit masks for USB_CSR0 */
620
621#define RXPKTRDY 0x1 /* data packet receive indicator */
622#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
623#define STALL_SENT 0x4 /* STALL handshake sent */
624#define DATAEND 0x8 /* Data end indicator */
625#define SETUPEND 0x10 /* Setup end */
626#define SENDSTALL 0x20 /* Send STALL handshake */
627#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
628#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
629#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
630#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
631#define SETUPPKT_H 0x8 /* send Setup token host mode */
632#define ERROR_H 0x10 /* timeout error indicator host mode */
633#define REQPKT_H 0x20 /* Request an IN transaction host mode */
634#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
635#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
636
637/* Bit masks for USB_COUNT0 */
638
639#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
640
641/* Bit masks for USB_NAKLIMIT0 */
642
643#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
644
645/* Bit masks for USB_TX_MAX_PACKET */
646
647#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
648
649/* Bit masks for USB_RX_MAX_PACKET */
650
651#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
652
653/* Bit masks for USB_TXCSR */
654
655#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
656#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
657#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
658#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
659#define STALL_SEND_T 0x10 /* issue a Stall handshake */
660#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
661#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
662#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
663#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
664#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
665#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
666#define ISO_T 0x4000 /* enable Isochronous transfers */
667#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
668#define ERROR_TH 0x4 /* error condition host mode */
669#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
670#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
671
672/* Bit masks for USB_TXCOUNT */
673
674#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
675
676/* Bit masks for USB_RXCSR */
677
678#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
679#define FIFO_FULL_R 0x2 /* FIFO not empty */
680#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
681#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
682#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
683#define STALL_SEND_R 0x20 /* issue a Stall handshake */
684#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
685#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
686#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
687#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
688#define DISNYET_R 0x1000 /* disable Nyet handshakes */
689#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
690#define ISO_R 0x4000 /* enable Isochronous transfers */
691#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
692#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
693#define REQPKT_RH 0x20 /* request an IN transaction host mode */
694#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
695#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
696#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
697#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
698
699/* Bit masks for USB_RXCOUNT */
700
701#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
702
703/* Bit masks for USB_TXTYPE */
704
705#define TARGET_EP_NO_T 0xf /* EP number */
706#define PROTOCOL_T 0xc /* transfer type */
707
708/* Bit masks for USB_TXINTERVAL */
709
710#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
711
712/* Bit masks for USB_RXTYPE */
713
714#define TARGET_EP_NO_R 0xf /* EP number */
715#define PROTOCOL_R 0xc /* transfer type */
716
717/* Bit masks for USB_RXINTERVAL */
718
719#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
720
721/* Bit masks for USB_DMA_INTERRUPT */
722
723#define DMA0_INT 0x1 /* DMA0 pending interrupt */
724#define DMA1_INT 0x2 /* DMA1 pending interrupt */
725#define DMA2_INT 0x4 /* DMA2 pending interrupt */
726#define DMA3_INT 0x8 /* DMA3 pending interrupt */
727#define DMA4_INT 0x10 /* DMA4 pending interrupt */
728#define DMA5_INT 0x20 /* DMA5 pending interrupt */
729#define DMA6_INT 0x40 /* DMA6 pending interrupt */
730#define DMA7_INT 0x80 /* DMA7 pending interrupt */
731
732/* Bit masks for USB_DMAxCONTROL */
733
734#define DMA_ENA 0x1 /* DMA enable */
735#define DIRECTION 0x2 /* direction of DMA transfer */
736#define MODE 0x4 /* DMA Bus error */
737#define INT_ENA 0x8 /* Interrupt enable */
738#define EPNUM 0xf0 /* EP number */
739#define BUSERROR 0x100 /* DMA Bus error */
740
741/* Bit masks for USB_DMAxADDRHIGH */
742
743#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
744
745/* Bit masks for USB_DMAxADDRLOW */
746
747#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
748
749/* Bit masks for USB_DMAxCOUNTHIGH */
750
751#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
752
753/* Bit masks for USB_DMAxCOUNTLOW */
754
755#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
756
757
758/* ******************************************* */
759/* MULTI BIT MACRO ENUMERATIONS */
760/* ******************************************* */
761
762
763#endif /* _DEF_BF542_H */