1/*
  2 * linux/arch/arm/include/asm/hardware/coresight.h
  3 *
  4 * CoreSight components' registers
  5 *
  6 * Copyright (C) 2009 Nokia Corporation.
  7 * Alexander Shishkin
  8 *
  9 * This program is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License version 2 as
 11 * published by the Free Software Foundation.
 12 */
 13
 14#ifndef __ASM_HARDWARE_CORESIGHT_H
 15#define __ASM_HARDWARE_CORESIGHT_H
 16
 17#define TRACER_ACCESSED_BIT	0
 18#define TRACER_RUNNING_BIT	1
 19#define TRACER_CYCLE_ACC_BIT	2
 20#define TRACER_ACCESSED		BIT(TRACER_ACCESSED_BIT)
 21#define TRACER_RUNNING		BIT(TRACER_RUNNING_BIT)
 22#define TRACER_CYCLE_ACC	BIT(TRACER_CYCLE_ACC_BIT)
 23
 24#define TRACER_TIMEOUT 10000
 25
 26#define etm_writel(t, v, x) \
 27	(__raw_writel((v), (t)->etm_regs + (x)))
 28#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
 29
 30/* CoreSight Management Registers */
 31#define CSMR_LOCKACCESS 0xfb0
 32#define CSMR_LOCKSTATUS 0xfb4
 33#define CSMR_AUTHSTATUS 0xfb8
 34#define CSMR_DEVID	0xfc8
 35#define CSMR_DEVTYPE	0xfcc
 36/* CoreSight Component Registers */
 37#define CSCR_CLASS	0xff4
 38
 39#define UNLOCK_MAGIC	0xc5acce55
 40
 41/* ETM control register, "ETM Architecture", 3.3.1 */
 42#define ETMR_CTRL		0
 43#define ETMCTRL_POWERDOWN	1
 44#define ETMCTRL_PROGRAM		(1 << 10)
 45#define ETMCTRL_PORTSEL		(1 << 11)
 46#define ETMCTRL_DO_CONTEXTID	(3 << 14)
 47#define ETMCTRL_PORTMASK1	(7 << 4)
 48#define ETMCTRL_PORTMASK2	(1 << 21)
 49#define ETMCTRL_PORTMASK	(ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
 50#define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21)
 51#define ETMCTRL_DO_CPRT		(1 << 1)
 52#define ETMCTRL_DATAMASK	(3 << 2)
 53#define ETMCTRL_DATA_DO_DATA	(1 << 2)
 54#define ETMCTRL_DATA_DO_ADDR	(1 << 3)
 55#define ETMCTRL_DATA_DO_BOTH	(ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
 56#define ETMCTRL_BRANCH_OUTPUT	(1 << 8)
 57#define ETMCTRL_CYCLEACCURATE	(1 << 12)
 58
 59/* ETM configuration code register */
 60#define ETMR_CONFCODE		(0x04)
 61
 62/* ETM trace start/stop resource control register */
 63#define ETMR_TRACESSCTRL	(0x18)
 64
 65/* ETM trigger event register */
 66#define ETMR_TRIGEVT		(0x08)
 67
 68/* address access type register bits, "ETM architecture",
 69 * table 3-27 */
 70/* - access type */
 71#define ETMAAT_IFETCH		0
 72#define ETMAAT_IEXEC		1
 73#define ETMAAT_IEXECPASS	2
 74#define ETMAAT_IEXECFAIL	3
 75#define ETMAAT_DLOADSTORE	4
 76#define ETMAAT_DLOAD		5
 77#define ETMAAT_DSTORE		6
 78/* - comparison access size */
 79#define ETMAAT_JAVA		(0 << 3)
 80#define ETMAAT_THUMB		(1 << 3)
 81#define ETMAAT_ARM		(3 << 3)
 82/* - data value comparison control */
 83#define ETMAAT_NOVALCMP		(0 << 5)
 84#define ETMAAT_VALMATCH		(1 << 5)
 85#define ETMAAT_VALNOMATCH	(3 << 5)
 86/* - exact match */
 87#define ETMAAT_EXACTMATCH	(1 << 7)
 88/* - context id comparator control */
 89#define ETMAAT_IGNCONTEXTID	(0 << 8)
 90#define ETMAAT_VALUE1		(1 << 8)
 91#define ETMAAT_VALUE2		(2 << 8)
 92#define ETMAAT_VALUE3		(3 << 8)
 93/* - security level control */
 94#define ETMAAT_IGNSECURITY	(0 << 10)
 95#define ETMAAT_NSONLY		(1 << 10)
 96#define ETMAAT_SONLY		(2 << 10)
 97
 98#define ETMR_COMP_VAL(x)	(0x40 + (x) * 4)
 99#define ETMR_COMP_ACC_TYPE(x)	(0x80 + (x) * 4)
100
101/* ETM status register, "ETM Architecture", 3.3.2 */
102#define ETMR_STATUS		(0x10)
103#define ETMST_OVERFLOW		BIT(0)
104#define ETMST_PROGBIT		BIT(1)
105#define ETMST_STARTSTOP		BIT(2)
106#define ETMST_TRIGGER		BIT(3)
107
108#define etm_progbit(t)		(etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
109#define etm_started(t)		(etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
110#define etm_triggered(t)	(etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)
111
112#define ETMR_TRACEENCTRL2	0x1c
113#define ETMR_TRACEENCTRL	0x24
114#define ETMTE_INCLEXCL		BIT(24)
115#define ETMR_TRACEENEVT		0x20
116#define ETMCTRL_OPTS		(ETMCTRL_DO_CPRT | \
117				ETMCTRL_DATA_DO_ADDR | \
118				ETMCTRL_BRANCH_OUTPUT | \
119				ETMCTRL_DO_CONTEXTID)
120
121/* ETM management registers, "ETM Architecture", 3.5.24 */
122#define ETMMR_OSLAR	0x300
123#define ETMMR_OSLSR	0x304
124#define ETMMR_OSSRR	0x308
125#define ETMMR_PDSR	0x314
126
127/* ETB registers, "CoreSight Components TRM", 9.3 */
128#define ETBR_DEPTH		0x04
129#define ETBR_STATUS		0x0c
130#define ETBR_READMEM		0x10
131#define ETBR_READADDR		0x14
132#define ETBR_WRITEADDR		0x18
133#define ETBR_TRIGGERCOUNT	0x1c
134#define ETBR_CTRL		0x20
135#define ETBR_FORMATTERCTRL	0x304
136#define ETBFF_ENFTC		1
137#define ETBFF_ENFCONT		BIT(1)
138#define ETBFF_FONFLIN		BIT(4)
139#define ETBFF_MANUAL_FLUSH	BIT(6)
140#define ETBFF_TRIGIN		BIT(8)
141#define ETBFF_TRIGEVT		BIT(9)
142#define ETBFF_TRIGFL		BIT(10)
143
144#define etb_writel(t, v, x) \
145	(__raw_writel((v), (t)->etb_regs + (x)))
146#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
147
148#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
149#define etm_unlock(t) \
150	do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
151
152#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
153#define etb_unlock(t) \
154	do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
155
156#endif /* __ASM_HARDWARE_CORESIGHT_H */
157