1/*
  2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 */
  9
 10#include <linux/interrupt.h>
 11#include <linux/module.h>
 12#include <linux/of.h>
 13#include <linux/irqdomain.h>
 14#include <linux/irqchip.h>
 15#include <asm/irq.h>
 16
 17#define TIMER0_IRQ	3	/* Fixed by ISA */
 18
 19/*
 20 * Early Hardware specific Interrupt setup
 21 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
 22 * -Called very early (start_kernel -> setup_arch -> setup_processor)
 23 *
 24 * what it does ?
 25 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
 26 */
 27void arc_init_IRQ(void)
 28{
 29	int level_mask = 0;
 30
 31       /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
 32	level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
 33
 34	/*
 35	 * Write to register, even if no LV2 IRQs configured to reset it
 36	 * in case bootloader had mucked with it
 37	 */
 38	write_aux_reg(AUX_IRQ_LEV, level_mask);
 39
 40	if (level_mask)
 41		pr_info("Level-2 interrupts bitset %x\n", level_mask);
 42}
 43
 44/*
 45 * ARC700 core includes a simple on-chip intc supporting
 46 * -per IRQ enable/disable
 47 * -2 levels of interrupts (high/low)
 48 * -all interrupts being level triggered
 49 *
 50 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
 51 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
 52 * below, per IRQ.
 53 */
 54
 55static void arc_irq_mask(struct irq_data *data)
 56{
 57	unsigned int ienb;
 58
 59	ienb = read_aux_reg(AUX_IENABLE);
 60	ienb &= ~(1 << data->hwirq);
 61	write_aux_reg(AUX_IENABLE, ienb);
 62}
 63
 64static void arc_irq_unmask(struct irq_data *data)
 65{
 66	unsigned int ienb;
 67
 68	ienb = read_aux_reg(AUX_IENABLE);
 69	ienb |= (1 << data->hwirq);
 70	write_aux_reg(AUX_IENABLE, ienb);
 71}
 72
 73static struct irq_chip onchip_intc = {
 74	.name           = "ARC In-core Intc",
 75	.irq_mask	= arc_irq_mask,
 76	.irq_unmask	= arc_irq_unmask,
 77};
 78
 79static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
 80			       irq_hw_number_t hw)
 81{
 82	switch (hw) {
 83	case TIMER0_IRQ:
 84		irq_set_percpu_devid(irq);
 85		irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
 86		break;
 87	default:
 88		irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
 89	}
 90	return 0;
 91}
 92
 93static const struct irq_domain_ops arc_intc_domain_ops = {
 94	.xlate = irq_domain_xlate_onecell,
 95	.map = arc_intc_domain_map,
 96};
 97
 98static int __init
 99init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
100{
101	struct irq_domain *root_domain;
102
103	if (parent)
104		panic("DeviceTree incore intc not a root irq controller\n");
105
106	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
107					    &arc_intc_domain_ops, NULL);
108	if (!root_domain)
109		panic("root irq domain not avail\n");
110
111	/*
112	 * Needed for primary domain lookup to succeed
113	 * This is a primary irqchip, and can never have a parent
114	 */
115	irq_set_default_host(root_domain);
116
117	return 0;
118}
119
120IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
121
122/*
123 * arch_local_irq_enable - Enable interrupts.
124 *
125 * 1. Explicitly called to re-enable interrupts
126 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
127 *    which maybe in hard ISR itself
128 *
129 * Semantics of this function change depending on where it is called from:
130 *
131 * -If called from hard-ISR, it must not invert interrupt priorities
132 *  e.g. suppose TIMER is high priority (Level 2) IRQ
133 *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
134 *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
135 * -If called from soft-ISR, it must re-enable all interrupts
136 *    soft ISR are low prioity jobs which can be very slow, thus all IRQs
137 *    must be enabled while they run.
138 *    Now hardware context wise we may still be in L2 ISR (not done rtie)
139 *    still we must re-enable both L1 and L2 IRQs
140 *  Another twist is prev scenario with flow being
141 *     L1 ISR ==> interrupted by L2 ISR  ==> L2 soft ISR
142 *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
143 *     over-written (this is deficiency in ARC700 Interrupt mechanism)
144 */
145
146#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS	/* Complex version for 2 IRQ levels */
147
148void arch_local_irq_enable(void)
149{
150	unsigned long flags = arch_local_save_flags();
151
152	if (flags & STATUS_A2_MASK)
153		flags |= STATUS_E2_MASK;
154	else if (flags & STATUS_A1_MASK)
155		flags |= STATUS_E1_MASK;
156
157	arch_local_irq_restore(flags);
158}
159
160EXPORT_SYMBOL(arch_local_irq_enable);
161#endif