1/*
  2 * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 */
  9
 10#include <linux/interrupt.h>
 11#include <linux/module.h>
 12#include <linux/of.h>
 13#include <linux/irqdomain.h>
 14#include <linux/irqchip.h>
 15#include <asm/irq.h>
 16
 17/*
 18 * Early Hardware specific Interrupt setup
 19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
 20 * -Platform Independent (must for any ARC Core)
 21 * -Needed for each CPU (hence not foldable into init_IRQ)
 22 */
 23void arc_init_IRQ(void)
 24{
 25	unsigned int tmp, irq_prio;
 26
 27	struct irq_build {
 28#ifdef CONFIG_CPU_BIG_ENDIAN
 29		unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
 30#else
 31		unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
 32#endif
 33	} irq_bcr;
 34
 35	struct aux_irq_ctrl {
 36#ifdef CONFIG_CPU_BIG_ENDIAN
 37		unsigned int res3:18, save_idx_regs:1, res2:1,
 38			     save_u_to_u:1, save_lp_regs:1, save_blink:1,
 39			     res:4, save_nr_gpr_pairs:5;
 40#else
 41		unsigned int save_nr_gpr_pairs:5, res:4,
 42			     save_blink:1, save_lp_regs:1, save_u_to_u:1,
 43			     res2:1, save_idx_regs:1, res3:18;
 44#endif
 45	} ictrl;
 46
 47	*(unsigned int *)&ictrl = 0;
 48
 49	ictrl.save_nr_gpr_pairs = 6;	/* r0 to r11 (r12 saved manually) */
 50	ictrl.save_blink = 1;
 51	ictrl.save_lp_regs = 1;		/* LP_COUNT, LP_START, LP_END */
 52	ictrl.save_u_to_u = 0;		/* user ctxt saved on kernel stack */
 53	ictrl.save_idx_regs = 1;	/* JLI, LDI, EI */
 54
 55	WRITE_AUX(AUX_IRQ_CTRL, ictrl);
 56
 57	/*
 58	 * ARCv2 core intc provides multiple interrupt priorities (upto 16).
 59	 * Typical builds though have only two levels (0-high, 1-low)
 60	 * Linux by default uses lower prio 1 for most irqs, reserving 0 for
 61	 * NMI style interrupts in future (say perf)
 62	 */
 63
 64	READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
 65
 66	irq_prio = irq_bcr.prio;	/* Encoded as N-1 for N levels */
 67	pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
 68		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
 69		irq_bcr.firq ? " FIRQ (not used)":"");
 70
 71	/* setup status32, don't enable intr yet as kernel doesn't want */
 72	tmp = read_aux_reg(0xa);
 73	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
 74	tmp &= ~STATUS_IE_MASK;
 75	asm volatile("kflag %0	\n"::"r"(tmp));
 76}
 77
 78static void arcv2_irq_mask(struct irq_data *data)
 79{
 80	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
 81	write_aux_reg(AUX_IRQ_ENABLE, 0);
 82}
 83
 84static void arcv2_irq_unmask(struct irq_data *data)
 85{
 86	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
 87	write_aux_reg(AUX_IRQ_ENABLE, 1);
 88}
 89
 90void arcv2_irq_enable(struct irq_data *data)
 91{
 92	/* set default priority */
 93	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
 94	write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
 95
 96	/*
 97	 * hw auto enables (linux unmask) all by default
 98	 * So no need to do IRQ_ENABLE here
 99	 * XXX: However OSCI LAN need it
100	 */
101	write_aux_reg(AUX_IRQ_ENABLE, 1);
102}
103
104static struct irq_chip arcv2_irq_chip = {
105	.name           = "ARCv2 core Intc",
106	.irq_mask	= arcv2_irq_mask,
107	.irq_unmask	= arcv2_irq_unmask,
108	.irq_enable	= arcv2_irq_enable
109};
110
111static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
112			 irq_hw_number_t hw)
113{
114	/*
115	 * core intc IRQs [16, 23]:
116	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
117	 */
118	if (hw < 24) {
119		/*
120		 * A subsequent request_percpu_irq() fails if percpu_devid is
121		 * not set. That in turns sets NOAUTOEN, meaning each core needs
122		 * to call enable_percpu_irq()
123		 */
124		irq_set_percpu_devid(irq);
125		irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
126	} else {
127		irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
128	}
129
130	return 0;
131}
132
133static const struct irq_domain_ops arcv2_irq_ops = {
134	.xlate = irq_domain_xlate_onecell,
135	.map = arcv2_irq_map,
136};
137
138
139static int __init
140init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
141{
142	struct irq_domain *root_domain;
143
144	if (parent)
145		panic("DeviceTree incore intc not a root irq controller\n");
146
147	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
148	if (!root_domain)
149		panic("root irq domain not avail\n");
150
151	/*
152	 * Needed for primary domain lookup to succeed
153	 * This is a primary irqchip, and can never have a parent
154	 */
155	irq_set_default_host(root_domain);
156
157#ifdef CONFIG_SMP
158	irq_create_mapping(root_domain, IPI_IRQ);
159#endif
160	irq_create_mapping(root_domain, SOFTIRQ_IRQ);
161
162	return 0;
163}
164
165IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);