1/*
   2 * ATI Mach64 Register Definitions
   3 *
   4 * Copyright (C) 1997 Michael AK Tesch
   5 *  written with much help from Jon Howell
   6 *
   7 * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
   8 *	
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version
  12 * 2 of the License, or (at your option) any later version.
  13 */
  14
  15/*
  16 * most of the rest of this file comes from ATI sample code
  17 */
  18#ifndef REGMACH64_H
  19#define REGMACH64_H
  20
  21/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
  22
  23/* Accelerator CRTC */
  24#define CRTC_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
  25#define CRTC2_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
  26#define CRTC_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
  27#define CRTC2_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
  28#define CRTC_H_SYNC_STRT	0x0004
  29#define CRTC2_H_SYNC_STRT	0x0004
  30#define CRTC_H_SYNC_DLY		0x0005
  31#define CRTC2_H_SYNC_DLY	0x0005
  32#define CRTC_H_SYNC_WID		0x0006
  33#define CRTC2_H_SYNC_WID	0x0006
  34#define CRTC_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
  35#define CRTC2_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
  36#define CRTC_V_TOTAL		0x0008
  37#define CRTC2_V_TOTAL		0x0008
  38#define CRTC_V_DISP		0x000A
  39#define CRTC2_V_DISP		0x000A
  40#define CRTC_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
  41#define CRTC2_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
  42#define CRTC_V_SYNC_STRT	0x000C
  43#define CRTC2_V_SYNC_STRT	0x000C
  44#define CRTC_V_SYNC_WID		0x000E
  45#define CRTC2_V_SYNC_WID	0x000E
  46#define CRTC_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
  47#define CRTC2_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
  48#define CRTC_OFF_PITCH		0x0014	/* Dword offset 0_05 */
  49#define CRTC_OFFSET		0x0014
  50#define CRTC_PITCH		0x0016
  51#define CRTC_INT_CNTL		0x0018	/* Dword offset 0_06 */
  52#define CRTC_GEN_CNTL		0x001C	/* Dword offset 0_07 */
  53#define CRTC_PIX_WIDTH		0x001D
  54#define CRTC_FIFO		0x001E
  55#define CRTC_EXT_DISP		0x001F
  56
  57/* Memory Buffer Control */
  58#define DSP_CONFIG		0x0020	/* Dword offset 0_08 */
  59#define PM_DSP_CONFIG		0x0020	/* Dword offset 0_08 (Mobility Only) */
  60#define DSP_ON_OFF		0x0024	/* Dword offset 0_09 */
  61#define PM_DSP_ON_OFF		0x0024	/* Dword offset 0_09 (Mobility Only) */
  62#define TIMER_CONFIG		0x0028	/* Dword offset 0_0A */
  63#define MEM_BUF_CNTL		0x002C	/* Dword offset 0_0B */
  64#define MEM_ADDR_CONFIG		0x0034	/* Dword offset 0_0D */
  65
  66/* Accelerator CRTC */
  67#define CRT_TRAP		0x0038	/* Dword offset 0_0E */
  68
  69#define I2C_CNTL_0		0x003C	/* Dword offset 0_0F */
  70
  71#define DSTN_CONTROL_LG		0x003C	/* Dword offset 0_0F (LG) */
  72
  73/* Overscan */
  74#define OVR_CLR			0x0040	/* Dword offset 0_10 */
  75#define OVR2_CLR		0x0040	/* Dword offset 0_10 */
  76#define OVR_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
  77#define OVR2_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
  78#define OVR_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
  79#define OVR2_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
  80
  81/* Memory Buffer Control */
  82#define VGA_DSP_CONFIG		0x004C	/* Dword offset 0_13 */
  83#define PM_VGA_DSP_CONFIG	0x004C	/* Dword offset 0_13 (Mobility Only) */
  84#define VGA_DSP_ON_OFF		0x0050	/* Dword offset 0_14 */
  85#define PM_VGA_DSP_ON_OFF	0x0050	/* Dword offset 0_14 (Mobility Only) */
  86#define DSP2_CONFIG		0x0054	/* Dword offset 0_15 */
  87#define PM_DSP2_CONFIG		0x0054	/* Dword offset 0_15 (Mobility Only) */
  88#define DSP2_ON_OFF		0x0058	/* Dword offset 0_16 */
  89#define PM_DSP2_ON_OFF		0x0058	/* Dword offset 0_16 (Mobility Only) */
  90
  91/* Accelerator CRTC */
  92#define CRTC2_OFF_PITCH		0x005C	/* Dword offset 0_17 */
  93
  94/* Hardware Cursor */
  95#define CUR_CLR0		0x0060	/* Dword offset 0_18 */
  96#define CUR2_CLR0		0x0060	/* Dword offset 0_18 */
  97#define CUR_CLR1		0x0064	/* Dword offset 0_19 */
  98#define CUR2_CLR1		0x0064	/* Dword offset 0_19 */
  99#define CUR_OFFSET		0x0068	/* Dword offset 0_1A */
 100#define CUR2_OFFSET		0x0068	/* Dword offset 0_1A */
 101#define CUR_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
 102#define CUR2_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
 103#define CUR_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
 104#define CUR2_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
 105
 106#define CNFG_PANEL_LG		0x0074	/* Dword offset 0_1D (LG) */
 107
 108/* General I/O Control */
 109#define GP_IO			0x0078	/* Dword offset 0_1E */
 110
 111/* Test and Debug */
 112#define HW_DEBUG		0x007C	/* Dword offset 0_1F */
 113
 114/* Scratch Pad and Test */
 115#define SCRATCH_REG0		0x0080	/* Dword offset 0_20 */
 116#define SCRATCH_REG1		0x0084	/* Dword offset 0_21 */
 117#define SCRATCH_REG2		0x0088	/* Dword offset 0_22 */
 118#define SCRATCH_REG3		0x008C	/* Dword offset 0_23 */
 119
 120/* Clock Control */
 121#define CLOCK_CNTL			0x0090	/* Dword offset 0_24 */
 122/* CLOCK_CNTL register constants CT LAYOUT */
 123#define CLOCK_SEL			0x0f
 124#define CLOCK_SEL_INTERNAL		0x03
 125#define CLOCK_SEL_EXTERNAL		0x0c
 126#define CLOCK_DIV			0x30
 127#define CLOCK_DIV1			0x00
 128#define CLOCK_DIV2			0x10
 129#define CLOCK_DIV4			0x20
 130#define CLOCK_STROBE			0x40
 131/*  ?					0x80 */
 132/* CLOCK_CNTL register constants GX LAYOUT */
 133#define CLOCK_BIT			0x04	/* For ICS2595 */
 134#define CLOCK_PULSE			0x08	/* For ICS2595 */
 135/*#define CLOCK_STROBE			0x40 dito as CT */
 136#define CLOCK_DATA			0x80
 137
 138/* For internal PLL(CT) start */
 139#define CLOCK_CNTL_ADDR			CLOCK_CNTL + 1
 140#define PLL_WR_EN			0x02
 141#define PLL_ADDR			0xfc
 142#define CLOCK_CNTL_DATA			CLOCK_CNTL + 2
 143#define PLL_DATA			0xff
 144/* For internal PLL(CT) end */
 145
 146#define CLOCK_SEL_CNTL		0x0090	/* Dword offset 0_24 */
 147
 148/* Configuration */
 149#define CNFG_STAT1		0x0094	/* Dword offset 0_25 */
 150#define CNFG_STAT2		0x0098	/* Dword offset 0_26 */
 151
 152/* Bus Control */
 153#define BUS_CNTL		0x00A0	/* Dword offset 0_28 */
 154
 155#define LCD_INDEX		0x00A4	/* Dword offset 0_29 */
 156#define LCD_DATA		0x00A8	/* Dword offset 0_2A */
 157
 158#define HFB_PITCH_ADDR_LG	0x00A8	/* Dword offset 0_2A (LG) */
 159
 160/* Memory Control */
 161#define EXT_MEM_CNTL		0x00AC	/* Dword offset 0_2B */
 162#define MEM_CNTL		0x00B0	/* Dword offset 0_2C */
 163#define MEM_VGA_WP_SEL		0x00B4	/* Dword offset 0_2D */
 164#define MEM_VGA_RP_SEL		0x00B8	/* Dword offset 0_2E */
 165
 166#define I2C_CNTL_1		0x00BC	/* Dword offset 0_2F */
 167
 168#define LT_GIO_LG		0x00BC	/* Dword offset 0_2F (LG) */
 169
 170/* DAC Control */
 171#define DAC_REGS		0x00C0	/* Dword offset 0_30 */
 172#define DAC_W_INDEX		0x00C0	/* Dword offset 0_30 */
 173#define DAC_DATA		0x00C1	/* Dword offset 0_30 */
 174#define DAC_MASK		0x00C2	/* Dword offset 0_30 */
 175#define DAC_R_INDEX		0x00C3	/* Dword offset 0_30 */
 176#define DAC_CNTL		0x00C4	/* Dword offset 0_31 */
 177
 178#define EXT_DAC_REGS		0x00C8	/* Dword offset 0_32 */
 179
 180#define HORZ_STRETCHING_LG	0x00C8	/* Dword offset 0_32 (LG) */
 181#define VERT_STRETCHING_LG	0x00CC	/* Dword offset 0_33 (LG) */
 182
 183/* Test and Debug */
 184#define GEN_TEST_CNTL		0x00D0	/* Dword offset 0_34 */
 185
 186/* Custom Macros */
 187#define CUSTOM_MACRO_CNTL	0x00D4	/* Dword offset 0_35 */
 188
 189#define LCD_GEN_CNTL_LG		0x00D4	/* Dword offset 0_35 (LG) */
 190#define POWER_MANAGEMENT_LG	0x00D8	/* Dword offset 0_36 (LG) */
 191
 192/* Configuration */
 193#define CNFG_CNTL		0x00DC	/* Dword offset 0_37 (CT, ET, VT) */
 194#define CNFG_CHIP_ID		0x00E0	/* Dword offset 0_38 */
 195#define CNFG_STAT0		0x00E4	/* Dword offset 0_39 */
 196
 197/* Test and Debug */
 198#define CRC_SIG			0x00E8	/* Dword offset 0_3A */
 199#define CRC2_SIG		0x00E8	/* Dword offset 0_3A */
 200
 201
 202/* GUI MEMORY MAPPED Registers */
 203
 204/* Draw Engine Destination Trajectory */
 205#define DST_OFF_PITCH		0x0100	/* Dword offset 0_40 */
 206#define DST_X			0x0104	/* Dword offset 0_41 */
 207#define DST_Y			0x0108	/* Dword offset 0_42 */
 208#define DST_Y_X			0x010C	/* Dword offset 0_43 */
 209#define DST_WIDTH		0x0110	/* Dword offset 0_44 */
 210#define DST_HEIGHT		0x0114	/* Dword offset 0_45 */
 211#define DST_HEIGHT_WIDTH	0x0118	/* Dword offset 0_46 */
 212#define DST_X_WIDTH		0x011C	/* Dword offset 0_47 */
 213#define DST_BRES_LNTH		0x0120	/* Dword offset 0_48 */
 214#define DST_BRES_ERR		0x0124	/* Dword offset 0_49 */
 215#define DST_BRES_INC		0x0128	/* Dword offset 0_4A */
 216#define DST_BRES_DEC		0x012C	/* Dword offset 0_4B */
 217#define DST_CNTL		0x0130	/* Dword offset 0_4C */
 218#define DST_Y_X__ALIAS__	0x0134	/* Dword offset 0_4D */
 219#define TRAIL_BRES_ERR		0x0138	/* Dword offset 0_4E */
 220#define TRAIL_BRES_INC		0x013C	/* Dword offset 0_4F */
 221#define TRAIL_BRES_DEC		0x0140	/* Dword offset 0_50 */
 222#define LEAD_BRES_LNTH		0x0144	/* Dword offset 0_51 */
 223#define Z_OFF_PITCH		0x0148	/* Dword offset 0_52 */
 224#define Z_CNTL			0x014C	/* Dword offset 0_53 */
 225#define ALPHA_TST_CNTL		0x0150	/* Dword offset 0_54 */
 226#define SECONDARY_STW_EXP	0x0158	/* Dword offset 0_56 */
 227#define SECONDARY_S_X_INC	0x015C	/* Dword offset 0_57 */
 228#define SECONDARY_S_Y_INC	0x0160	/* Dword offset 0_58 */
 229#define SECONDARY_S_START	0x0164	/* Dword offset 0_59 */
 230#define SECONDARY_W_X_INC	0x0168	/* Dword offset 0_5A */
 231#define SECONDARY_W_Y_INC	0x016C	/* Dword offset 0_5B */
 232#define SECONDARY_W_START	0x0170	/* Dword offset 0_5C */
 233#define SECONDARY_T_X_INC	0x0174	/* Dword offset 0_5D */
 234#define SECONDARY_T_Y_INC	0x0178	/* Dword offset 0_5E */
 235#define SECONDARY_T_START	0x017C	/* Dword offset 0_5F */
 236
 237/* Draw Engine Source Trajectory */
 238#define SRC_OFF_PITCH		0x0180	/* Dword offset 0_60 */
 239#define SRC_X			0x0184	/* Dword offset 0_61 */
 240#define SRC_Y			0x0188	/* Dword offset 0_62 */
 241#define SRC_Y_X			0x018C	/* Dword offset 0_63 */
 242#define SRC_WIDTH1		0x0190	/* Dword offset 0_64 */
 243#define SRC_HEIGHT1		0x0194	/* Dword offset 0_65 */
 244#define SRC_HEIGHT1_WIDTH1	0x0198	/* Dword offset 0_66 */
 245#define SRC_X_START		0x019C	/* Dword offset 0_67 */
 246#define SRC_Y_START		0x01A0	/* Dword offset 0_68 */
 247#define SRC_Y_X_START		0x01A4	/* Dword offset 0_69 */
 248#define SRC_WIDTH2		0x01A8	/* Dword offset 0_6A */
 249#define SRC_HEIGHT2		0x01AC	/* Dword offset 0_6B */
 250#define SRC_HEIGHT2_WIDTH2	0x01B0	/* Dword offset 0_6C */
 251#define SRC_CNTL		0x01B4	/* Dword offset 0_6D */
 252
 253#define SCALE_OFF		0x01C0	/* Dword offset 0_70 */
 254#define SECONDARY_SCALE_OFF	0x01C4	/* Dword offset 0_71 */
 255
 256#define TEX_0_OFF		0x01C0	/* Dword offset 0_70 */
 257#define TEX_1_OFF		0x01C4	/* Dword offset 0_71 */
 258#define TEX_2_OFF		0x01C8	/* Dword offset 0_72 */
 259#define TEX_3_OFF		0x01CC	/* Dword offset 0_73 */
 260#define TEX_4_OFF		0x01D0	/* Dword offset 0_74 */
 261#define TEX_5_OFF		0x01D4	/* Dword offset 0_75 */
 262#define TEX_6_OFF		0x01D8	/* Dword offset 0_76 */
 263#define TEX_7_OFF		0x01DC	/* Dword offset 0_77 */
 264
 265#define SCALE_WIDTH		0x01DC	/* Dword offset 0_77 */
 266#define SCALE_HEIGHT		0x01E0	/* Dword offset 0_78 */
 267
 268#define TEX_8_OFF		0x01E0	/* Dword offset 0_78 */
 269#define TEX_9_OFF		0x01E4	/* Dword offset 0_79 */
 270#define TEX_10_OFF		0x01E8	/* Dword offset 0_7A */
 271#define S_Y_INC			0x01EC	/* Dword offset 0_7B */
 272
 273#define SCALE_PITCH		0x01EC	/* Dword offset 0_7B */
 274#define SCALE_X_INC		0x01F0	/* Dword offset 0_7C */
 275
 276#define RED_X_INC		0x01F0	/* Dword offset 0_7C */
 277#define GREEN_X_INC		0x01F4	/* Dword offset 0_7D */
 278
 279#define SCALE_Y_INC		0x01F4	/* Dword offset 0_7D */
 280#define SCALE_VACC		0x01F8	/* Dword offset 0_7E */
 281#define SCALE_3D_CNTL		0x01FC	/* Dword offset 0_7F */
 282
 283/* Host Data */
 284#define HOST_DATA0		0x0200	/* Dword offset 0_80 */
 285#define HOST_DATA1		0x0204	/* Dword offset 0_81 */
 286#define HOST_DATA2		0x0208	/* Dword offset 0_82 */
 287#define HOST_DATA3		0x020C	/* Dword offset 0_83 */
 288#define HOST_DATA4		0x0210	/* Dword offset 0_84 */
 289#define HOST_DATA5		0x0214	/* Dword offset 0_85 */
 290#define HOST_DATA6		0x0218	/* Dword offset 0_86 */
 291#define HOST_DATA7		0x021C	/* Dword offset 0_87 */
 292#define HOST_DATA8		0x0220	/* Dword offset 0_88 */
 293#define HOST_DATA9		0x0224	/* Dword offset 0_89 */
 294#define HOST_DATAA		0x0228	/* Dword offset 0_8A */
 295#define HOST_DATAB		0x022C	/* Dword offset 0_8B */
 296#define HOST_DATAC		0x0230	/* Dword offset 0_8C */
 297#define HOST_DATAD		0x0234	/* Dword offset 0_8D */
 298#define HOST_DATAE		0x0238	/* Dword offset 0_8E */
 299#define HOST_DATAF		0x023C	/* Dword offset 0_8F */
 300#define HOST_CNTL		0x0240	/* Dword offset 0_90 */
 301
 302/* GUI Bus Mastering */
 303#define BM_HOSTDATA		0x0244	/* Dword offset 0_91 */
 304#define BM_ADDR			0x0248	/* Dword offset 0_92 */
 305#define BM_DATA			0x0248	/* Dword offset 0_92 */
 306#define BM_GUI_TABLE_CMD	0x024C	/* Dword offset 0_93 */
 307
 308/* Pattern */
 309#define PAT_REG0		0x0280	/* Dword offset 0_A0 */
 310#define PAT_REG1		0x0284	/* Dword offset 0_A1 */
 311#define PAT_CNTL		0x0288	/* Dword offset 0_A2 */
 312
 313/* Scissors */
 314#define SC_LEFT			0x02A0	/* Dword offset 0_A8 */
 315#define SC_RIGHT		0x02A4	/* Dword offset 0_A9 */
 316#define SC_LEFT_RIGHT		0x02A8	/* Dword offset 0_AA */
 317#define SC_TOP			0x02AC	/* Dword offset 0_AB */
 318#define SC_BOTTOM		0x02B0	/* Dword offset 0_AC */
 319#define SC_TOP_BOTTOM		0x02B4	/* Dword offset 0_AD */
 320
 321/* Data Path */
 322#define USR1_DST_OFF_PITCH	0x02B8	/* Dword offset 0_AE */
 323#define USR2_DST_OFF_PITCH	0x02BC	/* Dword offset 0_AF */
 324#define DP_BKGD_CLR		0x02C0	/* Dword offset 0_B0 */
 325#define DP_FOG_CLR		0x02C4	/* Dword offset 0_B1 */
 326#define DP_FRGD_CLR		0x02C4	/* Dword offset 0_B1 */
 327#define DP_WRITE_MASK		0x02C8	/* Dword offset 0_B2 */
 328#define DP_CHAIN_MASK		0x02CC	/* Dword offset 0_B3 */
 329#define DP_PIX_WIDTH		0x02D0	/* Dword offset 0_B4 */
 330#define DP_MIX			0x02D4	/* Dword offset 0_B5 */
 331#define DP_SRC			0x02D8	/* Dword offset 0_B6 */
 332#define DP_FRGD_CLR_MIX		0x02DC	/* Dword offset 0_B7 */
 333#define DP_FRGD_BKGD_CLR	0x02E0	/* Dword offset 0_B8 */
 334
 335/* Draw Engine Destination Trajectory */
 336#define DST_X_Y			0x02E8	/* Dword offset 0_BA */
 337#define DST_WIDTH_HEIGHT	0x02EC	/* Dword offset 0_BB */
 338
 339/* Data Path */
 340#define USR_DST_PICTH		0x02F0	/* Dword offset 0_BC */
 341#define DP_SET_GUI_ENGINE2	0x02F8	/* Dword offset 0_BE */
 342#define DP_SET_GUI_ENGINE	0x02FC	/* Dword offset 0_BF */
 343
 344/* Color Compare */
 345#define CLR_CMP_CLR		0x0300	/* Dword offset 0_C0 */
 346#define CLR_CMP_MASK		0x0304	/* Dword offset 0_C1 */
 347#define CLR_CMP_CNTL		0x0308	/* Dword offset 0_C2 */
 348
 349/* Command FIFO */
 350#define FIFO_STAT		0x0310	/* Dword offset 0_C4 */
 351
 352#define CONTEXT_MASK		0x0320	/* Dword offset 0_C8 */
 353#define CONTEXT_LOAD_CNTL	0x032C	/* Dword offset 0_CB */
 354
 355/* Engine Control */
 356#define GUI_TRAJ_CNTL		0x0330	/* Dword offset 0_CC */
 357
 358/* Engine Status/FIFO */
 359#define GUI_STAT		0x0338	/* Dword offset 0_CE */
 360
 361#define TEX_PALETTE_INDEX	0x0340	/* Dword offset 0_D0 */
 362#define STW_EXP			0x0344	/* Dword offset 0_D1 */
 363#define LOG_MAX_INC		0x0348	/* Dword offset 0_D2 */
 364#define S_X_INC			0x034C	/* Dword offset 0_D3 */
 365#define S_Y_INC__ALIAS__	0x0350	/* Dword offset 0_D4 */
 366
 367#define SCALE_PITCH__ALIAS__	0x0350	/* Dword offset 0_D4 */
 368
 369#define S_START			0x0354	/* Dword offset 0_D5 */
 370#define W_X_INC			0x0358	/* Dword offset 0_D6 */
 371#define W_Y_INC			0x035C	/* Dword offset 0_D7 */
 372#define W_START			0x0360	/* Dword offset 0_D8 */
 373#define T_X_INC			0x0364	/* Dword offset 0_D9 */
 374#define T_Y_INC			0x0368	/* Dword offset 0_DA */
 375
 376#define SECONDARY_SCALE_PITCH	0x0368	/* Dword offset 0_DA */
 377
 378#define T_START			0x036C	/* Dword offset 0_DB */
 379#define TEX_SIZE_PITCH		0x0370	/* Dword offset 0_DC */
 380#define TEX_CNTL		0x0374	/* Dword offset 0_DD */
 381#define SECONDARY_TEX_OFFSET	0x0378	/* Dword offset 0_DE */
 382#define TEX_PALETTE		0x037C	/* Dword offset 0_DF */
 383
 384#define SCALE_PITCH_BOTH	0x0380	/* Dword offset 0_E0 */
 385#define SECONDARY_SCALE_OFF_ACC	0x0384	/* Dword offset 0_E1 */
 386#define SCALE_OFF_ACC		0x0388	/* Dword offset 0_E2 */
 387#define SCALE_DST_Y_X		0x038C	/* Dword offset 0_E3 */
 388
 389/* Draw Engine Destination Trajectory */
 390#define COMPOSITE_SHADOW_ID	0x0398	/* Dword offset 0_E6 */
 391
 392#define SECONDARY_SCALE_X_INC	0x039C	/* Dword offset 0_E7 */
 393
 394#define SPECULAR_RED_X_INC	0x039C	/* Dword offset 0_E7 */
 395#define SPECULAR_RED_Y_INC	0x03A0	/* Dword offset 0_E8 */
 396#define SPECULAR_RED_START	0x03A4	/* Dword offset 0_E9 */
 397
 398#define SECONDARY_SCALE_HACC	0x03A4	/* Dword offset 0_E9 */
 399
 400#define SPECULAR_GREEN_X_INC	0x03A8	/* Dword offset 0_EA */
 401#define SPECULAR_GREEN_Y_INC	0x03AC	/* Dword offset 0_EB */
 402#define SPECULAR_GREEN_START	0x03B0	/* Dword offset 0_EC */
 403#define SPECULAR_BLUE_X_INC	0x03B4	/* Dword offset 0_ED */
 404#define SPECULAR_BLUE_Y_INC	0x03B8	/* Dword offset 0_EE */
 405#define SPECULAR_BLUE_START	0x03BC	/* Dword offset 0_EF */
 406
 407#define SCALE_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
 408
 409#define RED_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
 410#define RED_Y_INC		0x03C4	/* Dword offset 0_F1 */
 411#define RED_START		0x03C8	/* Dword offset 0_F2 */
 412
 413#define SCALE_HACC		0x03C8	/* Dword offset 0_F2 */
 414#define SCALE_Y_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
 415
 416#define GREEN_X_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
 417#define GREEN_Y_INC		0x03D0	/* Dword offset 0_F4 */
 418
 419#define SECONDARY_SCALE_Y_INC	0x03D0	/* Dword offset 0_F4 */
 420#define SECONDARY_SCALE_VACC	0x03D4	/* Dword offset 0_F5 */
 421
 422#define GREEN_START		0x03D4	/* Dword offset 0_F5 */
 423#define BLUE_X_INC		0x03D8	/* Dword offset 0_F6 */
 424#define BLUE_Y_INC		0x03DC	/* Dword offset 0_F7 */
 425#define BLUE_START		0x03E0	/* Dword offset 0_F8 */
 426#define Z_X_INC			0x03E4	/* Dword offset 0_F9 */
 427#define Z_Y_INC			0x03E8	/* Dword offset 0_FA */
 428#define Z_START			0x03EC	/* Dword offset 0_FB */
 429#define ALPHA_X_INC		0x03F0	/* Dword offset 0_FC */
 430#define FOG_X_INC		0x03F0	/* Dword offset 0_FC */
 431#define ALPHA_Y_INC		0x03F4	/* Dword offset 0_FD */
 432#define FOG_Y_INC		0x03F4	/* Dword offset 0_FD */
 433#define ALPHA_START		0x03F8	/* Dword offset 0_FE */
 434#define FOG_START		0x03F8	/* Dword offset 0_FE */
 435
 436#define OVERLAY_Y_X_START		0x0400	/* Dword offset 1_00 */
 437#define OVERLAY_Y_X_END			0x0404	/* Dword offset 1_01 */
 438#define OVERLAY_VIDEO_KEY_CLR		0x0408	/* Dword offset 1_02 */
 439#define OVERLAY_VIDEO_KEY_MSK		0x040C	/* Dword offset 1_03 */
 440#define OVERLAY_GRAPHICS_KEY_CLR	0x0410	/* Dword offset 1_04 */
 441#define OVERLAY_GRAPHICS_KEY_MSK	0x0414	/* Dword offset 1_05 */
 442#define OVERLAY_KEY_CNTL		0x0418	/* Dword offset 1_06 */
 443
 444#define OVERLAY_SCALE_INC	0x0420	/* Dword offset 1_08 */
 445#define OVERLAY_SCALE_CNTL	0x0424	/* Dword offset 1_09 */
 446#define SCALER_HEIGHT_WIDTH	0x0428	/* Dword offset 1_0A */
 447#define SCALER_TEST		0x042C	/* Dword offset 1_0B */
 448#define SCALER_BUF0_OFFSET	0x0434	/* Dword offset 1_0D */
 449#define SCALER_BUF1_OFFSET	0x0438	/* Dword offset 1_0E */
 450#define SCALE_BUF_PITCH		0x043C	/* Dword offset 1_0F */
 451
 452#define CAPTURE_START_END	0x0440	/* Dword offset 1_10 */
 453#define CAPTURE_X_WIDTH		0x0444	/* Dword offset 1_11 */
 454#define VIDEO_FORMAT		0x0448	/* Dword offset 1_12 */
 455#define VBI_START_END		0x044C	/* Dword offset 1_13 */
 456#define CAPTURE_CONFIG		0x0450	/* Dword offset 1_14 */
 457#define TRIG_CNTL		0x0454	/* Dword offset 1_15 */
 458
 459#define OVERLAY_EXCLUSIVE_HORZ	0x0458	/* Dword offset 1_16 */
 460#define OVERLAY_EXCLUSIVE_VERT	0x045C	/* Dword offset 1_17 */
 461
 462#define VAL_WIDTH		0x0460	/* Dword offset 1_18 */
 463#define CAPTURE_DEBUG		0x0464	/* Dword offset 1_19 */
 464#define VIDEO_SYNC_TEST		0x0468	/* Dword offset 1_1A */
 465
 466/* GenLocking */
 467#define SNAPSHOT_VH_COUNTS	0x0470	/* Dword offset 1_1C */
 468#define SNAPSHOT_F_COUNT	0x0474	/* Dword offset 1_1D */
 469#define N_VIF_COUNT		0x0478	/* Dword offset 1_1E */
 470#define SNAPSHOT_VIF_COUNT	0x047C	/* Dword offset 1_1F */
 471
 472#define CAPTURE_BUF0_OFFSET	0x0480	/* Dword offset 1_20 */
 473#define CAPTURE_BUF1_OFFSET	0x0484	/* Dword offset 1_21 */
 474#define CAPTURE_BUF_PITCH	0x0488	/* Dword offset 1_22 */
 475
 476/* GenLocking */
 477#define SNAPSHOT2_VH_COUNTS	0x04B0	/* Dword offset 1_2C */
 478#define SNAPSHOT2_F_COUNT	0x04B4	/* Dword offset 1_2D */
 479#define N_VIF2_COUNT		0x04B8	/* Dword offset 1_2E */
 480#define SNAPSHOT2_VIF_COUNT	0x04BC	/* Dword offset 1_2F */
 481
 482#define MPP_CONFIG		0x04C0	/* Dword offset 1_30 */
 483#define MPP_STROBE_SEQ		0x04C4	/* Dword offset 1_31 */
 484#define MPP_ADDR		0x04C8	/* Dword offset 1_32 */
 485#define MPP_DATA		0x04CC	/* Dword offset 1_33 */
 486#define TVO_CNTL		0x0500	/* Dword offset 1_40 */
 487
 488/* Test and Debug */
 489#define CRT_HORZ_VERT_LOAD	0x0544	/* Dword offset 1_51 */
 490
 491/* AGP */
 492#define AGP_BASE		0x0548	/* Dword offset 1_52 */
 493#define AGP_CNTL		0x054C	/* Dword offset 1_53 */
 494
 495#define SCALER_COLOUR_CNTL	0x0550	/* Dword offset 1_54 */
 496#define SCALER_H_COEFF0		0x0554	/* Dword offset 1_55 */
 497#define SCALER_H_COEFF1		0x0558	/* Dword offset 1_56 */
 498#define SCALER_H_COEFF2		0x055C	/* Dword offset 1_57 */
 499#define SCALER_H_COEFF3		0x0560	/* Dword offset 1_58 */
 500#define SCALER_H_COEFF4		0x0564	/* Dword offset 1_59 */
 501
 502/* Command FIFO */
 503#define GUI_CMDFIFO_DEBUG	0x0570	/* Dword offset 1_5C */
 504#define GUI_CMDFIFO_DATA	0x0574	/* Dword offset 1_5D */
 505#define GUI_CNTL		0x0578	/* Dword offset 1_5E */
 506
 507/* Bus Mastering */
 508#define BM_FRAME_BUF_OFFSET	0x0580	/* Dword offset 1_60 */
 509#define BM_SYSTEM_MEM_ADDR	0x0584	/* Dword offset 1_61 */
 510#define BM_COMMAND		0x0588	/* Dword offset 1_62 */
 511#define BM_STATUS		0x058C	/* Dword offset 1_63 */
 512#define BM_GUI_TABLE		0x05B8	/* Dword offset 1_6E */
 513#define BM_SYSTEM_TABLE		0x05BC	/* Dword offset 1_6F */
 514
 515#define SCALER_BUF0_OFFSET_U	0x05D4	/* Dword offset 1_75 */
 516#define SCALER_BUF0_OFFSET_V	0x05D8	/* Dword offset 1_76 */
 517#define SCALER_BUF1_OFFSET_U	0x05DC	/* Dword offset 1_77 */
 518#define SCALER_BUF1_OFFSET_V	0x05E0	/* Dword offset 1_78 */
 519
 520/* Setup Engine */
 521#define VERTEX_1_S		0x0640	/* Dword offset 1_90 */
 522#define VERTEX_1_T		0x0644	/* Dword offset 1_91 */
 523#define VERTEX_1_W		0x0648	/* Dword offset 1_92 */
 524#define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_93 */
 525#define VERTEX_1_Z		0x0650	/* Dword offset 1_94 */
 526#define VERTEX_1_ARGB		0x0654	/* Dword offset 1_95 */
 527#define VERTEX_1_X_Y		0x0658	/* Dword offset 1_96 */
 528#define ONE_OVER_AREA		0x065C	/* Dword offset 1_97 */
 529#define VERTEX_2_S		0x0660	/* Dword offset 1_98 */
 530#define VERTEX_2_T		0x0664	/* Dword offset 1_99 */
 531#define VERTEX_2_W		0x0668	/* Dword offset 1_9A */
 532#define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_9B */
 533#define VERTEX_2_Z		0x0670	/* Dword offset 1_9C */
 534#define VERTEX_2_ARGB		0x0674	/* Dword offset 1_9D */
 535#define VERTEX_2_X_Y		0x0678	/* Dword offset 1_9E */
 536#define ONE_OVER_AREA		0x065C	/* Dword offset 1_9F */
 537#define VERTEX_3_S		0x0680	/* Dword offset 1_A0 */
 538#define VERTEX_3_T		0x0684	/* Dword offset 1_A1 */
 539#define VERTEX_3_W		0x0688	/* Dword offset 1_A2 */
 540#define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_A3 */
 541#define VERTEX_3_Z		0x0690	/* Dword offset 1_A4 */
 542#define VERTEX_3_ARGB		0x0694	/* Dword offset 1_A5 */
 543#define VERTEX_3_X_Y		0x0698	/* Dword offset 1_A6 */
 544#define ONE_OVER_AREA		0x065C	/* Dword offset 1_A7 */
 545#define VERTEX_1_S		0x0640	/* Dword offset 1_AB */
 546#define VERTEX_1_T		0x0644	/* Dword offset 1_AC */
 547#define VERTEX_1_W		0x0648	/* Dword offset 1_AD */
 548#define VERTEX_2_S		0x0660	/* Dword offset 1_AE */
 549#define VERTEX_2_T		0x0664	/* Dword offset 1_AF */
 550#define VERTEX_2_W		0x0668	/* Dword offset 1_B0 */
 551#define VERTEX_3_SECONDARY_S	0x06C0	/* Dword offset 1_B0 */
 552#define VERTEX_3_S		0x0680	/* Dword offset 1_B1 */
 553#define VERTEX_3_SECONDARY_T	0x06C4	/* Dword offset 1_B1 */
 554#define VERTEX_3_T		0x0684	/* Dword offset 1_B2 */
 555#define VERTEX_3_SECONDARY_W	0x06C8	/* Dword offset 1_B2 */
 556#define VERTEX_3_W		0x0688	/* Dword offset 1_B3 */
 557#define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_B4 */
 558#define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_B5 */
 559#define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_B6 */
 560#define VERTEX_1_Z		0x0650	/* Dword offset 1_B7 */
 561#define VERTEX_2_Z		0x0670	/* Dword offset 1_B8 */
 562#define VERTEX_3_Z		0x0690	/* Dword offset 1_B9 */
 563#define VERTEX_1_ARGB		0x0654	/* Dword offset 1_BA */
 564#define VERTEX_2_ARGB		0x0674	/* Dword offset 1_BB */
 565#define VERTEX_3_ARGB		0x0694	/* Dword offset 1_BC */
 566#define VERTEX_1_X_Y		0x0658	/* Dword offset 1_BD */
 567#define VERTEX_2_X_Y		0x0678	/* Dword offset 1_BE */
 568#define VERTEX_3_X_Y		0x0698	/* Dword offset 1_BF */
 569#define ONE_OVER_AREA_UC	0x0700	/* Dword offset 1_C0 */
 570#define SETUP_CNTL		0x0704	/* Dword offset 1_C1 */
 571#define VERTEX_1_SECONDARY_S	0x0728	/* Dword offset 1_CA */
 572#define VERTEX_1_SECONDARY_T	0x072C	/* Dword offset 1_CB */
 573#define VERTEX_1_SECONDARY_W	0x0730	/* Dword offset 1_CC */
 574#define VERTEX_2_SECONDARY_S	0x0734	/* Dword offset 1_CD */
 575#define VERTEX_2_SECONDARY_T	0x0738	/* Dword offset 1_CE */
 576#define VERTEX_2_SECONDARY_W	0x073C	/* Dword offset 1_CF */
 577
 578
 579#define GTC_3D_RESET_DELAY	3	/* 3D engine reset delay in ms */
 580
 581/* CRTC control values (mostly CRTC_GEN_CNTL) */
 582
 583#define CRTC_H_SYNC_NEG		0x00200000
 584#define CRTC_V_SYNC_NEG		0x00200000
 585
 586#define CRTC_DBL_SCAN_EN	0x00000001
 587#define CRTC_INTERLACE_EN	0x00000002
 588#define CRTC_HSYNC_DIS		0x00000004
 589#define CRTC_VSYNC_DIS		0x00000008
 590#define CRTC_CSYNC_EN		0x00000010
 591#define CRTC_PIX_BY_2_EN	0x00000020	/* unused on RAGE */
 592#define CRTC_DISPLAY_DIS	0x00000040
 593#define CRTC_VGA_XOVERSCAN	0x00000080
 594
 595#define CRTC_PIX_WIDTH_MASK	0x00000700
 596#define CRTC_PIX_WIDTH_4BPP	0x00000100
 597#define CRTC_PIX_WIDTH_8BPP	0x00000200
 598#define CRTC_PIX_WIDTH_15BPP	0x00000300
 599#define CRTC_PIX_WIDTH_16BPP	0x00000400
 600#define CRTC_PIX_WIDTH_24BPP	0x00000500
 601#define CRTC_PIX_WIDTH_32BPP	0x00000600
 602
 603#define CRTC_BYTE_PIX_ORDER	0x00000800
 604#define CRTC_PIX_ORDER_MSN_LSN	0x00000000
 605#define CRTC_PIX_ORDER_LSN_MSN	0x00000800
 606
 607#define CRTC_VSYNC_INT_EN	0x00001000ul	/* XC/XL */
 608#define CRTC_VSYNC_INT		0x00002000ul	/* XC/XL */
 609#define CRTC_FIFO_OVERFILL	0x0000c000ul	/* VT/GT */
 610#define CRTC2_VSYNC_INT_EN	0x00004000ul	/* XC/XL */
 611#define CRTC2_VSYNC_INT		0x00008000ul	/* XC/XL */
 612
 613#define CRTC_FIFO_LWM		0x000f0000
 614#define CRTC_HVSYNC_IO_DRIVE	0x00010000	/* XC/XL */
 615#define CRTC2_PIX_WIDTH		0x000e0000	/* LTPro */
 616
 617#define CRTC_VGA_128KAP_PAGING	0x00100000
 618#define CRTC_VFC_SYNC_TRISTATE	0x00200000	/* VTB/GTB/LT */
 619#define CRTC2_EN		0x00200000	/* LTPro */
 620#define CRTC_LOCK_REGS		0x00400000
 621#define CRTC_SYNC_TRISTATE	0x00800000
 622
 623#define CRTC_EXT_DISP_EN	0x01000000
 624#define CRTC_EN			0x02000000
 625#define CRTC_DISP_REQ_EN	0x04000000
 626#define CRTC_VGA_LINEAR		0x08000000
 627#define CRTC_VSYNC_FALL_EDGE	0x10000000
 628#define CRTC_VGA_TEXT_132	0x20000000
 629#define CRTC_CNT_EN		0x40000000
 630#define CRTC_CUR_B_TEST		0x80000000
 631
 632#define CRTC_CRNT_VLINE		0x07f00000
 633
 634#define CRTC_PRESERVED_MASK	0x0001f000
 635
 636#define CRTC_VBLANK		0x00000001
 637#define CRTC_VBLANK_INT_EN	0x00000002
 638#define CRTC_VBLANK_INT		0x00000004
 639#define CRTC_VBLANK_INT_AK	CRTC_VBLANK_INT
 640#define CRTC_VLINE_INT_EN	0x00000008
 641#define CRTC_VLINE_INT		0x00000010
 642#define CRTC_VLINE_INT_AK	CRTC_VLINE_INT
 643#define CRTC_VLINE_SYNC		0x00000020
 644#define CRTC_FRAME		0x00000040
 645#define SNAPSHOT_INT_EN		0x00000080
 646#define SNAPSHOT_INT		0x00000100
 647#define SNAPSHOT_INT_AK		SNAPSHOT_INT
 648#define I2C_INT_EN		0x00000200
 649#define I2C_INT			0x00000400
 650#define I2C_INT_AK		I2C_INT
 651#define CRTC2_VBLANK		0x00000800
 652#define CRTC2_VBLANK_INT_EN	0x00001000
 653#define CRTC2_VBLANK_INT	0x00002000
 654#define CRTC2_VBLANK_INT_AK	CRTC2_VBLANK_INT
 655#define CRTC2_VLINE_INT_EN	0x00004000
 656#define CRTC2_VLINE_INT		0x00008000
 657#define CRTC2_VLINE_INT_AK	CRTC2_VLINE_INT
 658#define CAPBUF0_INT_EN		0x00010000
 659#define CAPBUF0_INT		0x00020000
 660#define CAPBUF0_INT_AK		CAPBUF0_INT
 661#define CAPBUF1_INT_EN		0x00040000
 662#define CAPBUF1_INT		0x00080000
 663#define CAPBUF1_INT_AK		CAPBUF1_INT
 664#define OVERLAY_EOF_INT_EN	0x00100000
 665#define OVERLAY_EOF_INT		0x00200000
 666#define OVERLAY_EOF_INT_AK	OVERLAY_EOF_INT
 667#define ONESHOT_CAP_INT_EN	0x00400000
 668#define ONESHOT_CAP_INT		0x00800000
 669#define ONESHOT_CAP_INT_AK	ONESHOT_CAP_INT
 670#define BUSMASTER_EOL_INT_EN	0x01000000
 671#define BUSMASTER_EOL_INT	0x02000000
 672#define BUSMASTER_EOL_INT_AK	BUSMASTER_EOL_INT
 673#define GP_INT_EN		0x04000000
 674#define GP_INT			0x08000000
 675#define GP_INT_AK		GP_INT
 676#define CRTC2_VLINE_SYNC	0x10000000
 677#define SNAPSHOT2_INT_EN	0x20000000
 678#define SNAPSHOT2_INT		0x40000000
 679#define SNAPSHOT2_INT_AK	SNAPSHOT2_INT
 680#define VBLANK_BIT2_INT		0x80000000
 681#define VBLANK_BIT2_INT_AK	VBLANK_BIT2_INT
 682
 683#define CRTC_INT_EN_MASK	(CRTC_VBLANK_INT_EN |	\
 684				 CRTC_VLINE_INT_EN |	\
 685				 SNAPSHOT_INT_EN |	\
 686				 I2C_INT_EN |		\
 687				 CRTC2_VBLANK_INT_EN |	\
 688				 CRTC2_VLINE_INT_EN |	\
 689				 CAPBUF0_INT_EN |	\
 690				 CAPBUF1_INT_EN |	\
 691				 OVERLAY_EOF_INT_EN |	\
 692				 ONESHOT_CAP_INT_EN |	\
 693				 BUSMASTER_EOL_INT_EN |	\
 694				 GP_INT_EN |		\
 695				 SNAPSHOT2_INT_EN)
 696
 697/* DAC control values */
 698
 699#define DAC_EXT_SEL_RS2		0x01
 700#define DAC_EXT_SEL_RS3		0x02
 701#define DAC_8BIT_EN		0x00000100
 702#define DAC_PIX_DLY_MASK	0x00000600
 703#define DAC_PIX_DLY_0NS		0x00000000
 704#define DAC_PIX_DLY_2NS		0x00000200
 705#define DAC_PIX_DLY_4NS		0x00000400
 706#define DAC_BLANK_ADJ_MASK	0x00001800
 707#define DAC_BLANK_ADJ_0		0x00000000
 708#define DAC_BLANK_ADJ_1		0x00000800
 709#define DAC_BLANK_ADJ_2		0x00001000
 710
 711/* DAC control values (my source XL/XC Register reference) */
 712#define DAC_OUTPUT_MASK         0x00000001  /* 0 - PAL, 1 - NTSC */
 713#define DAC_MISTERY_BIT         0x00000002  /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
 714#define DAC_BLANKING            0x00000004
 715#define DAC_CMP_DISABLE         0x00000008
 716#define DAC1_CLK_SEL            0x00000010
 717#define PALETTE_ACCESS_CNTL     0x00000020
 718#define PALETTE2_SNOOP_EN       0x00000040
 719#define DAC_CMP_OUTPUT          0x00000080 /* read only */
 720/* #define DAC_8BIT_EN is ok */
 721#define CRT_SENSE               0x00000800 /* read only */
 722#define CRT_DETECTION_ON        0x00001000
 723#define DAC_VGA_ADR_EN          0x00002000
 724#define DAC_FEA_CON_EN          0x00004000
 725#define DAC_PDWN                0x00008000
 726#define DAC_TYPE_MASK           0x00070000 /* read only */
 727
 728
 729
 730/* Mix control values */
 731
 732#define MIX_NOT_DST		0x0000
 733#define MIX_0			0x0001
 734#define MIX_1			0x0002
 735#define MIX_DST			0x0003
 736#define MIX_NOT_SRC		0x0004
 737#define MIX_XOR			0x0005
 738#define MIX_XNOR		0x0006
 739#define MIX_SRC			0x0007
 740#define MIX_NAND		0x0008
 741#define MIX_NOT_SRC_OR_DST	0x0009
 742#define MIX_SRC_OR_NOT_DST	0x000a
 743#define MIX_OR			0x000b
 744#define MIX_AND			0x000c
 745#define MIX_SRC_AND_NOT_DST	0x000d
 746#define MIX_NOT_SRC_AND_DST	0x000e
 747#define MIX_NOR			0x000f
 748
 749/* Maximum engine dimensions */
 750#define ENGINE_MIN_X		0
 751#define ENGINE_MIN_Y		0
 752#define ENGINE_MAX_X		4095
 753#define ENGINE_MAX_Y		16383
 754
 755/* Mach64 engine bit constants - these are typically ORed together */
 756
 757/* BUS_CNTL register constants */
 758#define BUS_APER_REG_DIS	0x00000010
 759#define BUS_FIFO_ERR_ACK	0x00200000
 760#define BUS_HOST_ERR_ACK	0x00800000
 761
 762/* GEN_TEST_CNTL register constants */
 763#define GEN_OVR_OUTPUT_EN	0x20
 764#define HWCURSOR_ENABLE		0x80
 765#define GUI_ENGINE_ENABLE	0x100
 766#define BLOCK_WRITE_ENABLE	0x200
 767
 768/* DSP_CONFIG register constants */
 769#define DSP_XCLKS_PER_QW	0x00003fff
 770#define DSP_LOOP_LATENCY	0x000f0000
 771#define DSP_PRECISION		0x00700000
 772
 773/* DSP_ON_OFF register constants */
 774#define DSP_OFF			0x000007ff
 775#define DSP_ON			0x07ff0000
 776#define VGA_DSP_OFF		DSP_OFF
 777#define VGA_DSP_ON		DSP_ON
 778#define VGA_DSP_XCLKS_PER_QW	DSP_XCLKS_PER_QW
 779
 780/* PLL register indices and fields */
 781#define MPLL_CNTL		0x00
 782#define PLL_PC_GAIN		0x07
 783#define PLL_VC_GAIN		0x18
 784#define PLL_DUTY_CYC		0xE0
 785#define VPLL_CNTL		0x01
 786#define PLL_REF_DIV		0x02
 787#define PLL_GEN_CNTL		0x03
 788#define PLL_OVERRIDE		0x01	/* PLL_SLEEP */
 789#define PLL_MCLK_RST		0x02	/* PLL_MRESET */
 790#define OSC_EN			0x04
 791#define EXT_CLK_EN		0x08
 792#define FORCE_DCLK_TRI_STATE	0x08    /* VT4 -> */
 793#define MCLK_SRC_SEL		0x70
 794#define EXT_CLK_CNTL		0x80
 795#define DLL_PWDN		0x80    /* VT4 -> */
 796#define MCLK_FB_DIV		0x04
 797#define PLL_VCLK_CNTL		0x05
 798#define PLL_VCLK_SRC_SEL	0x03
 799#define PLL_VCLK_RST		0x04
 800#define PLL_VCLK_INVERT		0x08
 801#define VCLK_POST_DIV		0x06
 802#define VCLK0_POST		0x03
 803#define VCLK1_POST		0x0C
 804#define VCLK2_POST		0x30
 805#define VCLK3_POST		0xC0
 806#define VCLK0_FB_DIV		0x07
 807#define VCLK1_FB_DIV		0x08
 808#define VCLK2_FB_DIV		0x09
 809#define VCLK3_FB_DIV		0x0A
 810#define PLL_EXT_CNTL		0x0B
 811#define PLL_XCLK_MCLK_RATIO	0x03
 812#define PLL_XCLK_SRC_SEL	0x07
 813#define PLL_MFB_TIMES_4_2B	0x08
 814#define PLL_VCLK0_XDIV		0x10
 815#define PLL_VCLK1_XDIV		0x20
 816#define PLL_VCLK2_XDIV		0x40
 817#define PLL_VCLK3_XDIV		0x80
 818#define DLL_CNTL		0x0C
 819#define DLL1_CNTL		0x0C
 820#define VFC_CNTL		0x0D
 821#define PLL_TEST_CNTL		0x0E
 822#define PLL_TEST_COUNT		0x0F
 823#define LVDS_CNTL0		0x10
 824#define LVDS_CNTL1		0x11
 825#define AGP1_CNTL		0x12
 826#define AGP2_CNTL		0x13
 827#define DLL2_CNTL		0x14
 828#define SCLK_FB_DIV		0x15
 829#define SPLL_CNTL1		0x16
 830#define SPLL_CNTL2		0x17
 831#define APLL_STRAPS		0x18
 832#define EXT_VPLL_CNTL		0x19
 833#define EXT_VPLL_EN		0x04
 834#define EXT_VPLL_VGA_EN		0x08
 835#define EXT_VPLL_INSYNC		0x10
 836#define EXT_VPLL_REF_DIV	0x1A
 837#define EXT_VPLL_FB_DIV		0x1B
 838#define EXT_VPLL_MSB		0x1C
 839#define HTOTAL_CNTL		0x1D
 840#define BYTE_CLK_CNTL		0x1E
 841#define TV_PLL_CNTL1		0x1F
 842#define TV_PLL_CNTL2		0x20
 843#define TV_PLL_CNTL		0x21
 844#define EXT_TV_PLL		0x22
 845#define V2PLL_CNTL		0x23
 846#define PLL_V2CLK_CNTL		0x24
 847#define EXT_V2PLL_REF_DIV	0x25
 848#define EXT_V2PLL_FB_DIV	0x26
 849#define EXT_V2PLL_MSB		0x27
 850#define HTOTAL2_CNTL		0x28
 851#define PLL_YCLK_CNTL		0x29
 852#define PM_DYN_CLK_CNTL		0x2A
 853
 854/* CNFG_CNTL register constants */
 855#define APERTURE_4M_ENABLE	1
 856#define APERTURE_8M_ENABLE	2
 857#define VGA_APERTURE_ENABLE	4
 858
 859/* CNFG_STAT0 register constants (GX, CX) */
 860#define CFG_BUS_TYPE		0x00000007
 861#define CFG_MEM_TYPE		0x00000038
 862#define CFG_INIT_DAC_TYPE	0x00000e00
 863
 864/* CNFG_STAT0 register constants (CT, ET, VT) */
 865#define CFG_MEM_TYPE_xT		0x00000007
 866
 867#define ISA			0
 868#define EISA			1
 869#define LOCAL_BUS		6
 870#define PCI			7
 871
 872/* Memory types for GX, CX */
 873#define DRAMx4			0
 874#define VRAMx16			1
 875#define VRAMx16ssr		2
 876#define DRAMx16			3
 877#define GraphicsDRAMx16		4
 878#define EnhancedVRAMx16		5
 879#define EnhancedVRAMx16ssr	6
 880
 881/* Memory types for CT, ET, VT, GT */
 882#define DRAM			1
 883#define EDO			2
 884#define PSEUDO_EDO		3
 885#define SDRAM			4
 886#define SGRAM			5
 887#define WRAM			6
 888#define SDRAM32			6
 889
 890#define DAC_INTERNAL		0x00
 891#define DAC_IBMRGB514		0x01
 892#define DAC_ATI68875		0x02
 893#define DAC_TVP3026_A		0x72
 894#define DAC_BT476		0x03
 895#define DAC_BT481		0x04
 896#define DAC_ATT20C491		0x14
 897#define DAC_SC15026		0x24
 898#define DAC_MU9C1880		0x34
 899#define DAC_IMSG174		0x44
 900#define DAC_ATI68860_B		0x05
 901#define DAC_ATI68860_C		0x15
 902#define DAC_TVP3026_B		0x75
 903#define DAC_STG1700		0x06
 904#define DAC_ATT498		0x16
 905#define DAC_STG1702		0x07
 906#define DAC_SC15021		0x17
 907#define DAC_ATT21C498		0x27
 908#define DAC_STG1703		0x37
 909#define DAC_CH8398		0x47
 910#define DAC_ATT20C408		0x57
 911
 912#define CLK_ATI18818_0		0
 913#define CLK_ATI18818_1		1
 914#define CLK_STG1703		2
 915#define CLK_CH8398		3
 916#define CLK_INTERNAL		4
 917#define CLK_ATT20C408		5
 918#define CLK_IBMRGB514		6
 919
 920/* MEM_CNTL register constants */
 921#define MEM_SIZE_ALIAS		0x00000007
 922#define MEM_SIZE_512K		0x00000000
 923#define MEM_SIZE_1M		0x00000001
 924#define MEM_SIZE_2M		0x00000002
 925#define MEM_SIZE_4M		0x00000003
 926#define MEM_SIZE_6M		0x00000004
 927#define MEM_SIZE_8M		0x00000005
 928#define MEM_SIZE_ALIAS_GTB	0x0000000F
 929#define MEM_SIZE_2M_GTB		0x00000003
 930#define MEM_SIZE_4M_GTB		0x00000007
 931#define MEM_SIZE_6M_GTB		0x00000009
 932#define MEM_SIZE_8M_GTB		0x0000000B
 933#define MEM_BNDRY		0x00030000
 934#define MEM_BNDRY_0K		0x00000000
 935#define MEM_BNDRY_256K		0x00010000
 936#define MEM_BNDRY_512K		0x00020000
 937#define MEM_BNDRY_1M		0x00030000
 938#define MEM_BNDRY_EN		0x00040000
 939
 940#define ONE_MB			0x100000
 941/* ATI PCI constants */
 942#define PCI_ATI_VENDOR_ID	0x1002
 943
 944
 945/* CNFG_CHIP_ID register constants */
 946#define CFG_CHIP_TYPE		0x0000FFFF
 947#define CFG_CHIP_CLASS		0x00FF0000
 948#define CFG_CHIP_REV		0xFF000000
 949#define CFG_CHIP_MAJOR		0x07000000
 950#define CFG_CHIP_FND_ID		0x38000000
 951#define CFG_CHIP_MINOR		0xC0000000
 952
 953
 954/* Chip IDs read from CNFG_CHIP_ID */
 955
 956/* mach64GX family */
 957#define GX_CHIP_ID	0xD7	/* mach64GX (ATI888GX00) */
 958#define CX_CHIP_ID	0x57	/* mach64CX (ATI888CX00) */
 959
 960#define GX_PCI_ID	0x4758	/* mach64GX (ATI888GX00) */
 961#define CX_PCI_ID	0x4358	/* mach64CX (ATI888CX00) */
 962
 963/* mach64CT family */
 964#define CT_CHIP_ID	0x4354	/* mach64CT (ATI264CT) */
 965#define ET_CHIP_ID	0x4554	/* mach64ET (ATI264ET) */
 966
 967/* mach64CT family / mach64VT class */
 968#define VT_CHIP_ID	0x5654	/* mach64VT (ATI264VT) */
 969#define VU_CHIP_ID	0x5655	/* mach64VTB (ATI264VTB) */
 970#define VV_CHIP_ID	0x5656	/* mach64VT4 (ATI264VT4) */
 971
 972/* mach64CT family / mach64GT (3D RAGE) class */
 973#define LB_CHIP_ID	0x4c42	/* RAGE LT PRO, AGP */
 974#define LD_CHIP_ID	0x4c44	/* RAGE LT PRO */
 975#define LG_CHIP_ID	0x4c47	/* RAGE LT */
 976#define LI_CHIP_ID	0x4c49	/* RAGE LT PRO */
 977#define LP_CHIP_ID	0x4c50	/* RAGE LT PRO */
 978#define LT_CHIP_ID	0x4c54	/* RAGE LT */
 979
 980/* mach64CT family / (Rage XL) class */
 981#define GR_CHIP_ID	0x4752	/* RAGE XL, BGA, PCI33 */
 982#define GS_CHIP_ID	0x4753	/* RAGE XL, PQFP, PCI33 */
 983#define GM_CHIP_ID	0x474d	/* RAGE XL, BGA, AGP 1x,2x */
 984#define GN_CHIP_ID	0x474e	/* RAGE XL, PQFP,AGP 1x,2x */
 985#define GO_CHIP_ID	0x474f	/* RAGE XL, BGA, PCI66 */
 986#define GL_CHIP_ID	0x474c	/* RAGE XL, PQFP, PCI66 */
 987
 988#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
 989		   (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
 990		   (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
 991
 992#define GT_CHIP_ID	0x4754	/* RAGE (GT) */
 993#define GU_CHIP_ID	0x4755	/* RAGE II/II+ (GTB) */
 994#define GV_CHIP_ID	0x4756	/* RAGE IIC, PCI */
 995#define GW_CHIP_ID	0x4757	/* RAGE IIC, AGP */
 996#define GZ_CHIP_ID	0x475a	/* RAGE IIC, AGP */
 997#define GB_CHIP_ID	0x4742	/* RAGE PRO, BGA, AGP 1x and 2x */
 998#define GD_CHIP_ID	0x4744	/* RAGE PRO, BGA, AGP 1x only */
 999#define GI_CHIP_ID	0x4749	/* RAGE PRO, BGA, PCI33 only */
1000#define GP_CHIP_ID	0x4750	/* RAGE PRO, PQFP, PCI33, full 3D */
1001#define GQ_CHIP_ID	0x4751	/* RAGE PRO, PQFP, PCI33, limited 3D */
1002
1003#define LM_CHIP_ID	0x4c4d	/* RAGE Mobility AGP, full function */
1004#define LN_CHIP_ID	0x4c4e	/* RAGE Mobility AGP */
1005#define LR_CHIP_ID	0x4c52	/* RAGE Mobility PCI, full function */
1006#define LS_CHIP_ID	0x4c53	/* RAGE Mobility PCI */
1007
1008#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
1009			(id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
1010/* Mach64 major ASIC revisions */
1011#define MACH64_ASIC_NEC_VT_A3		0x08
1012#define MACH64_ASIC_NEC_VT_A4		0x48
1013#define MACH64_ASIC_SGS_VT_A4		0x40
1014#define MACH64_ASIC_SGS_VT_B1S1		0x01
1015#define MACH64_ASIC_SGS_GT_B1S1		0x01
1016#define MACH64_ASIC_SGS_GT_B1S2		0x41
1017#define MACH64_ASIC_UMC_GT_B2U1		0x1a
1018#define MACH64_ASIC_UMC_GT_B2U2		0x5a
1019#define MACH64_ASIC_UMC_VT_B2U3		0x9a
1020#define MACH64_ASIC_UMC_GT_B2U3		0x9a
1021#define MACH64_ASIC_UMC_R3B_D_P_A1	0x1b
1022#define MACH64_ASIC_UMC_R3B_D_P_A2	0x5b
1023#define MACH64_ASIC_UMC_R3B_D_P_A3	0x1c
1024#define MACH64_ASIC_UMC_R3B_D_P_A4	0x5c
1025
1026/* Mach64 foundries */
1027#define MACH64_FND_SGS		0
1028#define MACH64_FND_NEC		1
1029#define MACH64_FND_UMC		3
1030
1031/* Mach64 chip types */
1032#define MACH64_UNKNOWN		0
1033#define MACH64_GX		1
1034#define MACH64_CX		2
1035#define MACH64_CT		3Restore
1036#define MACH64_ET		4
1037#define MACH64_VT		5
1038#define MACH64_GT		6
1039
1040/* DST_CNTL register constants */
1041#define DST_X_RIGHT_TO_LEFT	0
1042#define DST_X_LEFT_TO_RIGHT	1
1043#define DST_Y_BOTTOM_TO_TOP	0
1044#define DST_Y_TOP_TO_BOTTOM	2
1045#define DST_X_MAJOR		0
1046#define DST_Y_MAJOR		4
1047#define DST_X_TILE		8
1048#define DST_Y_TILE		0x10
1049#define DST_LAST_PEL		0x20
1050#define DST_POLYGON_ENABLE	0x40
1051#define DST_24_ROTATION_ENABLE	0x80
1052
1053/* SRC_CNTL register constants */
1054#define SRC_PATTERN_ENABLE		1
1055#define SRC_ROTATION_ENABLE		2
1056#define SRC_LINEAR_ENABLE		4
1057#define SRC_BYTE_ALIGN			8
1058#define SRC_LINE_X_RIGHT_TO_LEFT	0
1059#define SRC_LINE_X_LEFT_TO_RIGHT	0x10
1060
1061/* HOST_CNTL register constants */
1062#define HOST_BYTE_ALIGN		1
1063
1064/* GUI_TRAJ_CNTL register constants */
1065#define PAT_MONO_8x8_ENABLE	0x01000000
1066#define PAT_CLR_4x2_ENABLE	0x02000000
1067#define PAT_CLR_8x1_ENABLE	0x04000000
1068
1069/* DP_CHAIN_MASK register constants */
1070#define DP_CHAIN_4BPP		0x8888
1071#define DP_CHAIN_7BPP		0xD2D2
1072#define DP_CHAIN_8BPP		0x8080
1073#define DP_CHAIN_8BPP_RGB	0x9292
1074#define DP_CHAIN_15BPP		0x4210
1075#define DP_CHAIN_16BPP		0x8410
1076#define DP_CHAIN_24BPP		0x8080
1077#define DP_CHAIN_32BPP		0x8080
1078
1079/* DP_PIX_WIDTH register constants */
1080#define DST_1BPP		0x0
1081#define DST_4BPP		0x1
1082#define DST_8BPP		0x2
1083#define DST_15BPP		0x3
1084#define DST_16BPP		0x4
1085#define DST_24BPP		0x5
1086#define DST_32BPP		0x6
1087#define DST_MASK		0xF
1088#define SRC_1BPP		0x000
1089#define SRC_4BPP		0x100
1090#define SRC_8BPP		0x200
1091#define SRC_15BPP		0x300
1092#define SRC_16BPP		0x400
1093#define SRC_24BPP		0x500
1094#define SRC_32BPP		0x600
1095#define SRC_MASK		0xF00
1096#define DP_HOST_TRIPLE_EN	0x2000
1097#define HOST_1BPP		0x00000
1098#define HOST_4BPP		0x10000
1099#define HOST_8BPP		0x20000
1100#define HOST_15BPP		0x30000
1101#define HOST_16BPP		0x40000
1102#define HOST_24BPP		0x50000
1103#define HOST_32BPP		0x60000
1104#define HOST_MASK		0xF0000
1105#define BYTE_ORDER_MSB_TO_LSB	0
1106#define BYTE_ORDER_LSB_TO_MSB	0x1000000
1107#define BYTE_ORDER_MASK		0x1000000
1108
1109/* DP_MIX register constants */
1110#define BKGD_MIX_NOT_D			0
1111#define BKGD_MIX_ZERO			1
1112#define BKGD_MIX_ONE			2
1113#define BKGD_MIX_D			3
1114#define BKGD_MIX_NOT_S			4
1115#define BKGD_MIX_D_XOR_S		5
1116#define BKGD_MIX_NOT_D_XOR_S		6
1117#define BKGD_MIX_S			7
1118#define BKGD_MIX_NOT_D_OR_NOT_S		8
1119#define BKGD_MIX_D_OR_NOT_S		9
1120#define BKGD_MIX_NOT_D_OR_S		10
1121#define BKGD_MIX_D_OR_S			11
1122#define BKGD_MIX_D_AND_S		12
1123#define BKGD_MIX_NOT_D_AND_S		13
1124#define BKGD_MIX_D_AND_NOT_S		14
1125#define BKGD_MIX_NOT_D_AND_NOT_S	15
1126#define BKGD_MIX_D_PLUS_S_DIV2		0x17
1127#define FRGD_MIX_NOT_D			0
1128#define FRGD_MIX_ZERO			0x10000
1129#define FRGD_MIX_ONE			0x20000
1130#define FRGD_MIX_D			0x30000
1131#define FRGD_MIX_NOT_S			0x40000
1132#define FRGD_MIX_D_XOR_S		0x50000
1133#define FRGD_MIX_NOT_D_XOR_S		0x60000
1134#define FRGD_MIX_S			0x70000
1135#define FRGD_MIX_NOT_D_OR_NOT_S		0x80000
1136#define FRGD_MIX_D_OR_NOT_S		0x90000
1137#define FRGD_MIX_NOT_D_OR_S		0xa0000
1138#define FRGD_MIX_D_OR_S			0xb0000
1139#define FRGD_MIX_D_AND_S		0xc0000
1140#define FRGD_MIX_NOT_D_AND_S		0xd0000
1141#define FRGD_MIX_D_AND_NOT_S		0xe0000
1142#define FRGD_MIX_NOT_D_AND_NOT_S	0xf0000
1143#define FRGD_MIX_D_PLUS_S_DIV2		0x170000
1144
1145/* DP_SRC register constants */
1146#define BKGD_SRC_BKGD_CLR	0
1147#define BKGD_SRC_FRGD_CLR	1
1148#define BKGD_SRC_HOST		2
1149#define BKGD_SRC_BLIT		3
1150#define BKGD_SRC_PATTERN	4
1151#define FRGD_SRC_BKGD_CLR	0
1152#define FRGD_SRC_FRGD_CLR	0x100
1153#define FRGD_SRC_HOST		0x200
1154#define FRGD_SRC_BLIT		0x300
1155#define FRGD_SRC_PATTERN	0x400
1156#define MONO_SRC_ONE		0
1157#define MONO_SRC_PATTERN	0x10000
1158#define MONO_SRC_HOST		0x20000
1159#define MONO_SRC_BLIT		0x30000
1160
1161/* CLR_CMP_CNTL register constants */
1162#define COMPARE_FALSE		0
1163#define COMPARE_TRUE		1
1164#define COMPARE_NOT_EQUAL	4
1165#define COMPARE_EQUAL		5
1166#define COMPARE_DESTINATION	0
1167#define COMPARE_SOURCE		0x1000000
1168
1169/* FIFO_STAT register constants */
1170#define FIFO_ERR		0x80000000
1171
1172/* CONTEXT_LOAD_CNTL constants */
1173#define CONTEXT_NO_LOAD			0
1174#define CONTEXT_LOAD			0x10000
1175#define CONTEXT_LOAD_AND_DO_FILL	0x20000
1176#define CONTEXT_LOAD_AND_DO_LINE	0x30000
1177#define CONTEXT_EXECUTE			0
1178#define CONTEXT_CMD_DISABLE		0x80000000
1179
1180/* GUI_STAT register constants */
1181#define ENGINE_IDLE			0
1182#define ENGINE_BUSY			1
1183#define SCISSOR_LEFT_FLAG		0x10
1184#define SCISSOR_RIGHT_FLAG		0x20
1185#define SCISSOR_TOP_FLAG		0x40
1186#define SCISSOR_BOTTOM_FLAG		0x80
1187
1188/* ATI VGA Extended Regsiters */
1189#define sioATIEXT		0x1ce
1190#define bioATIEXT		0x3ce
1191
1192#define ATI2E			0xae
1193#define ATI32			0xb2
1194#define ATI36			0xb6
1195
1196/* VGA Graphics Controller Registers */
1197#define R_GENMO			0x3cc
1198#define VGAGRA			0x3ce
1199#define GRA06			0x06
1200
1201/* VGA Seququencer Registers */
1202#define VGASEQ			0x3c4
1203#define SEQ02			0x02
1204#define SEQ04			0x04
1205
1206#define MACH64_MAX_X		ENGINE_MAX_X
1207#define MACH64_MAX_Y		ENGINE_MAX_Y
1208
1209#define INC_X			0x0020
1210#define INC_Y			0x0080
1211
1212#define RGB16_555		0x0000
1213#define RGB16_565		0x0040
1214#define RGB16_655		0x0080
1215#define RGB16_664		0x00c0
1216
1217#define POLY_TEXT_TYPE		0x0001
1218#define IMAGE_TEXT_TYPE		0x0002
1219#define TEXT_TYPE_8_BIT		0x0004
1220#define TEXT_TYPE_16_BIT	0x0008
1221#define POLY_TEXT_TYPE_8	(POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
1222#define IMAGE_TEXT_TYPE_8	(IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
1223#define POLY_TEXT_TYPE_16	(POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
1224#define IMAGE_TEXT_TYPE_16	(IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
1225
1226#define MACH64_NUM_CLOCKS	16
1227#define MACH64_NUM_FREQS	50
1228
1229/* Power Management register constants (LT & LT Pro) */
1230#define PWR_MGT_ON		0x00000001
1231#define PWR_MGT_MODE_MASK	0x00000006
1232#define AUTO_PWR_UP		0x00000008
1233#define USE_F32KHZ		0x00000400
1234#define TRISTATE_MEM_EN		0x00000800
1235#define SELF_REFRESH		0x00000080
1236#define PWR_BLON		0x02000000
1237#define STANDBY_NOW		0x10000000
1238#define SUSPEND_NOW		0x20000000
1239#define PWR_MGT_STATUS_MASK	0xC0000000
1240#define PWR_MGT_STATUS_SUSPEND	0x80000000
1241
1242/* PM Mode constants  */
1243#define PWR_MGT_MODE_PIN	0x00000000
1244#define PWR_MGT_MODE_REG	0x00000002
1245#define PWR_MGT_MODE_TIMER	0x00000004
1246#define PWR_MGT_MODE_PCI	0x00000006
1247
1248/* LCD registers (LT Pro) */
1249
1250/* LCD Index register */
1251#define LCD_INDEX_MASK		0x0000003F
1252#define LCD_DISPLAY_DIS		0x00000100
1253#define LCD_SRC_SEL		0x00000200
1254#define CRTC2_DISPLAY_DIS	0x00000400
1255
1256/* LCD register indices */
1257#define CNFG_PANEL		0x00
1258#define LCD_GEN_CNTL		0x01
1259#define DSTN_CONTROL		0x02
1260#define HFB_PITCH_ADDR		0x03
1261#define HORZ_STRETCHING		0x04
1262#define VERT_STRETCHING		0x05
1263#define EXT_VERT_STRETCH	0x06
1264#define LT_GIO			0x07
1265#define POWER_MANAGEMENT	0x08
1266#define ZVGPIO			0x09
1267#define ICON_CLR0		0x0A
1268#define ICON_CLR1		0x0B
1269#define ICON_OFFSET		0x0C
1270#define ICON_HORZ_VERT_POSN	0x0D
1271#define ICON_HORZ_VERT_OFF	0x0E
1272#define ICON2_CLR0		0x0F
1273#define ICON2_CLR1		0x10
1274#define ICON2_OFFSET		0x11
1275#define ICON2_HORZ_VERT_POSN	0x12
1276#define ICON2_HORZ_VERT_OFF	0x13
1277#define LCD_MISC_CNTL		0x14
1278#define APC_CNTL		0x1C
1279#define POWER_MANAGEMENT_2	0x1D
1280#define ALPHA_BLENDING		0x25
1281#define PORTRAIT_GEN_CNTL	0x26
1282#define APC_CTRL_IO		0x27
1283#define TEST_IO			0x28
1284#define TEST_OUTPUTS		0x29
1285#define DP1_MEM_ACCESS		0x2A
1286#define DP0_MEM_ACCESS		0x2B
1287#define DP0_DEBUG_A		0x2C
1288#define DP0_DEBUG_B		0x2D
1289#define DP1_DEBUG_A		0x2E
1290#define DP1_DEBUG_B		0x2F
1291#define DPCTRL_DEBUG_A		0x30
1292#define DPCTRL_DEBUG_B		0x31
1293#define MEMBLK_DEBUG		0x32
1294#define APC_LUT_AB		0x33
1295#define APC_LUT_CD		0x34
1296#define APC_LUT_EF		0x35
1297#define APC_LUT_GH		0x36
1298#define APC_LUT_IJ		0x37
1299#define APC_LUT_KL		0x38
1300#define APC_LUT_MN		0x39
1301#define APC_LUT_OP		0x3A
1302
1303/* Values in LCD_GEN_CTRL */
1304#define CRT_ON                          0x00000001ul
1305#define LCD_ON                          0x00000002ul
1306#define HORZ_DIVBY2_EN                  0x00000004ul
1307#define DONT_DS_ICON                    0x00000008ul
1308#define LOCK_8DOT                       0x00000010ul
1309#define ICON_ENABLE                     0x00000020ul
1310#define DONT_SHADOW_VPAR                0x00000040ul
1311#define V2CLK_PM_EN                     0x00000080ul
1312#define RST_FM                          0x00000100ul
1313#define DISABLE_PCLK_RESET              0x00000200ul	/* XC/XL */
1314#define DIS_HOR_CRT_DIVBY2              0x00000400ul
1315#define SCLK_SEL                        0x00000800ul
1316#define SCLK_DELAY                      0x0000f000ul
1317#define TVCLK_PM_EN                     0x00010000ul
1318#define VCLK_DAC_PM_EN                  0x00020000ul
1319#define VCLK_LCD_OFF                    0x00040000ul
1320#define SELECT_WAIT_4MS                 0x00080000ul
1321#define XTALIN_PM_EN                    0x00080000ul	/* XC/XL */
1322#define V2CLK_DAC_PM_EN                 0x00100000ul
1323#define LVDS_EN                         0x00200000ul
1324#define LVDS_PLL_EN                     0x00400000ul
1325#define LVDS_PLL_RESET                  0x00800000ul
1326#define LVDS_RESERVED_BITS              0x07000000ul
1327#define CRTC_RW_SELECT                  0x08000000ul	/* LTPro */
1328#define USE_SHADOWED_VEND               0x10000000ul
1329#define USE_SHADOWED_ROWCUR             0x20000000ul
1330#define SHADOW_EN                       0x40000000ul
1331#define SHADOW_RW_EN                  	0x80000000ul
1332
1333#define LCD_SET_PRIMARY_MASK            0x07FFFBFBul
1334
1335/* Values in HORZ_STRETCHING */
1336#define HORZ_STRETCH_BLEND		0x00000ffful
1337#define HORZ_STRETCH_RATIO		0x0000fffful
1338#define HORZ_STRETCH_LOOP		0x00070000ul
1339#define HORZ_STRETCH_LOOP09		0x00000000ul
1340#define HORZ_STRETCH_LOOP11		0x00010000ul
1341#define HORZ_STRETCH_LOOP12		0x00020000ul
1342#define HORZ_STRETCH_LOOP14		0x00030000ul
1343#define HORZ_STRETCH_LOOP15		0x00040000ul
1344/*	?				0x00050000ul */
1345/*	?				0x00060000ul */
1346/*	?				0x00070000ul */
1347/*	?				0x00080000ul */
1348#define HORZ_PANEL_SIZE			0x0ff00000ul	/* XC/XL */
1349/*	?				0x10000000ul */
1350#define AUTO_HORZ_RATIO			0x20000000ul	/* XC/XL */
1351#define HORZ_STRETCH_MODE		0x40000000ul
1352#define HORZ_STRETCH_EN			0x80000000ul
1353
1354/* Values in VERT_STRETCHING */
1355#define VERT_STRETCH_RATIO0		0x000003fful
1356#define VERT_STRETCH_RATIO1		0x000ffc00ul
1357#define VERT_STRETCH_RATIO2		0x3ff00000ul
1358#define VERT_STRETCH_USE0		0x40000000ul
1359#define VERT_STRETCH_EN			0x80000000ul
1360
1361/* Values in EXT_VERT_STRETCH */
1362#define VERT_STRETCH_RATIO3		0x000003fful
1363#define FORCE_DAC_DATA			0x000000fful
1364#define FORCE_DAC_DATA_SEL		0x00000300ul
1365#define VERT_STRETCH_MODE		0x00000400ul
1366#define VERT_PANEL_SIZE			0x003ff800ul
1367#define AUTO_VERT_RATIO			0x00400000ul
1368#define USE_AUTO_FP_POS			0x00800000ul
1369#define USE_AUTO_LCD_VSYNC		0x01000000ul
1370/*	?				0xfe000000ul */
1371
1372/* Values in LCD_MISC_CNTL */
1373#define BIAS_MOD_LEVEL_MASK		0x0000ff00
1374#define BIAS_MOD_LEVEL_SHIFT		8
1375#define BLMOD_EN			0x00010000
1376#define BIASMOD_EN			0x00020000
1377
1378#endif				/* REGMACH64_H */

   1/*
   2 * ATI Mach64 Register Definitions
   3 *
   4 * Copyright (C) 1997 Michael AK Tesch
   5 *  written with much help from Jon Howell
   6 *
   7 * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
   8 *	
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version
  12 * 2 of the License, or (at your option) any later version.
  13 */
  14
  15/*
  16 * most of the rest of this file comes from ATI sample code
  17 */
  18#ifndef REGMACH64_H
  19#define REGMACH64_H
  20
  21/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
  22
  23/* Accelerator CRTC */
  24#define CRTC_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
  25#define CRTC2_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
  26#define CRTC_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
  27#define CRTC2_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
  28#define CRTC_H_SYNC_STRT	0x0004
  29#define CRTC2_H_SYNC_STRT	0x0004
  30#define CRTC_H_SYNC_DLY		0x0005
  31#define CRTC2_H_SYNC_DLY	0x0005
  32#define CRTC_H_SYNC_WID		0x0006
  33#define CRTC2_H_SYNC_WID	0x0006
  34#define CRTC_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
  35#define CRTC2_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
  36#define CRTC_V_TOTAL		0x0008
  37#define CRTC2_V_TOTAL		0x0008
  38#define CRTC_V_DISP		0x000A
  39#define CRTC2_V_DISP		0x000A
  40#define CRTC_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
  41#define CRTC2_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
  42#define CRTC_V_SYNC_STRT	0x000C
  43#define CRTC2_V_SYNC_STRT	0x000C
  44#define CRTC_V_SYNC_WID		0x000E
  45#define CRTC2_V_SYNC_WID	0x000E
  46#define CRTC_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
  47#define CRTC2_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
  48#define CRTC_OFF_PITCH		0x0014	/* Dword offset 0_05 */
  49#define CRTC_OFFSET		0x0014
  50#define CRTC_PITCH		0x0016
  51#define CRTC_INT_CNTL		0x0018	/* Dword offset 0_06 */
  52#define CRTC_GEN_CNTL		0x001C	/* Dword offset 0_07 */
  53#define CRTC_PIX_WIDTH		0x001D
  54#define CRTC_FIFO		0x001E
  55#define CRTC_EXT_DISP		0x001F
  56
  57/* Memory Buffer Control */
  58#define DSP_CONFIG		0x0020	/* Dword offset 0_08 */
  59#define PM_DSP_CONFIG		0x0020	/* Dword offset 0_08 (Mobility Only) */
  60#define DSP_ON_OFF		0x0024	/* Dword offset 0_09 */
  61#define PM_DSP_ON_OFF		0x0024	/* Dword offset 0_09 (Mobility Only) */
  62#define TIMER_CONFIG		0x0028	/* Dword offset 0_0A */
  63#define MEM_BUF_CNTL		0x002C	/* Dword offset 0_0B */
  64#define MEM_ADDR_CONFIG		0x0034	/* Dword offset 0_0D */
  65
  66/* Accelerator CRTC */
  67#define CRT_TRAP		0x0038	/* Dword offset 0_0E */
  68
  69#define I2C_CNTL_0		0x003C	/* Dword offset 0_0F */
  70
  71#define DSTN_CONTROL_LG		0x003C	/* Dword offset 0_0F (LG) */
  72
  73/* Overscan */
  74#define OVR_CLR			0x0040	/* Dword offset 0_10 */
  75#define OVR2_CLR		0x0040	/* Dword offset 0_10 */
  76#define OVR_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
  77#define OVR2_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
  78#define OVR_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
  79#define OVR2_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
  80
  81/* Memory Buffer Control */
  82#define VGA_DSP_CONFIG		0x004C	/* Dword offset 0_13 */
  83#define PM_VGA_DSP_CONFIG	0x004C	/* Dword offset 0_13 (Mobility Only) */
  84#define VGA_DSP_ON_OFF		0x0050	/* Dword offset 0_14 */
  85#define PM_VGA_DSP_ON_OFF	0x0050	/* Dword offset 0_14 (Mobility Only) */
  86#define DSP2_CONFIG		0x0054	/* Dword offset 0_15 */
  87#define PM_DSP2_CONFIG		0x0054	/* Dword offset 0_15 (Mobility Only) */
  88#define DSP2_ON_OFF		0x0058	/* Dword offset 0_16 */
  89#define PM_DSP2_ON_OFF		0x0058	/* Dword offset 0_16 (Mobility Only) */
  90
  91/* Accelerator CRTC */
  92#define CRTC2_OFF_PITCH		0x005C	/* Dword offset 0_17 */
  93
  94/* Hardware Cursor */
  95#define CUR_CLR0		0x0060	/* Dword offset 0_18 */
  96#define CUR2_CLR0		0x0060	/* Dword offset 0_18 */
  97#define CUR_CLR1		0x0064	/* Dword offset 0_19 */
  98#define CUR2_CLR1		0x0064	/* Dword offset 0_19 */
  99#define CUR_OFFSET		0x0068	/* Dword offset 0_1A */
 100#define CUR2_OFFSET		0x0068	/* Dword offset 0_1A */
 101#define CUR_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
 102#define CUR2_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
 103#define CUR_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
 104#define CUR2_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
 105
 106#define CNFG_PANEL_LG		0x0074	/* Dword offset 0_1D (LG) */
 107
 108/* General I/O Control */
 109#define GP_IO			0x0078	/* Dword offset 0_1E */
 110
 111/* Test and Debug */
 112#define HW_DEBUG		0x007C	/* Dword offset 0_1F */
 113
 114/* Scratch Pad and Test */
 115#define SCRATCH_REG0		0x0080	/* Dword offset 0_20 */
 116#define SCRATCH_REG1		0x0084	/* Dword offset 0_21 */
 117#define SCRATCH_REG2		0x0088	/* Dword offset 0_22 */
 118#define SCRATCH_REG3		0x008C	/* Dword offset 0_23 */
 119
 120/* Clock Control */
 121#define CLOCK_CNTL			0x0090	/* Dword offset 0_24 */
 122/* CLOCK_CNTL register constants CT LAYOUT */
 123#define CLOCK_SEL			0x0f
 124#define CLOCK_SEL_INTERNAL		0x03
 125#define CLOCK_SEL_EXTERNAL		0x0c
 126#define CLOCK_DIV			0x30
 127#define CLOCK_DIV1			0x00
 128#define CLOCK_DIV2			0x10
 129#define CLOCK_DIV4			0x20
 130#define CLOCK_STROBE			0x40
 131/*  ?					0x80 */
 132/* CLOCK_CNTL register constants GX LAYOUT */
 133#define CLOCK_BIT			0x04	/* For ICS2595 */
 134#define CLOCK_PULSE			0x08	/* For ICS2595 */
 135/*#define CLOCK_STROBE			0x40 dito as CT */
 136#define CLOCK_DATA			0x80
 137
 138/* For internal PLL(CT) start */
 139#define CLOCK_CNTL_ADDR			CLOCK_CNTL + 1
 140#define PLL_WR_EN			0x02
 141#define PLL_ADDR			0xfc
 142#define CLOCK_CNTL_DATA			CLOCK_CNTL + 2
 143#define PLL_DATA			0xff
 144/* For internal PLL(CT) end */
 145
 146#define CLOCK_SEL_CNTL		0x0090	/* Dword offset 0_24 */
 147
 148/* Configuration */
 149#define CNFG_STAT1		0x0094	/* Dword offset 0_25 */
 150#define CNFG_STAT2		0x0098	/* Dword offset 0_26 */
 151
 152/* Bus Control */
 153#define BUS_CNTL		0x00A0	/* Dword offset 0_28 */
 154
 155#define LCD_INDEX		0x00A4	/* Dword offset 0_29 */
 156#define LCD_DATA		0x00A8	/* Dword offset 0_2A */
 157
 158#define HFB_PITCH_ADDR_LG	0x00A8	/* Dword offset 0_2A (LG) */
 159
 160/* Memory Control */
 161#define EXT_MEM_CNTL		0x00AC	/* Dword offset 0_2B */
 162#define MEM_CNTL		0x00B0	/* Dword offset 0_2C */
 163#define MEM_VGA_WP_SEL		0x00B4	/* Dword offset 0_2D */
 164#define MEM_VGA_RP_SEL		0x00B8	/* Dword offset 0_2E */
 165
 166#define I2C_CNTL_1		0x00BC	/* Dword offset 0_2F */
 167
 168#define LT_GIO_LG		0x00BC	/* Dword offset 0_2F (LG) */
 169
 170/* DAC Control */
 171#define DAC_REGS		0x00C0	/* Dword offset 0_30 */
 172#define DAC_W_INDEX		0x00C0	/* Dword offset 0_30 */
 173#define DAC_DATA		0x00C1	/* Dword offset 0_30 */
 174#define DAC_MASK		0x00C2	/* Dword offset 0_30 */
 175#define DAC_R_INDEX		0x00C3	/* Dword offset 0_30 */
 176#define DAC_CNTL		0x00C4	/* Dword offset 0_31 */
 177
 178#define EXT_DAC_REGS		0x00C8	/* Dword offset 0_32 */
 179
 180#define HORZ_STRETCHING_LG	0x00C8	/* Dword offset 0_32 (LG) */
 181#define VERT_STRETCHING_LG	0x00CC	/* Dword offset 0_33 (LG) */
 182
 183/* Test and Debug */
 184#define GEN_TEST_CNTL		0x00D0	/* Dword offset 0_34 */
 185
 186/* Custom Macros */
 187#define CUSTOM_MACRO_CNTL	0x00D4	/* Dword offset 0_35 */
 188
 189#define LCD_GEN_CNTL_LG		0x00D4	/* Dword offset 0_35 (LG) */
 190#define POWER_MANAGEMENT_LG	0x00D8	/* Dword offset 0_36 (LG) */
 191
 192/* Configuration */
 193#define CNFG_CNTL		0x00DC	/* Dword offset 0_37 (CT, ET, VT) */
 194#define CNFG_CHIP_ID		0x00E0	/* Dword offset 0_38 */
 195#define CNFG_STAT0		0x00E4	/* Dword offset 0_39 */
 196
 197/* Test and Debug */
 198#define CRC_SIG			0x00E8	/* Dword offset 0_3A */
 199#define CRC2_SIG		0x00E8	/* Dword offset 0_3A */
 200
 201
 202/* GUI MEMORY MAPPED Registers */
 203
 204/* Draw Engine Destination Trajectory */
 205#define DST_OFF_PITCH		0x0100	/* Dword offset 0_40 */
 206#define DST_X			0x0104	/* Dword offset 0_41 */
 207#define DST_Y			0x0108	/* Dword offset 0_42 */
 208#define DST_Y_X			0x010C	/* Dword offset 0_43 */
 209#define DST_WIDTH		0x0110	/* Dword offset 0_44 */
 210#define DST_HEIGHT		0x0114	/* Dword offset 0_45 */
 211#define DST_HEIGHT_WIDTH	0x0118	/* Dword offset 0_46 */
 212#define DST_X_WIDTH		0x011C	/* Dword offset 0_47 */
 213#define DST_BRES_LNTH		0x0120	/* Dword offset 0_48 */
 214#define DST_BRES_ERR		0x0124	/* Dword offset 0_49 */
 215#define DST_BRES_INC		0x0128	/* Dword offset 0_4A */
 216#define DST_BRES_DEC		0x012C	/* Dword offset 0_4B */
 217#define DST_CNTL		0x0130	/* Dword offset 0_4C */
 218#define DST_Y_X__ALIAS__	0x0134	/* Dword offset 0_4D */
 219#define TRAIL_BRES_ERR		0x0138	/* Dword offset 0_4E */
 220#define TRAIL_BRES_INC		0x013C	/* Dword offset 0_4F */
 221#define TRAIL_BRES_DEC		0x0140	/* Dword offset 0_50 */
 222#define LEAD_BRES_LNTH		0x0144	/* Dword offset 0_51 */
 223#define Z_OFF_PITCH		0x0148	/* Dword offset 0_52 */
 224#define Z_CNTL			0x014C	/* Dword offset 0_53 */
 225#define ALPHA_TST_CNTL		0x0150	/* Dword offset 0_54 */
 226#define SECONDARY_STW_EXP	0x0158	/* Dword offset 0_56 */
 227#define SECONDARY_S_X_INC	0x015C	/* Dword offset 0_57 */
 228#define SECONDARY_S_Y_INC	0x0160	/* Dword offset 0_58 */
 229#define SECONDARY_S_START	0x0164	/* Dword offset 0_59 */
 230#define SECONDARY_W_X_INC	0x0168	/* Dword offset 0_5A */
 231#define SECONDARY_W_Y_INC	0x016C	/* Dword offset 0_5B */
 232#define SECONDARY_W_START	0x0170	/* Dword offset 0_5C */
 233#define SECONDARY_T_X_INC	0x0174	/* Dword offset 0_5D */
 234#define SECONDARY_T_Y_INC	0x0178	/* Dword offset 0_5E */
 235#define SECONDARY_T_START	0x017C	/* Dword offset 0_5F */
 236
 237/* Draw Engine Source Trajectory */
 238#define SRC_OFF_PITCH		0x0180	/* Dword offset 0_60 */
 239#define SRC_X			0x0184	/* Dword offset 0_61 */
 240#define SRC_Y			0x0188	/* Dword offset 0_62 */
 241#define SRC_Y_X			0x018C	/* Dword offset 0_63 */
 242#define SRC_WIDTH1		0x0190	/* Dword offset 0_64 */
 243#define SRC_HEIGHT1		0x0194	/* Dword offset 0_65 */
 244#define SRC_HEIGHT1_WIDTH1	0x0198	/* Dword offset 0_66 */
 245#define SRC_X_START		0x019C	/* Dword offset 0_67 */
 246#define SRC_Y_START		0x01A0	/* Dword offset 0_68 */
 247#define SRC_Y_X_START		0x01A4	/* Dword offset 0_69 */
 248#define SRC_WIDTH2		0x01A8	/* Dword offset 0_6A */
 249#define SRC_HEIGHT2		0x01AC	/* Dword offset 0_6B */
 250#define SRC_HEIGHT2_WIDTH2	0x01B0	/* Dword offset 0_6C */
 251#define SRC_CNTL		0x01B4	/* Dword offset 0_6D */
 252
 253#define SCALE_OFF		0x01C0	/* Dword offset 0_70 */
 254#define SECONDARY_SCALE_OFF	0x01C4	/* Dword offset 0_71 */
 255
 256#define TEX_0_OFF		0x01C0	/* Dword offset 0_70 */
 257#define TEX_1_OFF		0x01C4	/* Dword offset 0_71 */
 258#define TEX_2_OFF		0x01C8	/* Dword offset 0_72 */
 259#define TEX_3_OFF		0x01CC	/* Dword offset 0_73 */
 260#define TEX_4_OFF		0x01D0	/* Dword offset 0_74 */
 261#define TEX_5_OFF		0x01D4	/* Dword offset 0_75 */
 262#define TEX_6_OFF		0x01D8	/* Dword offset 0_76 */
 263#define TEX_7_OFF		0x01DC	/* Dword offset 0_77 */
 264
 265#define SCALE_WIDTH		0x01DC	/* Dword offset 0_77 */
 266#define SCALE_HEIGHT		0x01E0	/* Dword offset 0_78 */
 267
 268#define TEX_8_OFF		0x01E0	/* Dword offset 0_78 */
 269#define TEX_9_OFF		0x01E4	/* Dword offset 0_79 */
 270#define TEX_10_OFF		0x01E8	/* Dword offset 0_7A */
 271#define S_Y_INC			0x01EC	/* Dword offset 0_7B */
 272
 273#define SCALE_PITCH		0x01EC	/* Dword offset 0_7B */
 274#define SCALE_X_INC		0x01F0	/* Dword offset 0_7C */
 275
 276#define RED_X_INC		0x01F0	/* Dword offset 0_7C */
 277#define GREEN_X_INC		0x01F4	/* Dword offset 0_7D */
 278
 279#define SCALE_Y_INC		0x01F4	/* Dword offset 0_7D */
 280#define SCALE_VACC		0x01F8	/* Dword offset 0_7E */
 281#define SCALE_3D_CNTL		0x01FC	/* Dword offset 0_7F */
 282
 283/* Host Data */
 284#define HOST_DATA0		0x0200	/* Dword offset 0_80 */
 285#define HOST_DATA1		0x0204	/* Dword offset 0_81 */
 286#define HOST_DATA2		0x0208	/* Dword offset 0_82 */
 287#define HOST_DATA3		0x020C	/* Dword offset 0_83 */
 288#define HOST_DATA4		0x0210	/* Dword offset 0_84 */
 289#define HOST_DATA5		0x0214	/* Dword offset 0_85 */
 290#define HOST_DATA6		0x0218	/* Dword offset 0_86 */
 291#define HOST_DATA7		0x021C	/* Dword offset 0_87 */
 292#define HOST_DATA8		0x0220	/* Dword offset 0_88 */
 293#define HOST_DATA9		0x0224	/* Dword offset 0_89 */
 294#define HOST_DATAA		0x0228	/* Dword offset 0_8A */
 295#define HOST_DATAB		0x022C	/* Dword offset 0_8B */
 296#define HOST_DATAC		0x0230	/* Dword offset 0_8C */
 297#define HOST_DATAD		0x0234	/* Dword offset 0_8D */
 298#define HOST_DATAE		0x0238	/* Dword offset 0_8E */
 299#define HOST_DATAF		0x023C	/* Dword offset 0_8F */
 300#define HOST_CNTL		0x0240	/* Dword offset 0_90 */
 301
 302/* GUI Bus Mastering */
 303#define BM_HOSTDATA		0x0244	/* Dword offset 0_91 */
 304#define BM_ADDR			0x0248	/* Dword offset 0_92 */
 305#define BM_DATA			0x0248	/* Dword offset 0_92 */
 306#define BM_GUI_TABLE_CMD	0x024C	/* Dword offset 0_93 */
 307
 308/* Pattern */
 309#define PAT_REG0		0x0280	/* Dword offset 0_A0 */
 310#define PAT_REG1		0x0284	/* Dword offset 0_A1 */
 311#define PAT_CNTL		0x0288	/* Dword offset 0_A2 */
 312
 313/* Scissors */
 314#define SC_LEFT			0x02A0	/* Dword offset 0_A8 */
 315#define SC_RIGHT		0x02A4	/* Dword offset 0_A9 */
 316#define SC_LEFT_RIGHT		0x02A8	/* Dword offset 0_AA */
 317#define SC_TOP			0x02AC	/* Dword offset 0_AB */
 318#define SC_BOTTOM		0x02B0	/* Dword offset 0_AC */
 319#define SC_TOP_BOTTOM		0x02B4	/* Dword offset 0_AD */
 320
 321/* Data Path */
 322#define USR1_DST_OFF_PITCH	0x02B8	/* Dword offset 0_AE */
 323#define USR2_DST_OFF_PITCH	0x02BC	/* Dword offset 0_AF */
 324#define DP_BKGD_CLR		0x02C0	/* Dword offset 0_B0 */
 325#define DP_FOG_CLR		0x02C4	/* Dword offset 0_B1 */
 326#define DP_FRGD_CLR		0x02C4	/* Dword offset 0_B1 */
 327#define DP_WRITE_MASK		0x02C8	/* Dword offset 0_B2 */
 328#define DP_CHAIN_MASK		0x02CC	/* Dword offset 0_B3 */
 329#define DP_PIX_WIDTH		0x02D0	/* Dword offset 0_B4 */
 330#define DP_MIX			0x02D4	/* Dword offset 0_B5 */
 331#define DP_SRC			0x02D8	/* Dword offset 0_B6 */
 332#define DP_FRGD_CLR_MIX		0x02DC	/* Dword offset 0_B7 */
 333#define DP_FRGD_BKGD_CLR	0x02E0	/* Dword offset 0_B8 */
 334
 335/* Draw Engine Destination Trajectory */
 336#define DST_X_Y			0x02E8	/* Dword offset 0_BA */
 337#define DST_WIDTH_HEIGHT	0x02EC	/* Dword offset 0_BB */
 338
 339/* Data Path */
 340#define USR_DST_PICTH		0x02F0	/* Dword offset 0_BC */
 341#define DP_SET_GUI_ENGINE2	0x02F8	/* Dword offset 0_BE */
 342#define DP_SET_GUI_ENGINE	0x02FC	/* Dword offset 0_BF */
 343
 344/* Color Compare */
 345#define CLR_CMP_CLR		0x0300	/* Dword offset 0_C0 */
 346#define CLR_CMP_MASK		0x0304	/* Dword offset 0_C1 */
 347#define CLR_CMP_CNTL		0x0308	/* Dword offset 0_C2 */
 348
 349/* Command FIFO */
 350#define FIFO_STAT		0x0310	/* Dword offset 0_C4 */
 351
 352#define CONTEXT_MASK		0x0320	/* Dword offset 0_C8 */
 353#define CONTEXT_LOAD_CNTL	0x032C	/* Dword offset 0_CB */
 354
 355/* Engine Control */
 356#define GUI_TRAJ_CNTL		0x0330	/* Dword offset 0_CC */
 357
 358/* Engine Status/FIFO */
 359#define GUI_STAT		0x0338	/* Dword offset 0_CE */
 360
 361#define TEX_PALETTE_INDEX	0x0340	/* Dword offset 0_D0 */
 362#define STW_EXP			0x0344	/* Dword offset 0_D1 */
 363#define LOG_MAX_INC		0x0348	/* Dword offset 0_D2 */
 364#define S_X_INC			0x034C	/* Dword offset 0_D3 */
 365#define S_Y_INC__ALIAS__	0x0350	/* Dword offset 0_D4 */
 366
 367#define SCALE_PITCH__ALIAS__	0x0350	/* Dword offset 0_D4 */
 368
 369#define S_START			0x0354	/* Dword offset 0_D5 */
 370#define W_X_INC			0x0358	/* Dword offset 0_D6 */
 371#define W_Y_INC			0x035C	/* Dword offset 0_D7 */
 372#define W_START			0x0360	/* Dword offset 0_D8 */
 373#define T_X_INC			0x0364	/* Dword offset 0_D9 */
 374#define T_Y_INC			0x0368	/* Dword offset 0_DA */
 375
 376#define SECONDARY_SCALE_PITCH	0x0368	/* Dword offset 0_DA */
 377
 378#define T_START			0x036C	/* Dword offset 0_DB */
 379#define TEX_SIZE_PITCH		0x0370	/* Dword offset 0_DC */
 380#define TEX_CNTL		0x0374	/* Dword offset 0_DD */
 381#define SECONDARY_TEX_OFFSET	0x0378	/* Dword offset 0_DE */
 382#define TEX_PALETTE		0x037C	/* Dword offset 0_DF */
 383
 384#define SCALE_PITCH_BOTH	0x0380	/* Dword offset 0_E0 */
 385#define SECONDARY_SCALE_OFF_ACC	0x0384	/* Dword offset 0_E1 */
 386#define SCALE_OFF_ACC		0x0388	/* Dword offset 0_E2 */
 387#define SCALE_DST_Y_X		0x038C	/* Dword offset 0_E3 */
 388
 389/* Draw Engine Destination Trajectory */
 390#define COMPOSITE_SHADOW_ID	0x0398	/* Dword offset 0_E6 */
 391
 392#define SECONDARY_SCALE_X_INC	0x039C	/* Dword offset 0_E7 */
 393
 394#define SPECULAR_RED_X_INC	0x039C	/* Dword offset 0_E7 */
 395#define SPECULAR_RED_Y_INC	0x03A0	/* Dword offset 0_E8 */
 396#define SPECULAR_RED_START	0x03A4	/* Dword offset 0_E9 */
 397
 398#define SECONDARY_SCALE_HACC	0x03A4	/* Dword offset 0_E9 */
 399
 400#define SPECULAR_GREEN_X_INC	0x03A8	/* Dword offset 0_EA */
 401#define SPECULAR_GREEN_Y_INC	0x03AC	/* Dword offset 0_EB */
 402#define SPECULAR_GREEN_START	0x03B0	/* Dword offset 0_EC */
 403#define SPECULAR_BLUE_X_INC	0x03B4	/* Dword offset 0_ED */
 404#define SPECULAR_BLUE_Y_INC	0x03B8	/* Dword offset 0_EE */
 405#define SPECULAR_BLUE_START	0x03BC	/* Dword offset 0_EF */
 406
 407#define SCALE_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
 408
 409#define RED_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
 410#define RED_Y_INC		0x03C4	/* Dword offset 0_F1 */
 411#define RED_START		0x03C8	/* Dword offset 0_F2 */
 412
 413#define SCALE_HACC		0x03C8	/* Dword offset 0_F2 */
 414#define SCALE_Y_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
 415
 416#define GREEN_X_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
 417#define GREEN_Y_INC		0x03D0	/* Dword offset 0_F4 */
 418
 419#define SECONDARY_SCALE_Y_INC	0x03D0	/* Dword offset 0_F4 */
 420#define SECONDARY_SCALE_VACC	0x03D4	/* Dword offset 0_F5 */
 421
 422#define GREEN_START		0x03D4	/* Dword offset 0_F5 */
 423#define BLUE_X_INC		0x03D8	/* Dword offset 0_F6 */
 424#define BLUE_Y_INC		0x03DC	/* Dword offset 0_F7 */
 425#define BLUE_START		0x03E0	/* Dword offset 0_F8 */
 426#define Z_X_INC			0x03E4	/* Dword offset 0_F9 */
 427#define Z_Y_INC			0x03E8	/* Dword offset 0_FA */
 428#define Z_START			0x03EC	/* Dword offset 0_FB */
 429#define ALPHA_X_INC		0x03F0	/* Dword offset 0_FC */
 430#define FOG_X_INC		0x03F0	/* Dword offset 0_FC */
 431#define ALPHA_Y_INC		0x03F4	/* Dword offset 0_FD */
 432#define FOG_Y_INC		0x03F4	/* Dword offset 0_FD */
 433#define ALPHA_START		0x03F8	/* Dword offset 0_FE */
 434#define FOG_START		0x03F8	/* Dword offset 0_FE */
 435
 436#define OVERLAY_Y_X_START		0x0400	/* Dword offset 1_00 */
 437#define OVERLAY_Y_X_END			0x0404	/* Dword offset 1_01 */
 438#define OVERLAY_VIDEO_KEY_CLR		0x0408	/* Dword offset 1_02 */
 439#define OVERLAY_VIDEO_KEY_MSK		0x040C	/* Dword offset 1_03 */
 440#define OVERLAY_GRAPHICS_KEY_CLR	0x0410	/* Dword offset 1_04 */
 441#define OVERLAY_GRAPHICS_KEY_MSK	0x0414	/* Dword offset 1_05 */
 442#define OVERLAY_KEY_CNTL		0x0418	/* Dword offset 1_06 */
 443
 444#define OVERLAY_SCALE_INC	0x0420	/* Dword offset 1_08 */
 445#define OVERLAY_SCALE_CNTL	0x0424	/* Dword offset 1_09 */
 446#define SCALER_HEIGHT_WIDTH	0x0428	/* Dword offset 1_0A */
 447#define SCALER_TEST		0x042C	/* Dword offset 1_0B */
 448#define SCALER_BUF0_OFFSET	0x0434	/* Dword offset 1_0D */
 449#define SCALER_BUF1_OFFSET	0x0438	/* Dword offset 1_0E */
 450#define SCALE_BUF_PITCH		0x043C	/* Dword offset 1_0F */
 451
 452#define CAPTURE_START_END	0x0440	/* Dword offset 1_10 */
 453#define CAPTURE_X_WIDTH		0x0444	/* Dword offset 1_11 */
 454#define VIDEO_FORMAT		0x0448	/* Dword offset 1_12 */
 455#define VBI_START_END		0x044C	/* Dword offset 1_13 */
 456#define CAPTURE_CONFIG		0x0450	/* Dword offset 1_14 */
 457#define TRIG_CNTL		0x0454	/* Dword offset 1_15 */
 458
 459#define OVERLAY_EXCLUSIVE_HORZ	0x0458	/* Dword offset 1_16 */
 460#define OVERLAY_EXCLUSIVE_VERT	0x045C	/* Dword offset 1_17 */
 461
 462#define VAL_WIDTH		0x0460	/* Dword offset 1_18 */
 463#define CAPTURE_DEBUG		0x0464	/* Dword offset 1_19 */
 464#define VIDEO_SYNC_TEST		0x0468	/* Dword offset 1_1A */
 465
 466/* GenLocking */
 467#define SNAPSHOT_VH_COUNTS	0x0470	/* Dword offset 1_1C */
 468#define SNAPSHOT_F_COUNT	0x0474	/* Dword offset 1_1D */
 469#define N_VIF_COUNT		0x0478	/* Dword offset 1_1E */
 470#define SNAPSHOT_VIF_COUNT	0x047C	/* Dword offset 1_1F */
 471
 472#define CAPTURE_BUF0_OFFSET	0x0480	/* Dword offset 1_20 */
 473#define CAPTURE_BUF1_OFFSET	0x0484	/* Dword offset 1_21 */
 474#define CAPTURE_BUF_PITCH	0x0488	/* Dword offset 1_22 */
 475
 476/* GenLocking */
 477#define SNAPSHOT2_VH_COUNTS	0x04B0	/* Dword offset 1_2C */
 478#define SNAPSHOT2_F_COUNT	0x04B4	/* Dword offset 1_2D */
 479#define N_VIF2_COUNT		0x04B8	/* Dword offset 1_2E */
 480#define SNAPSHOT2_VIF_COUNT	0x04BC	/* Dword offset 1_2F */
 481
 482#define MPP_CONFIG		0x04C0	/* Dword offset 1_30 */
 483#define MPP_STROBE_SEQ		0x04C4	/* Dword offset 1_31 */
 484#define MPP_ADDR		0x04C8	/* Dword offset 1_32 */
 485#define MPP_DATA		0x04CC	/* Dword offset 1_33 */
 486#define TVO_CNTL		0x0500	/* Dword offset 1_40 */
 487
 488/* Test and Debug */
 489#define CRT_HORZ_VERT_LOAD	0x0544	/* Dword offset 1_51 */
 490
 491/* AGP */
 492#define AGP_BASE		0x0548	/* Dword offset 1_52 */
 493#define AGP_CNTL		0x054C	/* Dword offset 1_53 */
 494
 495#define SCALER_COLOUR_CNTL	0x0550	/* Dword offset 1_54 */
 496#define SCALER_H_COEFF0		0x0554	/* Dword offset 1_55 */
 497#define SCALER_H_COEFF1		0x0558	/* Dword offset 1_56 */
 498#define SCALER_H_COEFF2		0x055C	/* Dword offset 1_57 */
 499#define SCALER_H_COEFF3		0x0560	/* Dword offset 1_58 */
 500#define SCALER_H_COEFF4		0x0564	/* Dword offset 1_59 */
 501
 502/* Command FIFO */
 503#define GUI_CMDFIFO_DEBUG	0x0570	/* Dword offset 1_5C */
 504#define GUI_CMDFIFO_DATA	0x0574	/* Dword offset 1_5D */
 505#define GUI_CNTL		0x0578	/* Dword offset 1_5E */
 506
 507/* Bus Mastering */
 508#define BM_FRAME_BUF_OFFSET	0x0580	/* Dword offset 1_60 */
 509#define BM_SYSTEM_MEM_ADDR	0x0584	/* Dword offset 1_61 */
 510#define BM_COMMAND		0x0588	/* Dword offset 1_62 */
 511#define BM_STATUS		0x058C	/* Dword offset 1_63 */
 512#define BM_GUI_TABLE		0x05B8	/* Dword offset 1_6E */
 513#define BM_SYSTEM_TABLE		0x05BC	/* Dword offset 1_6F */
 514
 515#define SCALER_BUF0_OFFSET_U	0x05D4	/* Dword offset 1_75 */
 516#define SCALER_BUF0_OFFSET_V	0x05D8	/* Dword offset 1_76 */
 517#define SCALER_BUF1_OFFSET_U	0x05DC	/* Dword offset 1_77 */
 518#define SCALER_BUF1_OFFSET_V	0x05E0	/* Dword offset 1_78 */
 519
 520/* Setup Engine */
 521#define VERTEX_1_S		0x0640	/* Dword offset 1_90 */
 522#define VERTEX_1_T		0x0644	/* Dword offset 1_91 */
 523#define VERTEX_1_W		0x0648	/* Dword offset 1_92 */
 524#define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_93 */
 525#define VERTEX_1_Z		0x0650	/* Dword offset 1_94 */
 526#define VERTEX_1_ARGB		0x0654	/* Dword offset 1_95 */
 527#define VERTEX_1_X_Y		0x0658	/* Dword offset 1_96 */
 528#define ONE_OVER_AREA		0x065C	/* Dword offset 1_97 */
 529#define VERTEX_2_S		0x0660	/* Dword offset 1_98 */
 530#define VERTEX_2_T		0x0664	/* Dword offset 1_99 */
 531#define VERTEX_2_W		0x0668	/* Dword offset 1_9A */
 532#define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_9B */
 533#define VERTEX_2_Z		0x0670	/* Dword offset 1_9C */
 534#define VERTEX_2_ARGB		0x0674	/* Dword offset 1_9D */
 535#define VERTEX_2_X_Y		0x0678	/* Dword offset 1_9E */
 536#define ONE_OVER_AREA		0x065C	/* Dword offset 1_9F */
 537#define VERTEX_3_S		0x0680	/* Dword offset 1_A0 */
 538#define VERTEX_3_T		0x0684	/* Dword offset 1_A1 */
 539#define VERTEX_3_W		0x0688	/* Dword offset 1_A2 */
 540#define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_A3 */
 541#define VERTEX_3_Z		0x0690	/* Dword offset 1_A4 */
 542#define VERTEX_3_ARGB		0x0694	/* Dword offset 1_A5 */
 543#define VERTEX_3_X_Y		0x0698	/* Dword offset 1_A6 */
 544#define ONE_OVER_AREA		0x065C	/* Dword offset 1_A7 */
 545#define VERTEX_1_S		0x0640	/* Dword offset 1_AB */
 546#define VERTEX_1_T		0x0644	/* Dword offset 1_AC */
 547#define VERTEX_1_W		0x0648	/* Dword offset 1_AD */
 548#define VERTEX_2_S		0x0660	/* Dword offset 1_AE */
 549#define VERTEX_2_T		0x0664	/* Dword offset 1_AF */
 550#define VERTEX_2_W		0x0668	/* Dword offset 1_B0 */
 551#define VERTEX_3_SECONDARY_S	0x06C0	/* Dword offset 1_B0 */
 552#define VERTEX_3_S		0x0680	/* Dword offset 1_B1 */
 553#define VERTEX_3_SECONDARY_T	0x06C4	/* Dword offset 1_B1 */
 554#define VERTEX_3_T		0x0684	/* Dword offset 1_B2 */
 555#define VERTEX_3_SECONDARY_W	0x06C8	/* Dword offset 1_B2 */
 556#define VERTEX_3_W		0x0688	/* Dword offset 1_B3 */
 557#define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_B4 */
 558#define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_B5 */
 559#define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_B6 */
 560#define VERTEX_1_Z		0x0650	/* Dword offset 1_B7 */
 561#define VERTEX_2_Z		0x0670	/* Dword offset 1_B8 */
 562#define VERTEX_3_Z		0x0690	/* Dword offset 1_B9 */
 563#define VERTEX_1_ARGB		0x0654	/* Dword offset 1_BA */
 564#define VERTEX_2_ARGB		0x0674	/* Dword offset 1_BB */
 565#define VERTEX_3_ARGB		0x0694	/* Dword offset 1_BC */
 566#define VERTEX_1_X_Y		0x0658	/* Dword offset 1_BD */
 567#define VERTEX_2_X_Y		0x0678	/* Dword offset 1_BE */
 568#define VERTEX_3_X_Y		0x0698	/* Dword offset 1_BF */
 569#define ONE_OVER_AREA_UC	0x0700	/* Dword offset 1_C0 */
 570#define SETUP_CNTL		0x0704	/* Dword offset 1_C1 */
 571#define VERTEX_1_SECONDARY_S	0x0728	/* Dword offset 1_CA */
 572#define VERTEX_1_SECONDARY_T	0x072C	/* Dword offset 1_CB */
 573#define VERTEX_1_SECONDARY_W	0x0730	/* Dword offset 1_CC */
 574#define VERTEX_2_SECONDARY_S	0x0734	/* Dword offset 1_CD */
 575#define VERTEX_2_SECONDARY_T	0x0738	/* Dword offset 1_CE */
 576#define VERTEX_2_SECONDARY_W	0x073C	/* Dword offset 1_CF */
 577
 578
 579#define GTC_3D_RESET_DELAY	3	/* 3D engine reset delay in ms */
 580
 581/* CRTC control values (mostly CRTC_GEN_CNTL) */
 582
 583#define CRTC_H_SYNC_NEG		0x00200000
 584#define CRTC_V_SYNC_NEG		0x00200000
 585
 586#define CRTC_DBL_SCAN_EN	0x00000001
 587#define CRTC_INTERLACE_EN	0x00000002
 588#define CRTC_HSYNC_DIS		0x00000004
 589#define CRTC_VSYNC_DIS		0x00000008
 590#define CRTC_CSYNC_EN		0x00000010
 591#define CRTC_PIX_BY_2_EN	0x00000020	/* unused on RAGE */
 592#define CRTC_DISPLAY_DIS	0x00000040
 593#define CRTC_VGA_XOVERSCAN	0x00000080
 594
 595#define CRTC_PIX_WIDTH_MASK	0x00000700
 596#define CRTC_PIX_WIDTH_4BPP	0x00000100
 597#define CRTC_PIX_WIDTH_8BPP	0x00000200
 598#define CRTC_PIX_WIDTH_15BPP	0x00000300
 599#define CRTC_PIX_WIDTH_16BPP	0x00000400
 600#define CRTC_PIX_WIDTH_24BPP	0x00000500
 601#define CRTC_PIX_WIDTH_32BPP	0x00000600
 602
 603#define CRTC_BYTE_PIX_ORDER	0x00000800
 604#define CRTC_PIX_ORDER_MSN_LSN	0x00000000
 605#define CRTC_PIX_ORDER_LSN_MSN	0x00000800
 606
 607#define CRTC_VSYNC_INT_EN	0x00001000ul	/* XC/XL */
 608#define CRTC_VSYNC_INT		0x00002000ul	/* XC/XL */
 609#define CRTC_FIFO_OVERFILL	0x0000c000ul	/* VT/GT */
 610#define CRTC2_VSYNC_INT_EN	0x00004000ul	/* XC/XL */
 611#define CRTC2_VSYNC_INT		0x00008000ul	/* XC/XL */
 612
 613#define CRTC_FIFO_LWM		0x000f0000
 614#define CRTC_HVSYNC_IO_DRIVE	0x00010000	/* XC/XL */
 615#define CRTC2_PIX_WIDTH		0x000e0000	/* LTPro */
 616
 617#define CRTC_VGA_128KAP_PAGING	0x00100000
 618#define CRTC_VFC_SYNC_TRISTATE	0x00200000	/* VTB/GTB/LT */
 619#define CRTC2_EN		0x00200000	/* LTPro */
 620#define CRTC_LOCK_REGS		0x00400000
 621#define CRTC_SYNC_TRISTATE	0x00800000
 622
 623#define CRTC_EXT_DISP_EN	0x01000000
 624#define CRTC_EN			0x02000000
 625#define CRTC_DISP_REQ_EN	0x04000000
 626#define CRTC_VGA_LINEAR		0x08000000
 627#define CRTC_VSYNC_FALL_EDGE	0x10000000
 628#define CRTC_VGA_TEXT_132	0x20000000
 629#define CRTC_CNT_EN		0x40000000
 630#define CRTC_CUR_B_TEST		0x80000000
 631
 632#define CRTC_CRNT_VLINE		0x07f00000
 633
 634#define CRTC_PRESERVED_MASK	0x0001f000
 635
 636#define CRTC_VBLANK		0x00000001
 637#define CRTC_VBLANK_INT_EN	0x00000002
 638#define CRTC_VBLANK_INT		0x00000004
 639#define CRTC_VBLANK_INT_AK	CRTC_VBLANK_INT
 640#define CRTC_VLINE_INT_EN	0x00000008
 641#define CRTC_VLINE_INT		0x00000010
 642#define CRTC_VLINE_INT_AK	CRTC_VLINE_INT
 643#define CRTC_VLINE_SYNC		0x00000020
 644#define CRTC_FRAME		0x00000040
 645#define SNAPSHOT_INT_EN		0x00000080
 646#define SNAPSHOT_INT		0x00000100
 647#define SNAPSHOT_INT_AK		SNAPSHOT_INT
 648#define I2C_INT_EN		0x00000200
 649#define I2C_INT			0x00000400
 650#define I2C_INT_AK		I2C_INT
 651#define CRTC2_VBLANK		0x00000800
 652#define CRTC2_VBLANK_INT_EN	0x00001000
 653#define CRTC2_VBLANK_INT	0x00002000
 654#define CRTC2_VBLANK_INT_AK	CRTC2_VBLANK_INT
 655#define CRTC2_VLINE_INT_EN	0x00004000
 656#define CRTC2_VLINE_INT		0x00008000
 657#define CRTC2_VLINE_INT_AK	CRTC2_VLINE_INT
 658#define CAPBUF0_INT_EN		0x00010000
 659#define CAPBUF0_INT		0x00020000
 660#define CAPBUF0_INT_AK		CAPBUF0_INT
 661#define CAPBUF1_INT_EN		0x00040000
 662#define CAPBUF1_INT		0x00080000
 663#define CAPBUF1_INT_AK		CAPBUF1_INT
 664#define OVERLAY_EOF_INT_EN	0x00100000
 665#define OVERLAY_EOF_INT		0x00200000
 666#define OVERLAY_EOF_INT_AK	OVERLAY_EOF_INT
 667#define ONESHOT_CAP_INT_EN	0x00400000
 668#define ONESHOT_CAP_INT		0x00800000
 669#define ONESHOT_CAP_INT_AK	ONESHOT_CAP_INT
 670#define BUSMASTER_EOL_INT_EN	0x01000000
 671#define BUSMASTER_EOL_INT	0x02000000
 672#define BUSMASTER_EOL_INT_AK	BUSMASTER_EOL_INT
 673#define GP_INT_EN		0x04000000
 674#define GP_INT			0x08000000
 675#define GP_INT_AK		GP_INT
 676#define CRTC2_VLINE_SYNC	0x10000000
 677#define SNAPSHOT2_INT_EN	0x20000000
 678#define SNAPSHOT2_INT		0x40000000
 679#define SNAPSHOT2_INT_AK	SNAPSHOT2_INT
 680#define VBLANK_BIT2_INT		0x80000000
 681#define VBLANK_BIT2_INT_AK	VBLANK_BIT2_INT
 682
 683#define CRTC_INT_EN_MASK	(CRTC_VBLANK_INT_EN |	\
 684				 CRTC_VLINE_INT_EN |	\
 685				 SNAPSHOT_INT_EN |	\
 686				 I2C_INT_EN |		\
 687				 CRTC2_VBLANK_INT_EN |	\
 688				 CRTC2_VLINE_INT_EN |	\
 689				 CAPBUF0_INT_EN |	\
 690				 CAPBUF1_INT_EN |	\
 691				 OVERLAY_EOF_INT_EN |	\
 692				 ONESHOT_CAP_INT_EN |	\
 693				 BUSMASTER_EOL_INT_EN |	\
 694				 GP_INT_EN |		\
 695				 SNAPSHOT2_INT_EN)
 696
 697/* DAC control values */
 698
 699#define DAC_EXT_SEL_RS2		0x01
 700#define DAC_EXT_SEL_RS3		0x02
 701#define DAC_8BIT_EN		0x00000100
 702#define DAC_PIX_DLY_MASK	0x00000600
 703#define DAC_PIX_DLY_0NS		0x00000000
 704#define DAC_PIX_DLY_2NS		0x00000200
 705#define DAC_PIX_DLY_4NS		0x00000400
 706#define DAC_BLANK_ADJ_MASK	0x00001800
 707#define DAC_BLANK_ADJ_0		0x00000000
 708#define DAC_BLANK_ADJ_1		0x00000800
 709#define DAC_BLANK_ADJ_2		0x00001000
 710
 711/* DAC control values (my source XL/XC Register reference) */
 712#define DAC_OUTPUT_MASK         0x00000001  /* 0 - PAL, 1 - NTSC */
 713#define DAC_MISTERY_BIT         0x00000002  /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
 714#define DAC_BLANKING            0x00000004
 715#define DAC_CMP_DISABLE         0x00000008
 716#define DAC1_CLK_SEL            0x00000010
 717#define PALETTE_ACCESS_CNTL     0x00000020
 718#define PALETTE2_SNOOP_EN       0x00000040
 719#define DAC_CMP_OUTPUT          0x00000080 /* read only */
 720/* #define DAC_8BIT_EN is ok */
 721#define CRT_SENSE               0x00000800 /* read only */
 722#define CRT_DETECTION_ON        0x00001000
 723#define DAC_VGA_ADR_EN          0x00002000
 724#define DAC_FEA_CON_EN          0x00004000
 725#define DAC_PDWN                0x00008000
 726#define DAC_TYPE_MASK           0x00070000 /* read only */
 727
 728
 729
 730/* Mix control values */
 731
 732#define MIX_NOT_DST		0x0000
 733#define MIX_0			0x0001
 734#define MIX_1			0x0002
 735#define MIX_DST			0x0003
 736#define MIX_NOT_SRC		0x0004
 737#define MIX_XOR			0x0005
 738#define MIX_XNOR		0x0006
 739#define MIX_SRC			0x0007
 740#define MIX_NAND		0x0008
 741#define MIX_NOT_SRC_OR_DST	0x0009
 742#define MIX_SRC_OR_NOT_DST	0x000a
 743#define MIX_OR			0x000b
 744#define MIX_AND			0x000c
 745#define MIX_SRC_AND_NOT_DST	0x000d
 746#define MIX_NOT_SRC_AND_DST	0x000e
 747#define MIX_NOR			0x000f
 748
 749/* Maximum engine dimensions */
 750#define ENGINE_MIN_X		0
 751#define ENGINE_MIN_Y		0
 752#define ENGINE_MAX_X		4095
 753#define ENGINE_MAX_Y		16383
 754
 755/* Mach64 engine bit constants - these are typically ORed together */
 756
 757/* BUS_CNTL register constants */
 758#define BUS_APER_REG_DIS	0x00000010
 759#define BUS_FIFO_ERR_ACK	0x00200000
 760#define BUS_HOST_ERR_ACK	0x00800000
 761
 762/* GEN_TEST_CNTL register constants */
 763#define GEN_OVR_OUTPUT_EN	0x20
 764#define HWCURSOR_ENABLE		0x80
 765#define GUI_ENGINE_ENABLE	0x100
 766#define BLOCK_WRITE_ENABLE	0x200
 767
 768/* DSP_CONFIG register constants */
 769#define DSP_XCLKS_PER_QW	0x00003fff
 770#define DSP_LOOP_LATENCY	0x000f0000
 771#define DSP_PRECISION		0x00700000
 772
 773/* DSP_ON_OFF register constants */
 774#define DSP_OFF			0x000007ff
 775#define DSP_ON			0x07ff0000
 776#define VGA_DSP_OFF		DSP_OFF
 777#define VGA_DSP_ON		DSP_ON
 778#define VGA_DSP_XCLKS_PER_QW	DSP_XCLKS_PER_QW
 779
 780/* PLL register indices and fields */
 781#define MPLL_CNTL		0x00
 782#define PLL_PC_GAIN		0x07
 783#define PLL_VC_GAIN		0x18
 784#define PLL_DUTY_CYC		0xE0
 785#define VPLL_CNTL		0x01
 786#define PLL_REF_DIV		0x02
 787#define PLL_GEN_CNTL		0x03
 788#define PLL_OVERRIDE		0x01	/* PLL_SLEEP */
 789#define PLL_MCLK_RST		0x02	/* PLL_MRESET */
 790#define OSC_EN			0x04
 791#define EXT_CLK_EN		0x08
 792#define FORCE_DCLK_TRI_STATE	0x08    /* VT4 -> */
 793#define MCLK_SRC_SEL		0x70
 794#define EXT_CLK_CNTL		0x80
 795#define DLL_PWDN		0x80    /* VT4 -> */
 796#define MCLK_FB_DIV		0x04
 797#define PLL_VCLK_CNTL		0x05
 798#define PLL_VCLK_SRC_SEL	0x03
 799#define PLL_VCLK_RST		0x04
 800#define PLL_VCLK_INVERT		0x08
 801#define VCLK_POST_DIV		0x06
 802#define VCLK0_POST		0x03
 803#define VCLK1_POST		0x0C
 804#define VCLK2_POST		0x30
 805#define VCLK3_POST		0xC0
 806#define VCLK0_FB_DIV		0x07
 807#define VCLK1_FB_DIV		0x08
 808#define VCLK2_FB_DIV		0x09
 809#define VCLK3_FB_DIV		0x0A
 810#define PLL_EXT_CNTL		0x0B
 811#define PLL_XCLK_MCLK_RATIO	0x03
 812#define PLL_XCLK_SRC_SEL	0x07
 813#define PLL_MFB_TIMES_4_2B	0x08
 814#define PLL_VCLK0_XDIV		0x10
 815#define PLL_VCLK1_XDIV		0x20
 816#define PLL_VCLK2_XDIV		0x40
 817#define PLL_VCLK3_XDIV		0x80
 818#define DLL_CNTL		0x0C
 819#define DLL1_CNTL		0x0C
 820#define VFC_CNTL		0x0D
 821#define PLL_TEST_CNTL		0x0E
 822#define PLL_TEST_COUNT		0x0F
 823#define LVDS_CNTL0		0x10
 824#define LVDS_CNTL1		0x11
 825#define AGP1_CNTL		0x12
 826#define AGP2_CNTL		0x13
 827#define DLL2_CNTL		0x14
 828#define SCLK_FB_DIV		0x15
 829#define SPLL_CNTL1		0x16
 830#define SPLL_CNTL2		0x17
 831#define APLL_STRAPS		0x18
 832#define EXT_VPLL_CNTL		0x19
 833#define EXT_VPLL_EN		0x04
 834#define EXT_VPLL_VGA_EN		0x08
 835#define EXT_VPLL_INSYNC		0x10
 836#define EXT_VPLL_REF_DIV	0x1A
 837#define EXT_VPLL_FB_DIV		0x1B
 838#define EXT_VPLL_MSB		0x1C
 839#define HTOTAL_CNTL		0x1D
 840#define BYTE_CLK_CNTL		0x1E
 841#define TV_PLL_CNTL1		0x1F
 842#define TV_PLL_CNTL2		0x20
 843#define TV_PLL_CNTL		0x21
 844#define EXT_TV_PLL		0x22
 845#define V2PLL_CNTL		0x23
 846#define PLL_V2CLK_CNTL		0x24
 847#define EXT_V2PLL_REF_DIV	0x25
 848#define EXT_V2PLL_FB_DIV	0x26
 849#define EXT_V2PLL_MSB		0x27
 850#define HTOTAL2_CNTL		0x28
 851#define PLL_YCLK_CNTL		0x29
 852#define PM_DYN_CLK_CNTL		0x2A
 853
 854/* CNFG_CNTL register constants */
 855#define APERTURE_4M_ENABLE	1
 856#define APERTURE_8M_ENABLE	2
 857#define VGA_APERTURE_ENABLE	4
 858
 859/* CNFG_STAT0 register constants (GX, CX) */
 860#define CFG_BUS_TYPE		0x00000007
 861#define CFG_MEM_TYPE		0x00000038
 862#define CFG_INIT_DAC_TYPE	0x00000e00
 863
 864/* CNFG_STAT0 register constants (CT, ET, VT) */
 865#define CFG_MEM_TYPE_xT		0x00000007
 866
 867#define ISA			0
 868#define EISA			1
 869#define LOCAL_BUS		6
 870#define PCI			7
 871
 872/* Memory types for GX, CX */
 873#define DRAMx4			0
 874#define VRAMx16			1
 875#define VRAMx16ssr		2
 876#define DRAMx16			3
 877#define GraphicsDRAMx16		4
 878#define EnhancedVRAMx16		5
 879#define EnhancedVRAMx16ssr	6
 880
 881/* Memory types for CT, ET, VT, GT */
 882#define DRAM			1
 883#define EDO			2
 884#define PSEUDO_EDO		3
 885#define SDRAM			4
 886#define SGRAM			5
 887#define WRAM			6
 888#define SDRAM32			6
 889
 890#define DAC_INTERNAL		0x00
 891#define DAC_IBMRGB514		0x01
 892#define DAC_ATI68875		0x02
 893#define DAC_TVP3026_A		0x72
 894#define DAC_BT476		0x03
 895#define DAC_BT481		0x04
 896#define DAC_ATT20C491		0x14
 897#define DAC_SC15026		0x24
 898#define DAC_MU9C1880		0x34
 899#define DAC_IMSG174		0x44
 900#define DAC_ATI68860_B		0x05
 901#define DAC_ATI68860_C		0x15
 902#define DAC_TVP3026_B		0x75
 903#define DAC_STG1700		0x06
 904#define DAC_ATT498		0x16
 905#define DAC_STG1702		0x07
 906#define DAC_SC15021		0x17
 907#define DAC_ATT21C498		0x27
 908#define DAC_STG1703		0x37
 909#define DAC_CH8398		0x47
 910#define DAC_ATT20C408		0x57
 911
 912#define CLK_ATI18818_0		0
 913#define CLK_ATI18818_1		1
 914#define CLK_STG1703		2
 915#define CLK_CH8398		3
 916#define CLK_INTERNAL		4
 917#define CLK_ATT20C408		5
 918#define CLK_IBMRGB514		6
 919
 920/* MEM_CNTL register constants */
 921#define MEM_SIZE_ALIAS		0x00000007
 922#define MEM_SIZE_512K		0x00000000
 923#define MEM_SIZE_1M		0x00000001
 924#define MEM_SIZE_2M		0x00000002
 925#define MEM_SIZE_4M		0x00000003
 926#define MEM_SIZE_6M		0x00000004
 927#define MEM_SIZE_8M		0x00000005
 928#define MEM_SIZE_ALIAS_GTB	0x0000000F
 929#define MEM_SIZE_2M_GTB		0x00000003
 930#define MEM_SIZE_4M_GTB		0x00000007
 931#define MEM_SIZE_6M_GTB		0x00000009
 932#define MEM_SIZE_8M_GTB		0x0000000B
 933#define MEM_BNDRY		0x00030000
 934#define MEM_BNDRY_0K		0x00000000
 935#define MEM_BNDRY_256K		0x00010000
 936#define MEM_BNDRY_512K		0x00020000
 937#define MEM_BNDRY_1M		0x00030000
 938#define MEM_BNDRY_EN		0x00040000
 939
 940#define ONE_MB			0x100000
 941/* ATI PCI constants */
 942#define PCI_ATI_VENDOR_ID	0x1002
 943
 944
 945/* CNFG_CHIP_ID register constants */
 946#define CFG_CHIP_TYPE		0x0000FFFF
 947#define CFG_CHIP_CLASS		0x00FF0000
 948#define CFG_CHIP_REV		0xFF000000
 949#define CFG_CHIP_MAJOR		0x07000000
 950#define CFG_CHIP_FND_ID		0x38000000
 951#define CFG_CHIP_MINOR		0xC0000000
 952
 953
 954/* Chip IDs read from CNFG_CHIP_ID */
 955
 956/* mach64GX family */
 957#define GX_CHIP_ID	0xD7	/* mach64GX (ATI888GX00) */
 958#define CX_CHIP_ID	0x57	/* mach64CX (ATI888CX00) */
 959
 960#define GX_PCI_ID	0x4758	/* mach64GX (ATI888GX00) */
 961#define CX_PCI_ID	0x4358	/* mach64CX (ATI888CX00) */
 962
 963/* mach64CT family */
 964#define CT_CHIP_ID	0x4354	/* mach64CT (ATI264CT) */
 965#define ET_CHIP_ID	0x4554	/* mach64ET (ATI264ET) */
 966
 967/* mach64CT family / mach64VT class */
 968#define VT_CHIP_ID	0x5654	/* mach64VT (ATI264VT) */
 969#define VU_CHIP_ID	0x5655	/* mach64VTB (ATI264VTB) */
 970#define VV_CHIP_ID	0x5656	/* mach64VT4 (ATI264VT4) */
 971
 972/* mach64CT family / mach64GT (3D RAGE) class */
 973#define LB_CHIP_ID	0x4c42	/* RAGE LT PRO, AGP */
 974#define LD_CHIP_ID	0x4c44	/* RAGE LT PRO */
 975#define LG_CHIP_ID	0x4c47	/* RAGE LT */
 976#define LI_CHIP_ID	0x4c49	/* RAGE LT PRO */
 977#define LP_CHIP_ID	0x4c50	/* RAGE LT PRO */
 978#define LT_CHIP_ID	0x4c54	/* RAGE LT */
 979
 980/* mach64CT family / (Rage XL) class */
 981#define GR_CHIP_ID	0x4752	/* RAGE XL, BGA, PCI33 */
 982#define GS_CHIP_ID	0x4753	/* RAGE XL, PQFP, PCI33 */
 983#define GM_CHIP_ID	0x474d	/* RAGE XL, BGA, AGP 1x,2x */
 984#define GN_CHIP_ID	0x474e	/* RAGE XL, PQFP,AGP 1x,2x */
 985#define GO_CHIP_ID	0x474f	/* RAGE XL, BGA, PCI66 */
 986#define GL_CHIP_ID	0x474c	/* RAGE XL, PQFP, PCI66 */
 987
 988#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
 989		   (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
 990		   (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
 991
 992#define GT_CHIP_ID	0x4754	/* RAGE (GT) */
 993#define GU_CHIP_ID	0x4755	/* RAGE II/II+ (GTB) */
 994#define GV_CHIP_ID	0x4756	/* RAGE IIC, PCI */
 995#define GW_CHIP_ID	0x4757	/* RAGE IIC, AGP */
 996#define GZ_CHIP_ID	0x475a	/* RAGE IIC, AGP */
 997#define GB_CHIP_ID	0x4742	/* RAGE PRO, BGA, AGP 1x and 2x */
 998#define GD_CHIP_ID	0x4744	/* RAGE PRO, BGA, AGP 1x only */
 999#define GI_CHIP_ID	0x4749	/* RAGE PRO, BGA, PCI33 only */
1000#define GP_CHIP_ID	0x4750	/* RAGE PRO, PQFP, PCI33, full 3D */
1001#define GQ_CHIP_ID	0x4751	/* RAGE PRO, PQFP, PCI33, limited 3D */
1002
1003#define LM_CHIP_ID	0x4c4d	/* RAGE Mobility AGP, full function */
1004#define LN_CHIP_ID	0x4c4e	/* RAGE Mobility AGP */
1005#define LR_CHIP_ID	0x4c52	/* RAGE Mobility PCI, full function */
1006#define LS_CHIP_ID	0x4c53	/* RAGE Mobility PCI */
1007
1008#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
1009			(id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
1010/* Mach64 major ASIC revisions */
1011#define MACH64_ASIC_NEC_VT_A3		0x08
1012#define MACH64_ASIC_NEC_VT_A4		0x48
1013#define MACH64_ASIC_SGS_VT_A4		0x40
1014#define MACH64_ASIC_SGS_VT_B1S1		0x01
1015#define MACH64_ASIC_SGS_GT_B1S1		0x01
1016#define MACH64_ASIC_SGS_GT_B1S2		0x41
1017#define MACH64_ASIC_UMC_GT_B2U1		0x1a
1018#define MACH64_ASIC_UMC_GT_B2U2		0x5a
1019#define MACH64_ASIC_UMC_VT_B2U3		0x9a
1020#define MACH64_ASIC_UMC_GT_B2U3		0x9a
1021#define MACH64_ASIC_UMC_R3B_D_P_A1	0x1b
1022#define MACH64_ASIC_UMC_R3B_D_P_A2	0x5b
1023#define MACH64_ASIC_UMC_R3B_D_P_A3	0x1c
1024#define MACH64_ASIC_UMC_R3B_D_P_A4	0x5c
1025
1026/* Mach64 foundries */
1027#define MACH64_FND_SGS		0
1028#define MACH64_FND_NEC		1
1029#define MACH64_FND_UMC		3
1030
1031/* Mach64 chip types */
1032#define MACH64_UNKNOWN		0
1033#define MACH64_GX		1
1034#define MACH64_CX		2
1035#define MACH64_CT		3Restore
1036#define MACH64_ET		4
1037#define MACH64_VT		5
1038#define MACH64_GT		6
1039
1040/* DST_CNTL register constants */
1041#define DST_X_RIGHT_TO_LEFT	0
1042#define DST_X_LEFT_TO_RIGHT	1
1043#define DST_Y_BOTTOM_TO_TOP	0
1044#define DST_Y_TOP_TO_BOTTOM	2
1045#define DST_X_MAJOR		0
1046#define DST_Y_MAJOR		4
1047#define DST_X_TILE		8
1048#define DST_Y_TILE		0x10
1049#define DST_LAST_PEL		0x20
1050#define DST_POLYGON_ENABLE	0x40
1051#define DST_24_ROTATION_ENABLE	0x80
1052
1053/* SRC_CNTL register constants */
1054#define SRC_PATTERN_ENABLE		1
1055#define SRC_ROTATION_ENABLE		2
1056#define SRC_LINEAR_ENABLE		4
1057#define SRC_BYTE_ALIGN			8
1058#define SRC_LINE_X_RIGHT_TO_LEFT	0
1059#define SRC_LINE_X_LEFT_TO_RIGHT	0x10
1060
1061/* HOST_CNTL register constants */
1062#define HOST_BYTE_ALIGN		1
1063
1064/* GUI_TRAJ_CNTL register constants */
1065#define PAT_MONO_8x8_ENABLE	0x01000000
1066#define PAT_CLR_4x2_ENABLE	0x02000000
1067#define PAT_CLR_8x1_ENABLE	0x04000000
1068
1069/* DP_CHAIN_MASK register constants */
1070#define DP_CHAIN_4BPP		0x8888
1071#define DP_CHAIN_7BPP		0xD2D2
1072#define DP_CHAIN_8BPP		0x8080
1073#define DP_CHAIN_8BPP_RGB	0x9292
1074#define DP_CHAIN_15BPP		0x4210
1075#define DP_CHAIN_16BPP		0x8410
1076#define DP_CHAIN_24BPP		0x8080
1077#define DP_CHAIN_32BPP		0x8080
1078
1079/* DP_PIX_WIDTH register constants */
1080#define DST_1BPP		0x0
1081#define DST_4BPP		0x1
1082#define DST_8BPP		0x2
1083#define DST_15BPP		0x3
1084#define DST_16BPP		0x4
1085#define DST_24BPP		0x5
1086#define DST_32BPP		0x6
1087#define DST_MASK		0xF
1088#define SRC_1BPP		0x000
1089#define SRC_4BPP		0x100
1090#define SRC_8BPP		0x200
1091#define SRC_15BPP		0x300
1092#define SRC_16BPP		0x400
1093#define SRC_24BPP		0x500
1094#define SRC_32BPP		0x600
1095#define SRC_MASK		0xF00
1096#define DP_HOST_TRIPLE_EN	0x2000
1097#define HOST_1BPP		0x00000
1098#define HOST_4BPP		0x10000
1099#define HOST_8BPP		0x20000
1100#define HOST_15BPP		0x30000
1101#define HOST_16BPP		0x40000
1102#define HOST_24BPP		0x50000
1103#define HOST_32BPP		0x60000
1104#define HOST_MASK		0xF0000
1105#define BYTE_ORDER_MSB_TO_LSB	0
1106#define BYTE_ORDER_LSB_TO_MSB	0x1000000
1107#define BYTE_ORDER_MASK		0x1000000
1108
1109/* DP_MIX register constants */
1110#define BKGD_MIX_NOT_D			0
1111#define BKGD_MIX_ZERO			1
1112#define BKGD_MIX_ONE			2
1113#define BKGD_MIX_D			3
1114#define BKGD_MIX_NOT_S			4
1115#define BKGD_MIX_D_XOR_S		5
1116#define BKGD_MIX_NOT_D_XOR_S		6
1117#define BKGD_MIX_S			7
1118#define BKGD_MIX_NOT_D_OR_NOT_S		8
1119#define BKGD_MIX_D_OR_NOT_S		9
1120#define BKGD_MIX_NOT_D_OR_S		10
1121#define BKGD_MIX_D_OR_S			11
1122#define BKGD_MIX_D_AND_S		12
1123#define BKGD_MIX_NOT_D_AND_S		13
1124#define BKGD_MIX_D_AND_NOT_S		14
1125#define BKGD_MIX_NOT_D_AND_NOT_S	15
1126#define BKGD_MIX_D_PLUS_S_DIV2		0x17
1127#define FRGD_MIX_NOT_D			0
1128#define FRGD_MIX_ZERO			0x10000
1129#define FRGD_MIX_ONE			0x20000
1130#define FRGD_MIX_D			0x30000
1131#define FRGD_MIX_NOT_S			0x40000
1132#define FRGD_MIX_D_XOR_S		0x50000
1133#define FRGD_MIX_NOT_D_XOR_S		0x60000
1134#define FRGD_MIX_S			0x70000
1135#define FRGD_MIX_NOT_D_OR_NOT_S		0x80000
1136#define FRGD_MIX_D_OR_NOT_S		0x90000
1137#define FRGD_MIX_NOT_D_OR_S		0xa0000
1138#define FRGD_MIX_D_OR_S			0xb0000
1139#define FRGD_MIX_D_AND_S		0xc0000
1140#define FRGD_MIX_NOT_D_AND_S		0xd0000
1141#define FRGD_MIX_D_AND_NOT_S		0xe0000
1142#define FRGD_MIX_NOT_D_AND_NOT_S	0xf0000
1143#define FRGD_MIX_D_PLUS_S_DIV2		0x170000
1144
1145/* DP_SRC register constants */
1146#define BKGD_SRC_BKGD_CLR	0
1147#define BKGD_SRC_FRGD_CLR	1
1148#define BKGD_SRC_HOST		2
1149#define BKGD_SRC_BLIT		3
1150#define BKGD_SRC_PATTERN	4
1151#define FRGD_SRC_BKGD_CLR	0
1152#define FRGD_SRC_FRGD_CLR	0x100
1153#define FRGD_SRC_HOST		0x200
1154#define FRGD_SRC_BLIT		0x300
1155#define FRGD_SRC_PATTERN	0x400
1156#define MONO_SRC_ONE		0
1157#define MONO_SRC_PATTERN	0x10000
1158#define MONO_SRC_HOST		0x20000
1159#define MONO_SRC_BLIT		0x30000
1160
1161/* CLR_CMP_CNTL register constants */
1162#define COMPARE_FALSE		0
1163#define COMPARE_TRUE		1
1164#define COMPARE_NOT_EQUAL	4
1165#define COMPARE_EQUAL		5
1166#define COMPARE_DESTINATION	0
1167#define COMPARE_SOURCE		0x1000000
1168
1169/* FIFO_STAT register constants */
1170#define FIFO_ERR		0x80000000
1171
1172/* CONTEXT_LOAD_CNTL constants */
1173#define CONTEXT_NO_LOAD			0
1174#define CONTEXT_LOAD			0x10000
1175#define CONTEXT_LOAD_AND_DO_FILL	0x20000
1176#define CONTEXT_LOAD_AND_DO_LINE	0x30000
1177#define CONTEXT_EXECUTE			0
1178#define CONTEXT_CMD_DISABLE		0x80000000
1179
1180/* GUI_STAT register constants */
1181#define ENGINE_IDLE			0
1182#define ENGINE_BUSY			1
1183#define SCISSOR_LEFT_FLAG		0x10
1184#define SCISSOR_RIGHT_FLAG		0x20
1185#define SCISSOR_TOP_FLAG		0x40
1186#define SCISSOR_BOTTOM_FLAG		0x80
1187
1188/* ATI VGA Extended Regsiters */
1189#define sioATIEXT		0x1ce
1190#define bioATIEXT		0x3ce
1191
1192#define ATI2E			0xae
1193#define ATI32			0xb2
1194#define ATI36			0xb6
1195
1196/* VGA Graphics Controller Registers */
1197#define R_GENMO			0x3cc
1198#define VGAGRA			0x3ce
1199#define GRA06			0x06
1200
1201/* VGA Seququencer Registers */
1202#define VGASEQ			0x3c4
1203#define SEQ02			0x02
1204#define SEQ04			0x04
1205
1206#define MACH64_MAX_X		ENGINE_MAX_X
1207#define MACH64_MAX_Y		ENGINE_MAX_Y
1208
1209#define INC_X			0x0020
1210#define INC_Y			0x0080
1211
1212#define RGB16_555		0x0000
1213#define RGB16_565		0x0040
1214#define RGB16_655		0x0080
1215#define RGB16_664		0x00c0
1216
1217#define POLY_TEXT_TYPE		0x0001
1218#define IMAGE_TEXT_TYPE		0x0002
1219#define TEXT_TYPE_8_BIT		0x0004
1220#define TEXT_TYPE_16_BIT	0x0008
1221#define POLY_TEXT_TYPE_8	(POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
1222#define IMAGE_TEXT_TYPE_8	(IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
1223#define POLY_TEXT_TYPE_16	(POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
1224#define IMAGE_TEXT_TYPE_16	(IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
1225
1226#define MACH64_NUM_CLOCKS	16
1227#define MACH64_NUM_FREQS	50
1228
1229/* Power Management register constants (LT & LT Pro) */
1230#define PWR_MGT_ON		0x00000001
1231#define PWR_MGT_MODE_MASK	0x00000006
1232#define AUTO_PWR_UP		0x00000008
1233#define USE_F32KHZ		0x00000400
1234#define TRISTATE_MEM_EN		0x00000800
1235#define SELF_REFRESH		0x00000080
1236#define PWR_BLON		0x02000000
1237#define STANDBY_NOW		0x10000000
1238#define SUSPEND_NOW		0x20000000
1239#define PWR_MGT_STATUS_MASK	0xC0000000
1240#define PWR_MGT_STATUS_SUSPEND	0x80000000
1241
1242/* PM Mode constants  */
1243#define PWR_MGT_MODE_PIN	0x00000000
1244#define PWR_MGT_MODE_REG	0x00000002
1245#define PWR_MGT_MODE_TIMER	0x00000004
1246#define PWR_MGT_MODE_PCI	0x00000006
1247
1248/* LCD registers (LT Pro) */
1249
1250/* LCD Index register */
1251#define LCD_INDEX_MASK		0x0000003F
1252#define LCD_DISPLAY_DIS		0x00000100
1253#define LCD_SRC_SEL		0x00000200
1254#define CRTC2_DISPLAY_DIS	0x00000400
1255
1256/* LCD register indices */
1257#define CNFG_PANEL		0x00
1258#define LCD_GEN_CNTL		0x01
1259#define DSTN_CONTROL		0x02
1260#define HFB_PITCH_ADDR		0x03
1261#define HORZ_STRETCHING		0x04
1262#define VERT_STRETCHING		0x05
1263#define EXT_VERT_STRETCH	0x06
1264#define LT_GIO			0x07
1265#define POWER_MANAGEMENT	0x08
1266#define ZVGPIO			0x09
1267#define ICON_CLR0		0x0A
1268#define ICON_CLR1		0x0B
1269#define ICON_OFFSET		0x0C
1270#define ICON_HORZ_VERT_POSN	0x0D
1271#define ICON_HORZ_VERT_OFF	0x0E
1272#define ICON2_CLR0		0x0F
1273#define ICON2_CLR1		0x10
1274#define ICON2_OFFSET		0x11
1275#define ICON2_HORZ_VERT_POSN	0x12
1276#define ICON2_HORZ_VERT_OFF	0x13
1277#define LCD_MISC_CNTL		0x14
1278#define APC_CNTL		0x1C
1279#define POWER_MANAGEMENT_2	0x1D
1280#define ALPHA_BLENDING		0x25
1281#define PORTRAIT_GEN_CNTL	0x26
1282#define APC_CTRL_IO		0x27
1283#define TEST_IO			0x28
1284#define TEST_OUTPUTS		0x29
1285#define DP1_MEM_ACCESS		0x2A
1286#define DP0_MEM_ACCESS		0x2B
1287#define DP0_DEBUG_A		0x2C
1288#define DP0_DEBUG_B		0x2D
1289#define DP1_DEBUG_A		0x2E
1290#define DP1_DEBUG_B		0x2F
1291#define DPCTRL_DEBUG_A		0x30
1292#define DPCTRL_DEBUG_B		0x31
1293#define MEMBLK_DEBUG		0x32
1294#define APC_LUT_AB		0x33
1295#define APC_LUT_CD		0x34
1296#define APC_LUT_EF		0x35
1297#define APC_LUT_GH		0x36
1298#define APC_LUT_IJ		0x37
1299#define APC_LUT_KL		0x38
1300#define APC_LUT_MN		0x39
1301#define APC_LUT_OP		0x3A
1302
1303/* Values in LCD_GEN_CTRL */
1304#define CRT_ON                          0x00000001ul
1305#define LCD_ON                          0x00000002ul
1306#define HORZ_DIVBY2_EN                  0x00000004ul
1307#define DONT_DS_ICON                    0x00000008ul
1308#define LOCK_8DOT                       0x00000010ul
1309#define ICON_ENABLE                     0x00000020ul
1310#define DONT_SHADOW_VPAR                0x00000040ul
1311#define V2CLK_PM_EN                     0x00000080ul
1312#define RST_FM                          0x00000100ul
1313#define DISABLE_PCLK_RESET              0x00000200ul	/* XC/XL */
1314#define DIS_HOR_CRT_DIVBY2              0x00000400ul
1315#define SCLK_SEL                        0x00000800ul
1316#define SCLK_DELAY                      0x0000f000ul
1317#define TVCLK_PM_EN                     0x00010000ul
1318#define VCLK_DAC_PM_EN                  0x00020000ul
1319#define VCLK_LCD_OFF                    0x00040000ul
1320#define SELECT_WAIT_4MS                 0x00080000ul
1321#define XTALIN_PM_EN                    0x00080000ul	/* XC/XL */
1322#define V2CLK_DAC_PM_EN                 0x00100000ul
1323#define LVDS_EN                         0x00200000ul
1324#define LVDS_PLL_EN                     0x00400000ul
1325#define LVDS_PLL_RESET                  0x00800000ul
1326#define LVDS_RESERVED_BITS              0x07000000ul
1327#define CRTC_RW_SELECT                  0x08000000ul	/* LTPro */
1328#define USE_SHADOWED_VEND               0x10000000ul
1329#define USE_SHADOWED_ROWCUR             0x20000000ul
1330#define SHADOW_EN                       0x40000000ul
1331#define SHADOW_RW_EN                  	0x80000000ul
1332
1333#define LCD_SET_PRIMARY_MASK            0x07FFFBFBul
1334
1335/* Values in HORZ_STRETCHING */
1336#define HORZ_STRETCH_BLEND		0x00000ffful
1337#define HORZ_STRETCH_RATIO		0x0000fffful
1338#define HORZ_STRETCH_LOOP		0x00070000ul
1339#define HORZ_STRETCH_LOOP09		0x00000000ul
1340#define HORZ_STRETCH_LOOP11		0x00010000ul
1341#define HORZ_STRETCH_LOOP12		0x00020000ul
1342#define HORZ_STRETCH_LOOP14		0x00030000ul
1343#define HORZ_STRETCH_LOOP15		0x00040000ul
1344/*	?				0x00050000ul */
1345/*	?				0x00060000ul */
1346/*	?				0x00070000ul */
1347/*	?				0x00080000ul */
1348#define HORZ_PANEL_SIZE			0x0ff00000ul	/* XC/XL */
1349/*	?				0x10000000ul */
1350#define AUTO_HORZ_RATIO			0x20000000ul	/* XC/XL */
1351#define HORZ_STRETCH_MODE		0x40000000ul
1352#define HORZ_STRETCH_EN			0x80000000ul
1353
1354/* Values in VERT_STRETCHING */
1355#define VERT_STRETCH_RATIO0		0x000003fful
1356#define VERT_STRETCH_RATIO1		0x000ffc00ul
1357#define VERT_STRETCH_RATIO2		0x3ff00000ul
1358#define VERT_STRETCH_USE0		0x40000000ul
1359#define VERT_STRETCH_EN			0x80000000ul
1360
1361/* Values in EXT_VERT_STRETCH */
1362#define VERT_STRETCH_RATIO3		0x000003fful
1363#define FORCE_DAC_DATA			0x000000fful
1364#define FORCE_DAC_DATA_SEL		0x00000300ul
1365#define VERT_STRETCH_MODE		0x00000400ul
1366#define VERT_PANEL_SIZE			0x003ff800ul
1367#define AUTO_VERT_RATIO			0x00400000ul
1368#define USE_AUTO_FP_POS			0x00800000ul
1369#define USE_AUTO_LCD_VSYNC		0x01000000ul
1370/*	?				0xfe000000ul */
1371
1372/* Values in LCD_MISC_CNTL */
1373#define BIAS_MOD_LEVEL_MASK		0x0000ff00
1374#define BIAS_MOD_LEVEL_SHIFT		8
1375#define BLMOD_EN			0x00010000
1376#define BIASMOD_EN			0x00020000
1377
1378#endif				/* REGMACH64_H */