1/*
  2 * Copyright (C) 2015, 2016 ARM Ltd.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 *
 13 * You should have received a copy of the GNU General Public License
 14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15 */
 16#ifndef __KVM_ARM_VGIC_H
 17#define __KVM_ARM_VGIC_H
 18
 19#include <linux/kernel.h>
 20#include <linux/kvm.h>
 21#include <linux/irqreturn.h>
 22#include <linux/spinlock.h>
 23#include <linux/static_key.h>
 24#include <linux/types.h>
 25#include <kvm/iodev.h>
 26#include <linux/list.h>
 27#include <linux/jump_label.h>
 28
 29#define VGIC_V3_MAX_CPUS	255
 30#define VGIC_V2_MAX_CPUS	8
 31#define VGIC_NR_IRQS_LEGACY     256
 32#define VGIC_NR_SGIS		16
 33#define VGIC_NR_PPIS		16
 34#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
 35#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
 36#define VGIC_MAX_SPI		1019
 37#define VGIC_MAX_RESERVED	1023
 38#define VGIC_MIN_LPI		8192
 39#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)
 40
 41enum vgic_type {
 42	VGIC_V2,		/* Good ol' GICv2 */
 43	VGIC_V3,		/* New fancy GICv3 */
 44};
 45
 46/* same for all guests, as depending only on the _host's_ GIC model */
 47struct vgic_global {
 48	/* type of the host GIC */
 49	enum vgic_type		type;
 50
 51	/* Physical address of vgic virtual cpu interface */
 52	phys_addr_t		vcpu_base;
 53
 54	/* GICV mapping */
 55	void __iomem		*vcpu_base_va;
 56
 57	/* virtual control interface mapping */
 58	void __iomem		*vctrl_base;
 59
 60	/* Number of implemented list registers */
 61	int			nr_lr;
 62
 63	/* Maintenance IRQ number */
 64	unsigned int		maint_irq;
 65
 66	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
 67	int			max_gic_vcpus;
 68
 69	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
 70	bool			can_emulate_gicv2;
 71
 72	/* GIC system register CPU interface */
 73	struct static_key_false gicv3_cpuif;
 74};
 75
 76extern struct vgic_global kvm_vgic_global_state;
 77
 78#define VGIC_V2_MAX_LRS		(1 << 6)
 79#define VGIC_V3_MAX_LRS		16
 80#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)
 81
 82enum vgic_irq_config {
 83	VGIC_CONFIG_EDGE = 0,
 84	VGIC_CONFIG_LEVEL
 85};
 86
 87struct vgic_irq {
 88	spinlock_t irq_lock;		/* Protects the content of the struct */
 89	struct list_head lpi_list;	/* Used to link all LPIs together */
 90	struct list_head ap_list;
 91
 92	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
 93					 * SPIs and LPIs: The VCPU whose ap_list
 94					 * this is queued on.
 95					 */
 96
 97	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
 98					 * be sent to, as a result of the
 99					 * targets reg (v2) or the
100					 * affinity reg (v3).
101					 */
102
103	u32 intid;			/* Guest visible INTID */
104	bool pending;
105	bool line_level;		/* Level only */
106	bool soft_pending;		/* Level only */
107	bool active;			/* not used for LPIs */
108	bool enabled;
109	bool hw;			/* Tied to HW IRQ */
110	struct kref refcount;		/* Used for LPIs */
111	u32 hwintid;			/* HW INTID number */
112	union {
113		u8 targets;			/* GICv2 target VCPUs mask */
114		u32 mpidr;			/* GICv3 target VCPU */
115	};
116	u8 source;			/* GICv2 SGIs only */
117	u8 priority;
118	enum vgic_irq_config config;	/* Level or edge */
119};
120
121struct vgic_register_region;
122struct vgic_its;
123
124enum iodev_type {
125	IODEV_CPUIF,
126	IODEV_DIST,
127	IODEV_REDIST,
128	IODEV_ITS
129};
130
131struct vgic_io_device {
132	gpa_t base_addr;
133	union {
134		struct kvm_vcpu *redist_vcpu;
135		struct vgic_its *its;
136	};
137	const struct vgic_register_region *regions;
138	enum iodev_type iodev_type;
139	int nr_regions;
140	struct kvm_io_device dev;
141};
142
143struct vgic_its {
144	/* The base address of the ITS control register frame */
145	gpa_t			vgic_its_base;
146
147	bool			enabled;
148	bool			initialized;
149	struct vgic_io_device	iodev;
150	struct kvm_device	*dev;
151
152	/* These registers correspond to GITS_BASER{0,1} */
153	u64			baser_device_table;
154	u64			baser_coll_table;
155
156	/* Protects the command queue */
157	struct mutex		cmd_lock;
158	u64			cbaser;
159	u32			creadr;
160	u32			cwriter;
161
162	/* Protects the device and collection lists */
163	struct mutex		its_lock;
164	struct list_head	device_list;
165	struct list_head	collection_list;
166};
167
168struct vgic_dist {
169	bool			in_kernel;
170	bool			ready;
171	bool			initialized;
172
173	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
174	u32			vgic_model;
175
176	/* Do injected MSIs require an additional device ID? */
177	bool			msis_require_devid;
178
179	int			nr_spis;
180
181	/* TODO: Consider moving to global state */
182	/* Virtual control interface mapping */
183	void __iomem		*vctrl_base;
184
185	/* base addresses in guest physical address space: */
186	gpa_t			vgic_dist_base;		/* distributor */
187	union {
188		/* either a GICv2 CPU interface */
189		gpa_t			vgic_cpu_base;
190		/* or a number of GICv3 redistributor regions */
191		gpa_t			vgic_redist_base;
192	};
193
194	/* distributor enabled */
195	bool			enabled;
196
197	struct vgic_irq		*spis;
198
199	struct vgic_io_device	dist_iodev;
200
201	bool			has_its;
202
203	/*
204	 * Contains the attributes and gpa of the LPI configuration table.
205	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
206	 * one address across all redistributors.
207	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
208	 */
209	u64			propbaser;
210
211	/* Protects the lpi_list and the count value below. */
212	spinlock_t		lpi_list_lock;
213	struct list_head	lpi_list_head;
214	int			lpi_list_count;
215};
216
217struct vgic_v2_cpu_if {
218	u32		vgic_hcr;
219	u32		vgic_vmcr;
220	u32		vgic_misr;	/* Saved only */
221	u64		vgic_eisr;	/* Saved only */
222	u64		vgic_elrsr;	/* Saved only */
223	u32		vgic_apr;
224	u32		vgic_lr[VGIC_V2_MAX_LRS];
225};
226
227struct vgic_v3_cpu_if {
228	u32		vgic_hcr;
229	u32		vgic_vmcr;
230	u32		vgic_sre;	/* Restored only, change ignored */
231	u32		vgic_misr;	/* Saved only */
232	u32		vgic_eisr;	/* Saved only */
233	u32		vgic_elrsr;	/* Saved only */
234	u32		vgic_ap0r[4];
235	u32		vgic_ap1r[4];
236	u64		vgic_lr[VGIC_V3_MAX_LRS];
237};
238
239struct vgic_cpu {
240	/* CPU vif control registers for world switch */
241	union {
242		struct vgic_v2_cpu_if	vgic_v2;
243		struct vgic_v3_cpu_if	vgic_v3;
244	};
245
246	unsigned int used_lrs;
247	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
248
249	spinlock_t ap_list_lock;	/* Protects the ap_list */
250
251	/*
252	 * List of IRQs that this VCPU should consider because they are either
253	 * Active or Pending (hence the name; AP list), or because they recently
254	 * were one of the two and need to be migrated off this list to another
255	 * VCPU.
256	 */
257	struct list_head ap_list_head;
258
259	u64 live_lrs;
260
261	/*
262	 * Members below are used with GICv3 emulation only and represent
263	 * parts of the redistributor.
264	 */
265	struct vgic_io_device	rd_iodev;
266	struct vgic_io_device	sgi_iodev;
267
268	/* Contains the attributes and gpa of the LPI pending tables. */
269	u64 pendbaser;
270
271	bool lpis_enabled;
272};
273
274extern struct static_key_false vgic_v2_cpuif_trap;
275
276int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
277void kvm_vgic_early_init(struct kvm *kvm);
278int kvm_vgic_create(struct kvm *kvm, u32 type);
279void kvm_vgic_destroy(struct kvm *kvm);
280void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
281void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
282int kvm_vgic_map_resources(struct kvm *kvm);
283int kvm_vgic_hyp_init(void);
284
285int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
286			bool level);
287int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
288			       bool level);
289int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
290int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
291bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
292
293int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
294
295#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
296#define vgic_initialized(k)	((k)->arch.vgic.initialized)
297#define vgic_ready(k)		((k)->arch.vgic.ready)
298#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
299			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
300
301bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
302void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
303void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
304
305void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
306
307/**
308 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
309 *
310 * The host's GIC naturally limits the maximum amount of VCPUs a guest
311 * can use.
312 */
313static inline int kvm_vgic_get_max_vcpus(void)
314{
315	return kvm_vgic_global_state.max_gic_vcpus;
316}
317
318int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
319
320/**
321 * kvm_vgic_setup_default_irq_routing:
322 * Setup a default flat gsi routing table mapping all SPIs
323 */
324int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
325
326#endif /* __KVM_ARM_VGIC_H */