Loading...
1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/platform_device.h>
21#include <linux/platform_data/tegra_usb.h>
22#include <linux/irq.h>
23#include <linux/usb/otg.h>
24#include <mach/usb_phy.h>
25
26#define TEGRA_USB_DMA_ALIGN 32
27
28struct tegra_ehci_hcd {
29 struct ehci_hcd *ehci;
30 struct tegra_usb_phy *phy;
31 struct clk *clk;
32 struct clk *emc_clk;
33 struct otg_transceiver *transceiver;
34 int host_resumed;
35 int bus_suspended;
36 int port_resuming;
37 int power_down_on_bus_suspend;
38 enum tegra_usb_phy_port_speed port_speed;
39};
40
41static void tegra_ehci_power_up(struct usb_hcd *hcd)
42{
43 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
44
45 clk_enable(tegra->emc_clk);
46 clk_enable(tegra->clk);
47 tegra_usb_phy_power_on(tegra->phy);
48 tegra->host_resumed = 1;
49}
50
51static void tegra_ehci_power_down(struct usb_hcd *hcd)
52{
53 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
54
55 tegra->host_resumed = 0;
56 tegra_usb_phy_power_off(tegra->phy);
57 clk_disable(tegra->clk);
58 clk_disable(tegra->emc_clk);
59}
60
61static int tegra_ehci_internal_port_reset(
62 struct ehci_hcd *ehci,
63 u32 __iomem *portsc_reg
64)
65{
66 u32 temp;
67 unsigned long flags;
68 int retval = 0;
69 int i, tries;
70 u32 saved_usbintr;
71
72 spin_lock_irqsave(&ehci->lock, flags);
73 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
74 /* disable USB interrupt */
75 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
76 spin_unlock_irqrestore(&ehci->lock, flags);
77
78 /*
79 * Here we have to do Port Reset at most twice for
80 * Port Enable bit to be set.
81 */
82 for (i = 0; i < 2; i++) {
83 temp = ehci_readl(ehci, portsc_reg);
84 temp |= PORT_RESET;
85 ehci_writel(ehci, temp, portsc_reg);
86 mdelay(10);
87 temp &= ~PORT_RESET;
88 ehci_writel(ehci, temp, portsc_reg);
89 mdelay(1);
90 tries = 100;
91 do {
92 mdelay(1);
93 /*
94 * Up to this point, Port Enable bit is
95 * expected to be set after 2 ms waiting.
96 * USB1 usually takes extra 45 ms, for safety,
97 * we take 100 ms as timeout.
98 */
99 temp = ehci_readl(ehci, portsc_reg);
100 } while (!(temp & PORT_PE) && tries--);
101 if (temp & PORT_PE)
102 break;
103 }
104 if (i == 2)
105 retval = -ETIMEDOUT;
106
107 /*
108 * Clear Connect Status Change bit if it's set.
109 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
110 */
111 if (temp & PORT_CSC)
112 ehci_writel(ehci, PORT_CSC, portsc_reg);
113
114 /*
115 * Write to clear any interrupt status bits that might be set
116 * during port reset.
117 */
118 temp = ehci_readl(ehci, &ehci->regs->status);
119 ehci_writel(ehci, temp, &ehci->regs->status);
120
121 /* restore original interrupt enable bits */
122 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
123 return retval;
124}
125
126static int tegra_ehci_hub_control(
127 struct usb_hcd *hcd,
128 u16 typeReq,
129 u16 wValue,
130 u16 wIndex,
131 char *buf,
132 u16 wLength
133)
134{
135 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
136 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
137 u32 __iomem *status_reg;
138 u32 temp;
139 unsigned long flags;
140 int retval = 0;
141
142 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
143
144 spin_lock_irqsave(&ehci->lock, flags);
145
146 /*
147 * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
148 * that are write on clear, by writing back the register read value, so
149 * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
150 */
151 if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
152 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
153 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
154 goto done;
155 }
156
157 else if (typeReq == GetPortStatus) {
158 temp = ehci_readl(ehci, status_reg);
159 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
160 /* Resume completed, re-enable disconnect detection */
161 tegra->port_resuming = 0;
162 tegra_usb_phy_postresume(tegra->phy);
163 }
164 }
165
166 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
167 temp = ehci_readl(ehci, status_reg);
168 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
169 retval = -EPIPE;
170 goto done;
171 }
172
173 temp &= ~PORT_WKCONN_E;
174 temp |= PORT_WKDISC_E | PORT_WKOC_E;
175 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
176
177 /*
178 * If a transaction is in progress, there may be a delay in
179 * suspending the port. Poll until the port is suspended.
180 */
181 if (handshake(ehci, status_reg, PORT_SUSPEND,
182 PORT_SUSPEND, 5000))
183 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
184
185 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
186 goto done;
187 }
188
189 /* For USB1 port we need to issue Port Reset twice internally */
190 if (tegra->phy->instance == 0 &&
191 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
192 spin_unlock_irqrestore(&ehci->lock, flags);
193 return tegra_ehci_internal_port_reset(ehci, status_reg);
194 }
195
196 /*
197 * Tegra host controller will time the resume operation to clear the bit
198 * when the port control state switches to HS or FS Idle. This behavior
199 * is different from EHCI where the host controller driver is required
200 * to set this bit to a zero after the resume duration is timed in the
201 * driver.
202 */
203 else if (typeReq == ClearPortFeature &&
204 wValue == USB_PORT_FEAT_SUSPEND) {
205 temp = ehci_readl(ehci, status_reg);
206 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
207 retval = -EPIPE;
208 goto done;
209 }
210
211 if (!(temp & PORT_SUSPEND))
212 goto done;
213
214 /* Disable disconnect detection during port resume */
215 tegra_usb_phy_preresume(tegra->phy);
216
217 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
218
219 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
220 /* start resume signalling */
221 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
222
223 spin_unlock_irqrestore(&ehci->lock, flags);
224 msleep(20);
225 spin_lock_irqsave(&ehci->lock, flags);
226
227 /* Poll until the controller clears RESUME and SUSPEND */
228 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
229 pr_err("%s: timeout waiting for RESUME\n", __func__);
230 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
231 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
232
233 ehci->reset_done[wIndex-1] = 0;
234
235 tegra->port_resuming = 1;
236 goto done;
237 }
238
239 spin_unlock_irqrestore(&ehci->lock, flags);
240
241 /* Handle the hub control events here */
242 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
243done:
244 spin_unlock_irqrestore(&ehci->lock, flags);
245 return retval;
246}
247
248static void tegra_ehci_restart(struct usb_hcd *hcd)
249{
250 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
251
252 ehci_reset(ehci);
253
254 /* setup the frame list and Async q heads */
255 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
256 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
257 /* setup the command register and set the controller in RUN mode */
258 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
259 ehci->command |= CMD_RUN;
260 ehci_writel(ehci, ehci->command, &ehci->regs->command);
261
262 down_write(&ehci_cf_port_reset_rwsem);
263 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
264 /* flush posted writes */
265 ehci_readl(ehci, &ehci->regs->command);
266 up_write(&ehci_cf_port_reset_rwsem);
267}
268
269static int tegra_usb_suspend(struct usb_hcd *hcd)
270{
271 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
272 struct ehci_regs __iomem *hw = tegra->ehci->regs;
273 unsigned long flags;
274
275 spin_lock_irqsave(&tegra->ehci->lock, flags);
276
277 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
278 ehci_halt(tegra->ehci);
279 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
280
281 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
282
283 tegra_ehci_power_down(hcd);
284 return 0;
285}
286
287static int tegra_usb_resume(struct usb_hcd *hcd)
288{
289 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
290 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
291 struct ehci_regs __iomem *hw = ehci->regs;
292 unsigned long val;
293
294 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
295 tegra_ehci_power_up(hcd);
296
297 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
298 /* Wait for the phy to detect new devices
299 * before we restart the controller */
300 msleep(10);
301 goto restart;
302 }
303
304 /* Force the phy to keep data lines in suspend state */
305 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
306
307 /* Enable host mode */
308 tdi_reset(ehci);
309
310 /* Enable Port Power */
311 val = readl(&hw->port_status[0]);
312 val |= PORT_POWER;
313 writel(val, &hw->port_status[0]);
314 udelay(10);
315
316 /* Check if the phy resume from LP0. When the phy resume from LP0
317 * USB register will be reset. */
318 if (!readl(&hw->async_next)) {
319 /* Program the field PTC based on the saved speed mode */
320 val = readl(&hw->port_status[0]);
321 val &= ~PORT_TEST(~0);
322 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
323 val |= PORT_TEST_FORCE;
324 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
325 val |= PORT_TEST(6);
326 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
327 val |= PORT_TEST(7);
328 writel(val, &hw->port_status[0]);
329 udelay(10);
330
331 /* Disable test mode by setting PTC field to NORMAL_OP */
332 val = readl(&hw->port_status[0]);
333 val &= ~PORT_TEST(~0);
334 writel(val, &hw->port_status[0]);
335 udelay(10);
336 }
337
338 /* Poll until CCS is enabled */
339 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
340 PORT_CONNECT, 2000)) {
341 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
342 goto restart;
343 }
344
345 /* Poll until PE is enabled */
346 if (handshake(ehci, &hw->port_status[0], PORT_PE,
347 PORT_PE, 2000)) {
348 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
349 goto restart;
350 }
351
352 /* Clear the PCI status, to avoid an interrupt taken upon resume */
353 val = readl(&hw->status);
354 val |= STS_PCD;
355 writel(val, &hw->status);
356
357 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
358 val = readl(&hw->port_status[0]);
359 if ((val & PORT_POWER) && (val & PORT_PE)) {
360 val |= PORT_SUSPEND;
361 writel(val, &hw->port_status[0]);
362
363 /* Wait until port suspend completes */
364 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
365 PORT_SUSPEND, 1000)) {
366 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
367 __func__);
368 goto restart;
369 }
370 }
371
372 tegra_ehci_phy_restore_end(tegra->phy);
373 return 0;
374
375restart:
376 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
377 tegra_ehci_phy_restore_end(tegra->phy);
378
379 tegra_ehci_restart(hcd);
380 return 0;
381}
382
383static void tegra_ehci_shutdown(struct usb_hcd *hcd)
384{
385 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
386
387 /* ehci_shutdown touches the USB controller registers, make sure
388 * controller has clocks to it */
389 if (!tegra->host_resumed)
390 tegra_ehci_power_up(hcd);
391
392 ehci_shutdown(hcd);
393}
394
395static int tegra_ehci_setup(struct usb_hcd *hcd)
396{
397 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
398 int retval;
399
400 /* EHCI registers start at offset 0x100 */
401 ehci->caps = hcd->regs + 0x100;
402 ehci->regs = hcd->regs + 0x100 +
403 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
404
405 dbg_hcs_params(ehci, "reset");
406 dbg_hcc_params(ehci, "reset");
407
408 /* cache this readonly data; minimize chip reads */
409 ehci->hcs_params = readl(&ehci->caps->hcs_params);
410
411 /* switch to host mode */
412 hcd->has_tt = 1;
413 ehci_reset(ehci);
414
415 retval = ehci_halt(ehci);
416 if (retval)
417 return retval;
418
419 /* data structure init */
420 retval = ehci_init(hcd);
421 if (retval)
422 return retval;
423
424 ehci->sbrn = 0x20;
425
426 ehci_port_power(ehci, 1);
427 return retval;
428}
429
430#ifdef CONFIG_PM
431static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
432{
433 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
434 int error_status = 0;
435
436 error_status = ehci_bus_suspend(hcd);
437 if (!error_status && tegra->power_down_on_bus_suspend) {
438 tegra_usb_suspend(hcd);
439 tegra->bus_suspended = 1;
440 }
441
442 return error_status;
443}
444
445static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
446{
447 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
448
449 if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
450 tegra_usb_resume(hcd);
451 tegra->bus_suspended = 0;
452 }
453
454 tegra_usb_phy_preresume(tegra->phy);
455 tegra->port_resuming = 1;
456 return ehci_bus_resume(hcd);
457}
458#endif
459
460struct temp_buffer {
461 void *kmalloc_ptr;
462 void *old_xfer_buffer;
463 u8 data[0];
464};
465
466static void free_temp_buffer(struct urb *urb)
467{
468 enum dma_data_direction dir;
469 struct temp_buffer *temp;
470
471 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
472 return;
473
474 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
475
476 temp = container_of(urb->transfer_buffer, struct temp_buffer,
477 data);
478
479 if (dir == DMA_FROM_DEVICE)
480 memcpy(temp->old_xfer_buffer, temp->data,
481 urb->transfer_buffer_length);
482 urb->transfer_buffer = temp->old_xfer_buffer;
483 kfree(temp->kmalloc_ptr);
484
485 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
486}
487
488static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
489{
490 enum dma_data_direction dir;
491 struct temp_buffer *temp, *kmalloc_ptr;
492 size_t kmalloc_size;
493
494 if (urb->num_sgs || urb->sg ||
495 urb->transfer_buffer_length == 0 ||
496 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
497 return 0;
498
499 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
500
501 /* Allocate a buffer with enough padding for alignment */
502 kmalloc_size = urb->transfer_buffer_length +
503 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
504
505 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
506 if (!kmalloc_ptr)
507 return -ENOMEM;
508
509 /* Position our struct temp_buffer such that data is aligned */
510 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
511
512 temp->kmalloc_ptr = kmalloc_ptr;
513 temp->old_xfer_buffer = urb->transfer_buffer;
514 if (dir == DMA_TO_DEVICE)
515 memcpy(temp->data, urb->transfer_buffer,
516 urb->transfer_buffer_length);
517 urb->transfer_buffer = temp->data;
518
519 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
520
521 return 0;
522}
523
524static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
525 gfp_t mem_flags)
526{
527 int ret;
528
529 ret = alloc_temp_buffer(urb, mem_flags);
530 if (ret)
531 return ret;
532
533 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
534 if (ret)
535 free_temp_buffer(urb);
536
537 return ret;
538}
539
540static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
541{
542 usb_hcd_unmap_urb_for_dma(hcd, urb);
543 free_temp_buffer(urb);
544}
545
546static const struct hc_driver tegra_ehci_hc_driver = {
547 .description = hcd_name,
548 .product_desc = "Tegra EHCI Host Controller",
549 .hcd_priv_size = sizeof(struct ehci_hcd),
550
551 .flags = HCD_USB2 | HCD_MEMORY,
552
553 .reset = tegra_ehci_setup,
554 .irq = ehci_irq,
555
556 .start = ehci_run,
557 .stop = ehci_stop,
558 .shutdown = tegra_ehci_shutdown,
559 .urb_enqueue = ehci_urb_enqueue,
560 .urb_dequeue = ehci_urb_dequeue,
561 .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
562 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
563 .endpoint_disable = ehci_endpoint_disable,
564 .endpoint_reset = ehci_endpoint_reset,
565 .get_frame_number = ehci_get_frame,
566 .hub_status_data = ehci_hub_status_data,
567 .hub_control = tegra_ehci_hub_control,
568 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
569#ifdef CONFIG_PM
570 .bus_suspend = tegra_ehci_bus_suspend,
571 .bus_resume = tegra_ehci_bus_resume,
572#endif
573 .relinquish_port = ehci_relinquish_port,
574 .port_handed_over = ehci_port_handed_over,
575};
576
577static int tegra_ehci_probe(struct platform_device *pdev)
578{
579 struct resource *res;
580 struct usb_hcd *hcd;
581 struct tegra_ehci_hcd *tegra;
582 struct tegra_ehci_platform_data *pdata;
583 int err = 0;
584 int irq;
585 int instance = pdev->id;
586
587 pdata = pdev->dev.platform_data;
588 if (!pdata) {
589 dev_err(&pdev->dev, "Platform data missing\n");
590 return -EINVAL;
591 }
592
593 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
594 if (!tegra)
595 return -ENOMEM;
596
597 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
598 dev_name(&pdev->dev));
599 if (!hcd) {
600 dev_err(&pdev->dev, "Unable to create HCD\n");
601 err = -ENOMEM;
602 goto fail_hcd;
603 }
604
605 platform_set_drvdata(pdev, tegra);
606
607 tegra->clk = clk_get(&pdev->dev, NULL);
608 if (IS_ERR(tegra->clk)) {
609 dev_err(&pdev->dev, "Can't get ehci clock\n");
610 err = PTR_ERR(tegra->clk);
611 goto fail_clk;
612 }
613
614 err = clk_enable(tegra->clk);
615 if (err)
616 goto fail_clken;
617
618 tegra->emc_clk = clk_get(&pdev->dev, "emc");
619 if (IS_ERR(tegra->emc_clk)) {
620 dev_err(&pdev->dev, "Can't get emc clock\n");
621 err = PTR_ERR(tegra->emc_clk);
622 goto fail_emc_clk;
623 }
624
625 clk_enable(tegra->emc_clk);
626 clk_set_rate(tegra->emc_clk, 400000000);
627
628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
629 if (!res) {
630 dev_err(&pdev->dev, "Failed to get I/O memory\n");
631 err = -ENXIO;
632 goto fail_io;
633 }
634 hcd->rsrc_start = res->start;
635 hcd->rsrc_len = resource_size(res);
636 hcd->regs = ioremap(res->start, resource_size(res));
637 if (!hcd->regs) {
638 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
639 err = -ENOMEM;
640 goto fail_io;
641 }
642
643 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
644 TEGRA_USB_PHY_MODE_HOST);
645 if (IS_ERR(tegra->phy)) {
646 dev_err(&pdev->dev, "Failed to open USB phy\n");
647 err = -ENXIO;
648 goto fail_phy;
649 }
650
651 err = tegra_usb_phy_power_on(tegra->phy);
652 if (err) {
653 dev_err(&pdev->dev, "Failed to power on the phy\n");
654 goto fail;
655 }
656
657 tegra->host_resumed = 1;
658 tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
659 tegra->ehci = hcd_to_ehci(hcd);
660
661 irq = platform_get_irq(pdev, 0);
662 if (!irq) {
663 dev_err(&pdev->dev, "Failed to get IRQ\n");
664 err = -ENODEV;
665 goto fail;
666 }
667 set_irq_flags(irq, IRQF_VALID);
668
669#ifdef CONFIG_USB_OTG_UTILS
670 if (pdata->operating_mode == TEGRA_USB_OTG) {
671 tegra->transceiver = otg_get_transceiver();
672 if (tegra->transceiver)
673 otg_set_host(tegra->transceiver, &hcd->self);
674 }
675#endif
676
677 err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
678 if (err) {
679 dev_err(&pdev->dev, "Failed to add USB HCD\n");
680 goto fail;
681 }
682
683 return err;
684
685fail:
686#ifdef CONFIG_USB_OTG_UTILS
687 if (tegra->transceiver) {
688 otg_set_host(tegra->transceiver, NULL);
689 otg_put_transceiver(tegra->transceiver);
690 }
691#endif
692 tegra_usb_phy_close(tegra->phy);
693fail_phy:
694 iounmap(hcd->regs);
695fail_io:
696 clk_disable(tegra->emc_clk);
697 clk_put(tegra->emc_clk);
698fail_emc_clk:
699 clk_disable(tegra->clk);
700fail_clken:
701 clk_put(tegra->clk);
702fail_clk:
703 usb_put_hcd(hcd);
704fail_hcd:
705 kfree(tegra);
706 return err;
707}
708
709#ifdef CONFIG_PM
710static int tegra_ehci_resume(struct platform_device *pdev)
711{
712 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
713 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
714
715 if (tegra->bus_suspended)
716 return 0;
717
718 return tegra_usb_resume(hcd);
719}
720
721static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
722{
723 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
724 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
725
726 if (tegra->bus_suspended)
727 return 0;
728
729 if (time_before(jiffies, tegra->ehci->next_statechange))
730 msleep(10);
731
732 return tegra_usb_suspend(hcd);
733}
734#endif
735
736static int tegra_ehci_remove(struct platform_device *pdev)
737{
738 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
739 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
740
741 if (tegra == NULL || hcd == NULL)
742 return -EINVAL;
743
744#ifdef CONFIG_USB_OTG_UTILS
745 if (tegra->transceiver) {
746 otg_set_host(tegra->transceiver, NULL);
747 otg_put_transceiver(tegra->transceiver);
748 }
749#endif
750
751 usb_remove_hcd(hcd);
752 usb_put_hcd(hcd);
753
754 tegra_usb_phy_close(tegra->phy);
755 iounmap(hcd->regs);
756
757 clk_disable(tegra->clk);
758 clk_put(tegra->clk);
759
760 clk_disable(tegra->emc_clk);
761 clk_put(tegra->emc_clk);
762
763 kfree(tegra);
764 return 0;
765}
766
767static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
768{
769 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
770 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
771
772 if (hcd->driver->shutdown)
773 hcd->driver->shutdown(hcd);
774}
775
776static struct platform_driver tegra_ehci_driver = {
777 .probe = tegra_ehci_probe,
778 .remove = tegra_ehci_remove,
779#ifdef CONFIG_PM
780 .suspend = tegra_ehci_suspend,
781 .resume = tegra_ehci_resume,
782#endif
783 .shutdown = tegra_ehci_hcd_shutdown,
784 .driver = {
785 .name = "tegra-ehci",
786 }
787};
1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/err.h>
22#include <linux/gpio.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/slab.h>
33#include <linux/usb/ehci_def.h>
34#include <linux/usb/tegra_usb_phy.h>
35#include <linux/usb.h>
36#include <linux/usb/hcd.h>
37#include <linux/usb/otg.h>
38
39#include "ehci.h"
40
41#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
42
43#define TEGRA_USB_DMA_ALIGN 32
44
45#define DRIVER_DESC "Tegra EHCI driver"
46#define DRV_NAME "tegra-ehci"
47
48static struct hc_driver __read_mostly tegra_ehci_hc_driver;
49static bool usb1_reset_attempted;
50
51struct tegra_ehci_soc_config {
52 bool has_hostpc;
53};
54
55struct tegra_ehci_hcd {
56 struct tegra_usb_phy *phy;
57 struct clk *clk;
58 struct reset_control *rst;
59 int port_resuming;
60 bool needs_double_reset;
61 enum tegra_usb_phy_port_speed port_speed;
62};
63
64/*
65 * The 1st USB controller contains some UTMI pad registers that are global for
66 * all the controllers on the chip. Those registers are also cleared when
67 * reset is asserted to the 1st controller. This means that the 1st controller
68 * can only be reset when no other controlled has finished probing. So we'll
69 * reset the 1st controller before doing any other setup on any of the
70 * controllers, and then never again.
71 *
72 * Since this is a PHY issue, the Tegra PHY driver should probably be doing
73 * the resetting of the USB controllers. But to keep compatibility with old
74 * device trees that don't have reset phandles in the PHYs, do it here.
75 * Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
76 * device isn't the first one to finish probing, so warn them.
77 */
78static int tegra_reset_usb_controller(struct platform_device *pdev)
79{
80 struct device_node *phy_np;
81 struct usb_hcd *hcd = platform_get_drvdata(pdev);
82 struct tegra_ehci_hcd *tegra =
83 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
84 bool has_utmi_pad_registers = false;
85
86 phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
87 if (!phy_np)
88 return -ENOENT;
89
90 if (of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers"))
91 has_utmi_pad_registers = true;
92
93 if (!usb1_reset_attempted) {
94 struct reset_control *usb1_reset;
95
96 if (!has_utmi_pad_registers)
97 usb1_reset = of_reset_control_get(phy_np, "utmi-pads");
98 else
99 usb1_reset = tegra->rst;
100
101 if (IS_ERR(usb1_reset)) {
102 dev_warn(&pdev->dev,
103 "can't get utmi-pads reset from the PHY\n");
104 dev_warn(&pdev->dev,
105 "continuing, but please update your DT\n");
106 } else {
107 reset_control_assert(usb1_reset);
108 udelay(1);
109 reset_control_deassert(usb1_reset);
110
111 if (!has_utmi_pad_registers)
112 reset_control_put(usb1_reset);
113 }
114
115 usb1_reset_attempted = true;
116 }
117
118 if (!has_utmi_pad_registers) {
119 reset_control_assert(tegra->rst);
120 udelay(1);
121 reset_control_deassert(tegra->rst);
122 }
123
124 of_node_put(phy_np);
125
126 return 0;
127}
128
129static int tegra_ehci_internal_port_reset(
130 struct ehci_hcd *ehci,
131 u32 __iomem *portsc_reg
132)
133{
134 u32 temp;
135 unsigned long flags;
136 int retval = 0;
137 int i, tries;
138 u32 saved_usbintr;
139
140 spin_lock_irqsave(&ehci->lock, flags);
141 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
142 /* disable USB interrupt */
143 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
144 spin_unlock_irqrestore(&ehci->lock, flags);
145
146 /*
147 * Here we have to do Port Reset at most twice for
148 * Port Enable bit to be set.
149 */
150 for (i = 0; i < 2; i++) {
151 temp = ehci_readl(ehci, portsc_reg);
152 temp |= PORT_RESET;
153 ehci_writel(ehci, temp, portsc_reg);
154 mdelay(10);
155 temp &= ~PORT_RESET;
156 ehci_writel(ehci, temp, portsc_reg);
157 mdelay(1);
158 tries = 100;
159 do {
160 mdelay(1);
161 /*
162 * Up to this point, Port Enable bit is
163 * expected to be set after 2 ms waiting.
164 * USB1 usually takes extra 45 ms, for safety,
165 * we take 100 ms as timeout.
166 */
167 temp = ehci_readl(ehci, portsc_reg);
168 } while (!(temp & PORT_PE) && tries--);
169 if (temp & PORT_PE)
170 break;
171 }
172 if (i == 2)
173 retval = -ETIMEDOUT;
174
175 /*
176 * Clear Connect Status Change bit if it's set.
177 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
178 */
179 if (temp & PORT_CSC)
180 ehci_writel(ehci, PORT_CSC, portsc_reg);
181
182 /*
183 * Write to clear any interrupt status bits that might be set
184 * during port reset.
185 */
186 temp = ehci_readl(ehci, &ehci->regs->status);
187 ehci_writel(ehci, temp, &ehci->regs->status);
188
189 /* restore original interrupt enable bits */
190 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
191 return retval;
192}
193
194static int tegra_ehci_hub_control(
195 struct usb_hcd *hcd,
196 u16 typeReq,
197 u16 wValue,
198 u16 wIndex,
199 char *buf,
200 u16 wLength
201)
202{
203 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
204 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
205 u32 __iomem *status_reg;
206 u32 temp;
207 unsigned long flags;
208 int retval = 0;
209
210 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
211
212 spin_lock_irqsave(&ehci->lock, flags);
213
214 if (typeReq == GetPortStatus) {
215 temp = ehci_readl(ehci, status_reg);
216 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
217 /* Resume completed, re-enable disconnect detection */
218 tegra->port_resuming = 0;
219 tegra_usb_phy_postresume(hcd->usb_phy);
220 }
221 }
222
223 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
224 temp = ehci_readl(ehci, status_reg);
225 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
226 retval = -EPIPE;
227 goto done;
228 }
229
230 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
231 temp |= PORT_WKDISC_E | PORT_WKOC_E;
232 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
233
234 /*
235 * If a transaction is in progress, there may be a delay in
236 * suspending the port. Poll until the port is suspended.
237 */
238 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
239 PORT_SUSPEND, 5000))
240 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
241
242 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
243 goto done;
244 }
245
246 /* For USB1 port we need to issue Port Reset twice internally */
247 if (tegra->needs_double_reset &&
248 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
249 spin_unlock_irqrestore(&ehci->lock, flags);
250 return tegra_ehci_internal_port_reset(ehci, status_reg);
251 }
252
253 /*
254 * Tegra host controller will time the resume operation to clear the bit
255 * when the port control state switches to HS or FS Idle. This behavior
256 * is different from EHCI where the host controller driver is required
257 * to set this bit to a zero after the resume duration is timed in the
258 * driver.
259 */
260 else if (typeReq == ClearPortFeature &&
261 wValue == USB_PORT_FEAT_SUSPEND) {
262 temp = ehci_readl(ehci, status_reg);
263 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
264 retval = -EPIPE;
265 goto done;
266 }
267
268 if (!(temp & PORT_SUSPEND))
269 goto done;
270
271 /* Disable disconnect detection during port resume */
272 tegra_usb_phy_preresume(hcd->usb_phy);
273
274 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
275
276 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
277 /* start resume signalling */
278 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
279 set_bit(wIndex-1, &ehci->resuming_ports);
280
281 spin_unlock_irqrestore(&ehci->lock, flags);
282 msleep(20);
283 spin_lock_irqsave(&ehci->lock, flags);
284
285 /* Poll until the controller clears RESUME and SUSPEND */
286 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
287 pr_err("%s: timeout waiting for RESUME\n", __func__);
288 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
289 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
290
291 ehci->reset_done[wIndex-1] = 0;
292 clear_bit(wIndex-1, &ehci->resuming_ports);
293
294 tegra->port_resuming = 1;
295 goto done;
296 }
297
298 spin_unlock_irqrestore(&ehci->lock, flags);
299
300 /* Handle the hub control events here */
301 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
302
303done:
304 spin_unlock_irqrestore(&ehci->lock, flags);
305 return retval;
306}
307
308struct dma_aligned_buffer {
309 void *kmalloc_ptr;
310 void *old_xfer_buffer;
311 u8 data[0];
312};
313
314static void free_dma_aligned_buffer(struct urb *urb)
315{
316 struct dma_aligned_buffer *temp;
317 size_t length;
318
319 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
320 return;
321
322 temp = container_of(urb->transfer_buffer,
323 struct dma_aligned_buffer, data);
324
325 if (usb_urb_dir_in(urb)) {
326 if (usb_pipeisoc(urb->pipe))
327 length = urb->transfer_buffer_length;
328 else
329 length = urb->actual_length;
330
331 memcpy(temp->old_xfer_buffer, temp->data, length);
332 }
333 urb->transfer_buffer = temp->old_xfer_buffer;
334 kfree(temp->kmalloc_ptr);
335
336 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
337}
338
339static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
340{
341 struct dma_aligned_buffer *temp, *kmalloc_ptr;
342 size_t kmalloc_size;
343
344 if (urb->num_sgs || urb->sg ||
345 urb->transfer_buffer_length == 0 ||
346 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
347 return 0;
348
349 /* Allocate a buffer with enough padding for alignment */
350 kmalloc_size = urb->transfer_buffer_length +
351 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
352
353 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
354 if (!kmalloc_ptr)
355 return -ENOMEM;
356
357 /* Position our struct dma_aligned_buffer such that data is aligned */
358 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
359 temp->kmalloc_ptr = kmalloc_ptr;
360 temp->old_xfer_buffer = urb->transfer_buffer;
361 if (usb_urb_dir_out(urb))
362 memcpy(temp->data, urb->transfer_buffer,
363 urb->transfer_buffer_length);
364 urb->transfer_buffer = temp->data;
365
366 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
367
368 return 0;
369}
370
371static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
372 gfp_t mem_flags)
373{
374 int ret;
375
376 ret = alloc_dma_aligned_buffer(urb, mem_flags);
377 if (ret)
378 return ret;
379
380 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
381 if (ret)
382 free_dma_aligned_buffer(urb);
383
384 return ret;
385}
386
387static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
388{
389 usb_hcd_unmap_urb_for_dma(hcd, urb);
390 free_dma_aligned_buffer(urb);
391}
392
393static const struct tegra_ehci_soc_config tegra30_soc_config = {
394 .has_hostpc = true,
395};
396
397static const struct tegra_ehci_soc_config tegra20_soc_config = {
398 .has_hostpc = false,
399};
400
401static const struct of_device_id tegra_ehci_of_match[] = {
402 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
403 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
404 { },
405};
406
407static int tegra_ehci_probe(struct platform_device *pdev)
408{
409 const struct of_device_id *match;
410 const struct tegra_ehci_soc_config *soc_config;
411 struct resource *res;
412 struct usb_hcd *hcd;
413 struct ehci_hcd *ehci;
414 struct tegra_ehci_hcd *tegra;
415 int err = 0;
416 int irq;
417 struct usb_phy *u_phy;
418
419 match = of_match_device(tegra_ehci_of_match, &pdev->dev);
420 if (!match) {
421 dev_err(&pdev->dev, "Error: No device match found\n");
422 return -ENODEV;
423 }
424 soc_config = match->data;
425
426 /* Right now device-tree probed devices don't get dma_mask set.
427 * Since shared usb code relies on it, set it here for now.
428 * Once we have dma capability bindings this can go away.
429 */
430 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
431 if (err)
432 return err;
433
434 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
435 dev_name(&pdev->dev));
436 if (!hcd) {
437 dev_err(&pdev->dev, "Unable to create HCD\n");
438 return -ENOMEM;
439 }
440 platform_set_drvdata(pdev, hcd);
441 ehci = hcd_to_ehci(hcd);
442 tegra = (struct tegra_ehci_hcd *)ehci->priv;
443
444 hcd->has_tt = 1;
445
446 tegra->clk = devm_clk_get(&pdev->dev, NULL);
447 if (IS_ERR(tegra->clk)) {
448 dev_err(&pdev->dev, "Can't get ehci clock\n");
449 err = PTR_ERR(tegra->clk);
450 goto cleanup_hcd_create;
451 }
452
453 tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
454 if (IS_ERR(tegra->rst)) {
455 dev_err(&pdev->dev, "Can't get ehci reset\n");
456 err = PTR_ERR(tegra->rst);
457 goto cleanup_hcd_create;
458 }
459
460 err = clk_prepare_enable(tegra->clk);
461 if (err)
462 goto cleanup_hcd_create;
463
464 err = tegra_reset_usb_controller(pdev);
465 if (err)
466 goto cleanup_clk_en;
467
468 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
469 if (IS_ERR(u_phy)) {
470 err = -EPROBE_DEFER;
471 goto cleanup_clk_en;
472 }
473 hcd->usb_phy = u_phy;
474
475 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
476 "nvidia,needs-double-reset");
477
478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
479 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
480 if (IS_ERR(hcd->regs)) {
481 err = PTR_ERR(hcd->regs);
482 goto cleanup_clk_en;
483 }
484 hcd->rsrc_start = res->start;
485 hcd->rsrc_len = resource_size(res);
486
487 ehci->caps = hcd->regs + 0x100;
488 ehci->has_hostpc = soc_config->has_hostpc;
489
490 err = usb_phy_init(hcd->usb_phy);
491 if (err) {
492 dev_err(&pdev->dev, "Failed to initialize phy\n");
493 goto cleanup_clk_en;
494 }
495
496 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
497 GFP_KERNEL);
498 if (!u_phy->otg) {
499 err = -ENOMEM;
500 goto cleanup_phy;
501 }
502 u_phy->otg->host = hcd_to_bus(hcd);
503
504 err = usb_phy_set_suspend(hcd->usb_phy, 0);
505 if (err) {
506 dev_err(&pdev->dev, "Failed to power on the phy\n");
507 goto cleanup_phy;
508 }
509
510 irq = platform_get_irq(pdev, 0);
511 if (!irq) {
512 dev_err(&pdev->dev, "Failed to get IRQ\n");
513 err = -ENODEV;
514 goto cleanup_phy;
515 }
516
517 otg_set_host(u_phy->otg, &hcd->self);
518
519 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
520 if (err) {
521 dev_err(&pdev->dev, "Failed to add USB HCD\n");
522 goto cleanup_otg_set_host;
523 }
524 device_wakeup_enable(hcd->self.controller);
525
526 return err;
527
528cleanup_otg_set_host:
529 otg_set_host(u_phy->otg, NULL);
530cleanup_phy:
531 usb_phy_shutdown(hcd->usb_phy);
532cleanup_clk_en:
533 clk_disable_unprepare(tegra->clk);
534cleanup_hcd_create:
535 usb_put_hcd(hcd);
536 return err;
537}
538
539static int tegra_ehci_remove(struct platform_device *pdev)
540{
541 struct usb_hcd *hcd = platform_get_drvdata(pdev);
542 struct tegra_ehci_hcd *tegra =
543 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
544
545 otg_set_host(hcd->usb_phy->otg, NULL);
546
547 usb_phy_shutdown(hcd->usb_phy);
548 usb_remove_hcd(hcd);
549
550 clk_disable_unprepare(tegra->clk);
551
552 usb_put_hcd(hcd);
553
554 return 0;
555}
556
557static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
558{
559 struct usb_hcd *hcd = platform_get_drvdata(pdev);
560
561 if (hcd->driver->shutdown)
562 hcd->driver->shutdown(hcd);
563}
564
565static struct platform_driver tegra_ehci_driver = {
566 .probe = tegra_ehci_probe,
567 .remove = tegra_ehci_remove,
568 .shutdown = tegra_ehci_hcd_shutdown,
569 .driver = {
570 .name = DRV_NAME,
571 .of_match_table = tegra_ehci_of_match,
572 }
573};
574
575static int tegra_ehci_reset(struct usb_hcd *hcd)
576{
577 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
578 int retval;
579 int txfifothresh;
580
581 retval = ehci_setup(hcd);
582 if (retval)
583 return retval;
584
585 /*
586 * We should really pull this value out of tegra_ehci_soc_config, but
587 * to avoid needing access to it, make use of the fact that Tegra20 is
588 * the only one so far that needs a value of 10, and Tegra20 is the
589 * only one which doesn't set has_hostpc.
590 */
591 txfifothresh = ehci->has_hostpc ? 0x10 : 10;
592 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
593
594 return 0;
595}
596
597static const struct ehci_driver_overrides tegra_overrides __initconst = {
598 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
599 .reset = tegra_ehci_reset,
600};
601
602static int __init ehci_tegra_init(void)
603{
604 if (usb_disabled())
605 return -ENODEV;
606
607 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
608
609 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
610
611 /*
612 * The Tegra HW has some unusual quirks, which require Tegra-specific
613 * workarounds. We override certain hc_driver functions here to
614 * achieve that. We explicitly do not enhance ehci_driver_overrides to
615 * allow this more easily, since this is an unusual case, and we don't
616 * want to encourage others to override these functions by making it
617 * too easy.
618 */
619
620 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
621 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
622 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
623
624 return platform_driver_register(&tegra_ehci_driver);
625}
626module_init(ehci_tegra_init);
627
628static void __exit ehci_tegra_cleanup(void)
629{
630 platform_driver_unregister(&tegra_ehci_driver);
631}
632module_exit(ehci_tegra_cleanup);
633
634MODULE_DESCRIPTION(DRIVER_DESC);
635MODULE_LICENSE("GPL");
636MODULE_ALIAS("platform:" DRV_NAME);
637MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);