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1/*
2 * Copyright 2005-2009 MontaVista Software, Inc.
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
20 * by Hunter Wu.
21 * Power Management support by Dave Liu <daveliu@freescale.com>,
22 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
23 * Anton Vorontsov <avorontsov@ru.mvista.com>.
24 */
25
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <linux/platform_device.h>
31#include <linux/fsl_devices.h>
32
33#include "ehci-fsl.h"
34
35/* configure so an HC device and id are always provided */
36/* always called with process context; sleeping is OK */
37
38/**
39 * usb_hcd_fsl_probe - initialize FSL-based HCDs
40 * @drvier: Driver to be used for this HCD
41 * @pdev: USB Host Controller being probed
42 * Context: !in_interrupt()
43 *
44 * Allocates basic resources for this USB host controller.
45 *
46 */
47static int usb_hcd_fsl_probe(const struct hc_driver *driver,
48 struct platform_device *pdev)
49{
50 struct fsl_usb2_platform_data *pdata;
51 struct usb_hcd *hcd;
52 struct resource *res;
53 int irq;
54 int retval;
55
56 pr_debug("initializing FSL-SOC USB Controller\n");
57
58 /* Need platform data for setup */
59 pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
60 if (!pdata) {
61 dev_err(&pdev->dev,
62 "No platform data for %s.\n", dev_name(&pdev->dev));
63 return -ENODEV;
64 }
65
66 /*
67 * This is a host mode driver, verify that we're supposed to be
68 * in host mode.
69 */
70 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
71 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
72 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
73 dev_err(&pdev->dev,
74 "Non Host Mode configured for %s. Wrong driver linked.\n",
75 dev_name(&pdev->dev));
76 return -ENODEV;
77 }
78
79 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
80 if (!res) {
81 dev_err(&pdev->dev,
82 "Found HC with no IRQ. Check %s setup!\n",
83 dev_name(&pdev->dev));
84 return -ENODEV;
85 }
86 irq = res->start;
87
88 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
89 if (!hcd) {
90 retval = -ENOMEM;
91 goto err1;
92 }
93
94 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
95 if (!res) {
96 dev_err(&pdev->dev,
97 "Found HC with no register addr. Check %s setup!\n",
98 dev_name(&pdev->dev));
99 retval = -ENODEV;
100 goto err2;
101 }
102 hcd->rsrc_start = res->start;
103 hcd->rsrc_len = resource_size(res);
104 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
105 driver->description)) {
106 dev_dbg(&pdev->dev, "controller already in use\n");
107 retval = -EBUSY;
108 goto err2;
109 }
110 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
111
112 if (hcd->regs == NULL) {
113 dev_dbg(&pdev->dev, "error mapping memory\n");
114 retval = -EFAULT;
115 goto err3;
116 }
117
118 pdata->regs = hcd->regs;
119
120 if (pdata->power_budget)
121 hcd->power_budget = pdata->power_budget;
122
123 /*
124 * do platform specific init: check the clock, grab/config pins, etc.
125 */
126 if (pdata->init && pdata->init(pdev)) {
127 retval = -ENODEV;
128 goto err3;
129 }
130
131 /* Enable USB controller, 83xx or 8536 */
132 if (pdata->have_sysif_regs)
133 setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
134
135 /* Don't need to set host mode here. It will be done by tdi_reset() */
136
137 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
138 if (retval != 0)
139 goto err4;
140
141#ifdef CONFIG_USB_OTG
142 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
143 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
144
145 ehci->transceiver = otg_get_transceiver();
146 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n",
147 hcd, ehci, ehci->transceiver);
148
149 if (ehci->transceiver) {
150 retval = otg_set_host(ehci->transceiver,
151 &ehci_to_hcd(ehci)->self);
152 if (retval) {
153 if (ehci->transceiver)
154 put_device(ehci->transceiver->dev);
155 goto err4;
156 }
157 } else {
158 dev_err(&pdev->dev, "can't find transceiver\n");
159 retval = -ENODEV;
160 goto err4;
161 }
162 }
163#endif
164 return retval;
165
166 err4:
167 iounmap(hcd->regs);
168 err3:
169 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
170 err2:
171 usb_put_hcd(hcd);
172 err1:
173 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
174 if (pdata->exit)
175 pdata->exit(pdev);
176 return retval;
177}
178
179/* may be called without controller electrically present */
180/* may be called with controller, bus, and devices active */
181
182/**
183 * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
184 * @dev: USB Host Controller being removed
185 * Context: !in_interrupt()
186 *
187 * Reverses the effect of usb_hcd_fsl_probe().
188 *
189 */
190static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
191 struct platform_device *pdev)
192{
193 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
194 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
195
196 if (ehci->transceiver) {
197 otg_set_host(ehci->transceiver, NULL);
198 put_device(ehci->transceiver->dev);
199 }
200
201 usb_remove_hcd(hcd);
202
203 /*
204 * do platform specific un-initialization:
205 * release iomux pins, disable clock, etc.
206 */
207 if (pdata->exit)
208 pdata->exit(pdev);
209 iounmap(hcd->regs);
210 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
211 usb_put_hcd(hcd);
212}
213
214static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
215 enum fsl_usb2_phy_modes phy_mode,
216 unsigned int port_offset)
217{
218 u32 portsc;
219
220 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
221 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
222
223 switch (phy_mode) {
224 case FSL_USB2_PHY_ULPI:
225 portsc |= PORT_PTS_ULPI;
226 break;
227 case FSL_USB2_PHY_SERIAL:
228 portsc |= PORT_PTS_SERIAL;
229 break;
230 case FSL_USB2_PHY_UTMI_WIDE:
231 portsc |= PORT_PTS_PTW;
232 /* fall through */
233 case FSL_USB2_PHY_UTMI:
234 portsc |= PORT_PTS_UTMI;
235 break;
236 case FSL_USB2_PHY_NONE:
237 break;
238 }
239 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
240}
241
242static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
243{
244 struct usb_hcd *hcd = ehci_to_hcd(ehci);
245 struct fsl_usb2_platform_data *pdata;
246 void __iomem *non_ehci = hcd->regs;
247 u32 temp;
248
249 pdata = hcd->self.controller->platform_data;
250
251 /* Enable PHY interface in the control reg. */
252 if (pdata->have_sysif_regs) {
253 temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
254 out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
255 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b);
256 }
257
258#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
259 /*
260 * Turn on cache snooping hardware, since some PowerPC platforms
261 * wholly rely on hardware to deal with cache coherent
262 */
263
264 /* Setup Snooping for all the 4GB space */
265 /* SNOOP1 starts from 0x0, size 2G */
266 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
267 /* SNOOP2 starts from 0x80000000, size 2G */
268 out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
269#endif
270
271 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
272 (pdata->operating_mode == FSL_USB2_DR_OTG))
273 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
274
275 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
276 unsigned int chip, rev, svr;
277
278 svr = mfspr(SPRN_SVR);
279 chip = svr >> 16;
280 rev = (svr >> 4) & 0xf;
281
282 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
283 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
284 ehci->has_fsl_port_bug = 1;
285
286 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
287 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
288 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
289 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1);
290 }
291
292 if (pdata->have_sysif_regs) {
293#ifdef CONFIG_PPC_85xx
294 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
295 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
296#else
297 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
298 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
299#endif
300 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
301 }
302}
303
304/* called after powerup, by probe or system-pm "wakeup" */
305static int ehci_fsl_reinit(struct ehci_hcd *ehci)
306{
307 ehci_fsl_usb_setup(ehci);
308 ehci_port_power(ehci, 0);
309
310 return 0;
311}
312
313/* called during probe() after chip reset completes */
314static int ehci_fsl_setup(struct usb_hcd *hcd)
315{
316 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
317 int retval;
318 struct fsl_usb2_platform_data *pdata;
319
320 pdata = hcd->self.controller->platform_data;
321 ehci->big_endian_desc = pdata->big_endian_desc;
322 ehci->big_endian_mmio = pdata->big_endian_mmio;
323
324 /* EHCI registers start at offset 0x100 */
325 ehci->caps = hcd->regs + 0x100;
326 ehci->regs = hcd->regs + 0x100 +
327 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
328 dbg_hcs_params(ehci, "reset");
329 dbg_hcc_params(ehci, "reset");
330
331 /* cache this readonly data; minimize chip reads */
332 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
333
334 hcd->has_tt = 1;
335
336 retval = ehci_halt(ehci);
337 if (retval)
338 return retval;
339
340 /* data structure init */
341 retval = ehci_init(hcd);
342 if (retval)
343 return retval;
344
345 ehci->sbrn = 0x20;
346
347 ehci_reset(ehci);
348
349 retval = ehci_fsl_reinit(ehci);
350 return retval;
351}
352
353struct ehci_fsl {
354 struct ehci_hcd ehci;
355
356#ifdef CONFIG_PM
357 /* Saved USB PHY settings, need to restore after deep sleep. */
358 u32 usb_ctrl;
359#endif
360};
361
362#ifdef CONFIG_PM
363
364#ifdef CONFIG_PPC_MPC512x
365static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
366{
367 struct usb_hcd *hcd = dev_get_drvdata(dev);
368 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
369 struct fsl_usb2_platform_data *pdata = dev->platform_data;
370 u32 tmp;
371
372#ifdef DEBUG
373 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
374 mode &= USBMODE_CM_MASK;
375 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
376
377 dev_dbg(dev, "suspend=%d already_suspended=%d "
378 "mode=%d usbcmd %08x\n", pdata->suspended,
379 pdata->already_suspended, mode, tmp);
380#endif
381
382 /*
383 * If the controller is already suspended, then this must be a
384 * PM suspend. Remember this fact, so that we will leave the
385 * controller suspended at PM resume time.
386 */
387 if (pdata->suspended) {
388 dev_dbg(dev, "already suspended, leaving early\n");
389 pdata->already_suspended = 1;
390 return 0;
391 }
392
393 dev_dbg(dev, "suspending...\n");
394
395 hcd->state = HC_STATE_SUSPENDED;
396 dev->power.power_state = PMSG_SUSPEND;
397
398 /* ignore non-host interrupts */
399 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
400
401 /* stop the controller */
402 tmp = ehci_readl(ehci, &ehci->regs->command);
403 tmp &= ~CMD_RUN;
404 ehci_writel(ehci, tmp, &ehci->regs->command);
405
406 /* save EHCI registers */
407 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
408 pdata->pm_command &= ~CMD_RUN;
409 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
410 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
411 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
412 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
413 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
414 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
415 pdata->pm_configured_flag =
416 ehci_readl(ehci, &ehci->regs->configured_flag);
417 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
418 pdata->pm_usbgenctrl = ehci_readl(ehci,
419 hcd->regs + FSL_SOC_USB_USBGENCTRL);
420
421 /* clear the W1C bits */
422 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
423
424 pdata->suspended = 1;
425
426 /* clear PP to cut power to the port */
427 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
428 tmp &= ~PORT_POWER;
429 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
430
431 return 0;
432}
433
434static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
435{
436 struct usb_hcd *hcd = dev_get_drvdata(dev);
437 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
438 struct fsl_usb2_platform_data *pdata = dev->platform_data;
439 u32 tmp;
440
441 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
442 pdata->suspended, pdata->already_suspended);
443
444 /*
445 * If the controller was already suspended at suspend time,
446 * then don't resume it now.
447 */
448 if (pdata->already_suspended) {
449 dev_dbg(dev, "already suspended, leaving early\n");
450 pdata->already_suspended = 0;
451 return 0;
452 }
453
454 if (!pdata->suspended) {
455 dev_dbg(dev, "not suspended, leaving early\n");
456 return 0;
457 }
458
459 pdata->suspended = 0;
460
461 dev_dbg(dev, "resuming...\n");
462
463 /* set host mode */
464 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
465 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
466
467 ehci_writel(ehci, pdata->pm_usbgenctrl,
468 hcd->regs + FSL_SOC_USB_USBGENCTRL);
469 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
470 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
471
472 /* restore EHCI registers */
473 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
474 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
475 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
476 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
477 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
478 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
479 ehci_writel(ehci, pdata->pm_configured_flag,
480 &ehci->regs->configured_flag);
481 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
482
483 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
484 hcd->state = HC_STATE_RUNNING;
485 dev->power.power_state = PMSG_ON;
486
487 tmp = ehci_readl(ehci, &ehci->regs->command);
488 tmp |= CMD_RUN;
489 ehci_writel(ehci, tmp, &ehci->regs->command);
490
491 usb_hcd_resume_root_hub(hcd);
492
493 return 0;
494}
495#else
496static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
497{
498 return 0;
499}
500
501static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
502{
503 return 0;
504}
505#endif /* CONFIG_PPC_MPC512x */
506
507static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
508{
509 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
510
511 return container_of(ehci, struct ehci_fsl, ehci);
512}
513
514static int ehci_fsl_drv_suspend(struct device *dev)
515{
516 struct usb_hcd *hcd = dev_get_drvdata(dev);
517 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
518 void __iomem *non_ehci = hcd->regs;
519
520 if (of_device_is_compatible(dev->parent->of_node,
521 "fsl,mpc5121-usb2-dr")) {
522 return ehci_fsl_mpc512x_drv_suspend(dev);
523 }
524
525 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
526 device_may_wakeup(dev));
527 if (!fsl_deep_sleep())
528 return 0;
529
530 ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
531 return 0;
532}
533
534static int ehci_fsl_drv_resume(struct device *dev)
535{
536 struct usb_hcd *hcd = dev_get_drvdata(dev);
537 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
538 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
539 void __iomem *non_ehci = hcd->regs;
540
541 if (of_device_is_compatible(dev->parent->of_node,
542 "fsl,mpc5121-usb2-dr")) {
543 return ehci_fsl_mpc512x_drv_resume(dev);
544 }
545
546 ehci_prepare_ports_for_controller_resume(ehci);
547 if (!fsl_deep_sleep())
548 return 0;
549
550 usb_root_hub_lost_power(hcd->self.root_hub);
551
552 /* Restore USB PHY settings and enable the controller. */
553 out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
554
555 ehci_reset(ehci);
556 ehci_fsl_reinit(ehci);
557
558 return 0;
559}
560
561static int ehci_fsl_drv_restore(struct device *dev)
562{
563 struct usb_hcd *hcd = dev_get_drvdata(dev);
564
565 usb_root_hub_lost_power(hcd->self.root_hub);
566 return 0;
567}
568
569static struct dev_pm_ops ehci_fsl_pm_ops = {
570 .suspend = ehci_fsl_drv_suspend,
571 .resume = ehci_fsl_drv_resume,
572 .restore = ehci_fsl_drv_restore,
573};
574
575#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
576#else
577#define EHCI_FSL_PM_OPS NULL
578#endif /* CONFIG_PM */
579
580#ifdef CONFIG_USB_OTG
581static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
582{
583 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
584 u32 status;
585
586 if (!port)
587 return -EINVAL;
588
589 port--;
590
591 /* start port reset before HNP protocol time out */
592 status = readl(&ehci->regs->port_status[port]);
593 if (!(status & PORT_CONNECT))
594 return -ENODEV;
595
596 /* khubd will finish the reset later */
597 if (ehci_is_TDI(ehci)) {
598 writel(PORT_RESET |
599 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
600 &ehci->regs->port_status[port]);
601 } else {
602 writel(PORT_RESET, &ehci->regs->port_status[port]);
603 }
604
605 return 0;
606}
607#else
608#define ehci_start_port_reset NULL
609#endif /* CONFIG_USB_OTG */
610
611
612static const struct hc_driver ehci_fsl_hc_driver = {
613 .description = hcd_name,
614 .product_desc = "Freescale On-Chip EHCI Host Controller",
615 .hcd_priv_size = sizeof(struct ehci_fsl),
616
617 /*
618 * generic hardware linkage
619 */
620 .irq = ehci_irq,
621 .flags = HCD_USB2 | HCD_MEMORY,
622
623 /*
624 * basic lifecycle operations
625 */
626 .reset = ehci_fsl_setup,
627 .start = ehci_run,
628 .stop = ehci_stop,
629 .shutdown = ehci_shutdown,
630
631 /*
632 * managing i/o requests and associated device resources
633 */
634 .urb_enqueue = ehci_urb_enqueue,
635 .urb_dequeue = ehci_urb_dequeue,
636 .endpoint_disable = ehci_endpoint_disable,
637 .endpoint_reset = ehci_endpoint_reset,
638
639 /*
640 * scheduling support
641 */
642 .get_frame_number = ehci_get_frame,
643
644 /*
645 * root hub support
646 */
647 .hub_status_data = ehci_hub_status_data,
648 .hub_control = ehci_hub_control,
649 .bus_suspend = ehci_bus_suspend,
650 .bus_resume = ehci_bus_resume,
651 .start_port_reset = ehci_start_port_reset,
652 .relinquish_port = ehci_relinquish_port,
653 .port_handed_over = ehci_port_handed_over,
654
655 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
656};
657
658static int ehci_fsl_drv_probe(struct platform_device *pdev)
659{
660 if (usb_disabled())
661 return -ENODEV;
662
663 /* FIXME we only want one one probe() not two */
664 return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
665}
666
667static int ehci_fsl_drv_remove(struct platform_device *pdev)
668{
669 struct usb_hcd *hcd = platform_get_drvdata(pdev);
670
671 /* FIXME we only want one one remove() not two */
672 usb_hcd_fsl_remove(hcd, pdev);
673 return 0;
674}
675
676MODULE_ALIAS("platform:fsl-ehci");
677
678static struct platform_driver ehci_fsl_driver = {
679 .probe = ehci_fsl_drv_probe,
680 .remove = ehci_fsl_drv_remove,
681 .shutdown = usb_hcd_platform_shutdown,
682 .driver = {
683 .name = "fsl-ehci",
684 .pm = EHCI_FSL_PM_OPS,
685 },
686};
1/*
2 * Copyright 2005-2009 MontaVista Software, Inc.
3 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
20 * by Hunter Wu.
21 * Power Management support by Dave Liu <daveliu@freescale.com>,
22 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
23 * Anton Vorontsov <avorontsov@ru.mvista.com>.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/types.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31#include <linux/err.h>
32#include <linux/usb.h>
33#include <linux/usb/ehci_def.h>
34#include <linux/usb/hcd.h>
35#include <linux/usb/otg.h>
36#include <linux/platform_device.h>
37#include <linux/fsl_devices.h>
38#include <linux/of_platform.h>
39
40#include "ehci.h"
41#include "ehci-fsl.h"
42
43#define DRIVER_DESC "Freescale EHCI Host controller driver"
44#define DRV_NAME "ehci-fsl"
45
46static struct hc_driver __read_mostly fsl_ehci_hc_driver;
47
48/* configure so an HC device and id are always provided */
49/* always called with process context; sleeping is OK */
50
51/*
52 * fsl_ehci_drv_probe - initialize FSL-based HCDs
53 * @pdev: USB Host Controller being probed
54 * Context: !in_interrupt()
55 *
56 * Allocates basic resources for this USB host controller.
57 *
58 */
59static int fsl_ehci_drv_probe(struct platform_device *pdev)
60{
61 struct fsl_usb2_platform_data *pdata;
62 struct usb_hcd *hcd;
63 struct resource *res;
64 int irq;
65 int retval;
66
67 pr_debug("initializing FSL-SOC USB Controller\n");
68
69 /* Need platform data for setup */
70 pdata = dev_get_platdata(&pdev->dev);
71 if (!pdata) {
72 dev_err(&pdev->dev,
73 "No platform data for %s.\n", dev_name(&pdev->dev));
74 return -ENODEV;
75 }
76
77 /*
78 * This is a host mode driver, verify that we're supposed to be
79 * in host mode.
80 */
81 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
82 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
83 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
84 dev_err(&pdev->dev,
85 "Non Host Mode configured for %s. Wrong driver linked.\n",
86 dev_name(&pdev->dev));
87 return -ENODEV;
88 }
89
90 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
91 if (!res) {
92 dev_err(&pdev->dev,
93 "Found HC with no IRQ. Check %s setup!\n",
94 dev_name(&pdev->dev));
95 return -ENODEV;
96 }
97 irq = res->start;
98
99 hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev,
100 dev_name(&pdev->dev));
101 if (!hcd) {
102 retval = -ENOMEM;
103 goto err1;
104 }
105
106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
108 if (IS_ERR(hcd->regs)) {
109 retval = PTR_ERR(hcd->regs);
110 goto err2;
111 }
112
113 hcd->rsrc_start = res->start;
114 hcd->rsrc_len = resource_size(res);
115
116 pdata->regs = hcd->regs;
117
118 if (pdata->power_budget)
119 hcd->power_budget = pdata->power_budget;
120
121 /*
122 * do platform specific init: check the clock, grab/config pins, etc.
123 */
124 if (pdata->init && pdata->init(pdev)) {
125 retval = -ENODEV;
126 goto err2;
127 }
128
129 /* Enable USB controller, 83xx or 8536 */
130 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
131 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
132 CONTROL_REGISTER_W1C_MASK, 0x4);
133
134 /*
135 * Enable UTMI phy and program PTS field in UTMI mode before asserting
136 * controller reset for USB Controller version 2.5
137 */
138 if (pdata->has_fsl_erratum_a007792) {
139 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
140 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
141 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
142 }
143
144 /* Don't need to set host mode here. It will be done by tdi_reset() */
145
146 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
147 if (retval != 0)
148 goto err2;
149 device_wakeup_enable(hcd->self.controller);
150
151#ifdef CONFIG_USB_OTG
152 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
153 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
154
155 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
156 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
157 hcd, ehci, hcd->usb_phy);
158
159 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
160 retval = otg_set_host(hcd->usb_phy->otg,
161 &ehci_to_hcd(ehci)->self);
162 if (retval) {
163 usb_put_phy(hcd->usb_phy);
164 goto err2;
165 }
166 } else {
167 dev_err(&pdev->dev, "can't find phy\n");
168 retval = -ENODEV;
169 goto err2;
170 }
171 }
172#endif
173 return retval;
174
175 err2:
176 usb_put_hcd(hcd);
177 err1:
178 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
179 if (pdata->exit)
180 pdata->exit(pdev);
181 return retval;
182}
183
184static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
185 enum fsl_usb2_phy_modes phy_mode,
186 unsigned int port_offset)
187{
188 u32 portsc;
189 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
190 void __iomem *non_ehci = hcd->regs;
191 struct device *dev = hcd->self.controller;
192 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
193
194 if (pdata->controller_ver < 0) {
195 dev_warn(hcd->self.controller, "Could not get controller version\n");
196 return -ENODEV;
197 }
198
199 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
200 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
201
202 switch (phy_mode) {
203 case FSL_USB2_PHY_ULPI:
204 if (pdata->have_sysif_regs && pdata->controller_ver) {
205 /* controller version 1.6 or above */
206 clrbits32(non_ehci + FSL_SOC_USB_CTRL,
207 CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
208 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
209 CONTROL_REGISTER_W1C_MASK,
210 ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
211 }
212 portsc |= PORT_PTS_ULPI;
213 break;
214 case FSL_USB2_PHY_SERIAL:
215 portsc |= PORT_PTS_SERIAL;
216 break;
217 case FSL_USB2_PHY_UTMI_WIDE:
218 portsc |= PORT_PTS_PTW;
219 /* fall through */
220 case FSL_USB2_PHY_UTMI:
221 case FSL_USB2_PHY_UTMI_DUAL:
222 if (pdata->have_sysif_regs && pdata->controller_ver) {
223 /* controller version 1.6 or above */
224 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
225 CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
226 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
227 become stable - 10ms*/
228 }
229 /* enable UTMI PHY */
230 if (pdata->have_sysif_regs)
231 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
232 CONTROL_REGISTER_W1C_MASK,
233 CTRL_UTMI_PHY_EN);
234 portsc |= PORT_PTS_UTMI;
235 break;
236 case FSL_USB2_PHY_NONE:
237 break;
238 }
239
240 /*
241 * check PHY_CLK_VALID to determine phy clock presence before writing
242 * to portsc
243 */
244 if (pdata->check_phy_clk_valid) {
245 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
246 PHY_CLK_VALID)) {
247 dev_warn(hcd->self.controller,
248 "USB PHY clock invalid\n");
249 return -EINVAL;
250 }
251 }
252
253 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
254
255 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
256 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
257 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
258
259 return 0;
260}
261
262static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
263{
264 struct usb_hcd *hcd = ehci_to_hcd(ehci);
265 struct fsl_usb2_platform_data *pdata;
266 void __iomem *non_ehci = hcd->regs;
267
268 pdata = dev_get_platdata(hcd->self.controller);
269
270 if (pdata->have_sysif_regs) {
271 /*
272 * Turn on cache snooping hardware, since some PowerPC platforms
273 * wholly rely on hardware to deal with cache coherent
274 */
275
276 /* Setup Snooping for all the 4GB space */
277 /* SNOOP1 starts from 0x0, size 2G */
278 iowrite32be(0x0 | SNOOP_SIZE_2GB,
279 non_ehci + FSL_SOC_USB_SNOOP1);
280 /* SNOOP2 starts from 0x80000000, size 2G */
281 iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
282 non_ehci + FSL_SOC_USB_SNOOP2);
283 }
284
285 /* Deal with USB erratum A-005275 */
286 if (pdata->has_fsl_erratum_a005275 == 1)
287 ehci->has_fsl_hs_errata = 1;
288
289 if (pdata->has_fsl_erratum_a005697 == 1)
290 ehci->has_fsl_susp_errata = 1;
291
292 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
293 (pdata->operating_mode == FSL_USB2_DR_OTG))
294 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
295 return -EINVAL;
296
297 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
298 unsigned int chip, rev, svr;
299
300 svr = mfspr(SPRN_SVR);
301 chip = svr >> 16;
302 rev = (svr >> 4) & 0xf;
303
304 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
305 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
306 ehci->has_fsl_port_bug = 1;
307
308 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
309 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
310 return -EINVAL;
311
312 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
313 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
314 return -EINVAL;
315 }
316
317 if (pdata->have_sysif_regs) {
318#ifdef CONFIG_FSL_SOC_BOOKE
319 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
320 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
321#else
322 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
323 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
324#endif
325 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
326 }
327
328 return 0;
329}
330
331/* called after powerup, by probe or system-pm "wakeup" */
332static int ehci_fsl_reinit(struct ehci_hcd *ehci)
333{
334 if (ehci_fsl_usb_setup(ehci))
335 return -EINVAL;
336
337 return 0;
338}
339
340/* called during probe() after chip reset completes */
341static int ehci_fsl_setup(struct usb_hcd *hcd)
342{
343 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
344 int retval;
345 struct fsl_usb2_platform_data *pdata;
346 struct device *dev;
347
348 dev = hcd->self.controller;
349 pdata = dev_get_platdata(hcd->self.controller);
350 ehci->big_endian_desc = pdata->big_endian_desc;
351 ehci->big_endian_mmio = pdata->big_endian_mmio;
352
353 /* EHCI registers start at offset 0x100 */
354 ehci->caps = hcd->regs + 0x100;
355
356#ifdef CONFIG_PPC_83xx
357 /*
358 * Deal with MPC834X that need port power to be cycled after the power
359 * fault condition is removed. Otherwise the state machine does not
360 * reflect PORTSC[CSC] correctly.
361 */
362 ehci->need_oc_pp_cycle = 1;
363#endif
364
365 hcd->has_tt = 1;
366
367 retval = ehci_setup(hcd);
368 if (retval)
369 return retval;
370
371 if (of_device_is_compatible(dev->parent->of_node,
372 "fsl,mpc5121-usb2-dr")) {
373 /*
374 * set SBUSCFG:AHBBRST so that control msgs don't
375 * fail when doing heavy PATA writes.
376 */
377 ehci_writel(ehci, SBUSCFG_INCR8,
378 hcd->regs + FSL_SOC_USB_SBUSCFG);
379 }
380
381 retval = ehci_fsl_reinit(ehci);
382 return retval;
383}
384
385struct ehci_fsl {
386 struct ehci_hcd ehci;
387
388#ifdef CONFIG_PM
389 /* Saved USB PHY settings, need to restore after deep sleep. */
390 u32 usb_ctrl;
391#endif
392};
393
394#ifdef CONFIG_PM
395
396#ifdef CONFIG_PPC_MPC512x
397static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
398{
399 struct usb_hcd *hcd = dev_get_drvdata(dev);
400 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
401 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
402 u32 tmp;
403
404#ifdef CONFIG_DYNAMIC_DEBUG
405 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
406 mode &= USBMODE_CM_MASK;
407 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
408
409 dev_dbg(dev, "suspend=%d already_suspended=%d "
410 "mode=%d usbcmd %08x\n", pdata->suspended,
411 pdata->already_suspended, mode, tmp);
412#endif
413
414 /*
415 * If the controller is already suspended, then this must be a
416 * PM suspend. Remember this fact, so that we will leave the
417 * controller suspended at PM resume time.
418 */
419 if (pdata->suspended) {
420 dev_dbg(dev, "already suspended, leaving early\n");
421 pdata->already_suspended = 1;
422 return 0;
423 }
424
425 dev_dbg(dev, "suspending...\n");
426
427 ehci->rh_state = EHCI_RH_SUSPENDED;
428 dev->power.power_state = PMSG_SUSPEND;
429
430 /* ignore non-host interrupts */
431 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
432
433 /* stop the controller */
434 tmp = ehci_readl(ehci, &ehci->regs->command);
435 tmp &= ~CMD_RUN;
436 ehci_writel(ehci, tmp, &ehci->regs->command);
437
438 /* save EHCI registers */
439 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
440 pdata->pm_command &= ~CMD_RUN;
441 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
442 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
443 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
444 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
445 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
446 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
447 pdata->pm_configured_flag =
448 ehci_readl(ehci, &ehci->regs->configured_flag);
449 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
450 pdata->pm_usbgenctrl = ehci_readl(ehci,
451 hcd->regs + FSL_SOC_USB_USBGENCTRL);
452
453 /* clear the W1C bits */
454 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
455
456 pdata->suspended = 1;
457
458 /* clear PP to cut power to the port */
459 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
460 tmp &= ~PORT_POWER;
461 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
462
463 return 0;
464}
465
466static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
467{
468 struct usb_hcd *hcd = dev_get_drvdata(dev);
469 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
470 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
471 u32 tmp;
472
473 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
474 pdata->suspended, pdata->already_suspended);
475
476 /*
477 * If the controller was already suspended at suspend time,
478 * then don't resume it now.
479 */
480 if (pdata->already_suspended) {
481 dev_dbg(dev, "already suspended, leaving early\n");
482 pdata->already_suspended = 0;
483 return 0;
484 }
485
486 if (!pdata->suspended) {
487 dev_dbg(dev, "not suspended, leaving early\n");
488 return 0;
489 }
490
491 pdata->suspended = 0;
492
493 dev_dbg(dev, "resuming...\n");
494
495 /* set host mode */
496 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
497 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
498
499 ehci_writel(ehci, pdata->pm_usbgenctrl,
500 hcd->regs + FSL_SOC_USB_USBGENCTRL);
501 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
502 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
503
504 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
505
506 /* restore EHCI registers */
507 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
508 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
509 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
510 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
511 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
512 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
513 ehci_writel(ehci, pdata->pm_configured_flag,
514 &ehci->regs->configured_flag);
515 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
516
517 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
518 ehci->rh_state = EHCI_RH_RUNNING;
519 dev->power.power_state = PMSG_ON;
520
521 tmp = ehci_readl(ehci, &ehci->regs->command);
522 tmp |= CMD_RUN;
523 ehci_writel(ehci, tmp, &ehci->regs->command);
524
525 usb_hcd_resume_root_hub(hcd);
526
527 return 0;
528}
529#else
530static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
531{
532 return 0;
533}
534
535static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
536{
537 return 0;
538}
539#endif /* CONFIG_PPC_MPC512x */
540
541static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
542{
543 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
544
545 return container_of(ehci, struct ehci_fsl, ehci);
546}
547
548static int ehci_fsl_drv_suspend(struct device *dev)
549{
550 struct usb_hcd *hcd = dev_get_drvdata(dev);
551 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
552 void __iomem *non_ehci = hcd->regs;
553
554 if (of_device_is_compatible(dev->parent->of_node,
555 "fsl,mpc5121-usb2-dr")) {
556 return ehci_fsl_mpc512x_drv_suspend(dev);
557 }
558
559 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
560 device_may_wakeup(dev));
561 if (!fsl_deep_sleep())
562 return 0;
563
564 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
565 return 0;
566}
567
568static int ehci_fsl_drv_resume(struct device *dev)
569{
570 struct usb_hcd *hcd = dev_get_drvdata(dev);
571 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
572 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
573 void __iomem *non_ehci = hcd->regs;
574
575 if (of_device_is_compatible(dev->parent->of_node,
576 "fsl,mpc5121-usb2-dr")) {
577 return ehci_fsl_mpc512x_drv_resume(dev);
578 }
579
580 ehci_prepare_ports_for_controller_resume(ehci);
581 if (!fsl_deep_sleep())
582 return 0;
583
584 usb_root_hub_lost_power(hcd->self.root_hub);
585
586 /* Restore USB PHY settings and enable the controller. */
587 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
588
589 ehci_reset(ehci);
590 ehci_fsl_reinit(ehci);
591
592 return 0;
593}
594
595static int ehci_fsl_drv_restore(struct device *dev)
596{
597 struct usb_hcd *hcd = dev_get_drvdata(dev);
598
599 usb_root_hub_lost_power(hcd->self.root_hub);
600 return 0;
601}
602
603static struct dev_pm_ops ehci_fsl_pm_ops = {
604 .suspend = ehci_fsl_drv_suspend,
605 .resume = ehci_fsl_drv_resume,
606 .restore = ehci_fsl_drv_restore,
607};
608
609#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
610#else
611#define EHCI_FSL_PM_OPS NULL
612#endif /* CONFIG_PM */
613
614#ifdef CONFIG_USB_OTG
615static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
616{
617 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
618 u32 status;
619
620 if (!port)
621 return -EINVAL;
622
623 port--;
624
625 /* start port reset before HNP protocol time out */
626 status = readl(&ehci->regs->port_status[port]);
627 if (!(status & PORT_CONNECT))
628 return -ENODEV;
629
630 /* hub_wq will finish the reset later */
631 if (ehci_is_TDI(ehci)) {
632 writel(PORT_RESET |
633 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
634 &ehci->regs->port_status[port]);
635 } else {
636 writel(PORT_RESET, &ehci->regs->port_status[port]);
637 }
638
639 return 0;
640}
641#else
642#define ehci_start_port_reset NULL
643#endif /* CONFIG_USB_OTG */
644
645static struct ehci_driver_overrides ehci_fsl_overrides __initdata = {
646 .extra_priv_size = sizeof(struct ehci_fsl),
647 .reset = ehci_fsl_setup,
648};
649
650/**
651 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
652 * @dev: USB Host Controller being removed
653 * Context: !in_interrupt()
654 *
655 * Reverses the effect of usb_hcd_fsl_probe().
656 *
657 */
658
659static int fsl_ehci_drv_remove(struct platform_device *pdev)
660{
661 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
662 struct usb_hcd *hcd = platform_get_drvdata(pdev);
663
664 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
665 otg_set_host(hcd->usb_phy->otg, NULL);
666 usb_put_phy(hcd->usb_phy);
667 }
668
669 usb_remove_hcd(hcd);
670
671 /*
672 * do platform specific un-initialization:
673 * release iomux pins, disable clock, etc.
674 */
675 if (pdata->exit)
676 pdata->exit(pdev);
677 usb_put_hcd(hcd);
678
679 return 0;
680}
681
682static struct platform_driver ehci_fsl_driver = {
683 .probe = fsl_ehci_drv_probe,
684 .remove = fsl_ehci_drv_remove,
685 .shutdown = usb_hcd_platform_shutdown,
686 .driver = {
687 .name = "fsl-ehci",
688 .pm = EHCI_FSL_PM_OPS,
689 },
690};
691
692static int __init ehci_fsl_init(void)
693{
694 if (usb_disabled())
695 return -ENODEV;
696
697 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
698
699 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
700
701 fsl_ehci_hc_driver.product_desc =
702 "Freescale On-Chip EHCI Host Controller";
703 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
704
705
706 return platform_driver_register(&ehci_fsl_driver);
707}
708module_init(ehci_fsl_init);
709
710static void __exit ehci_fsl_cleanup(void)
711{
712 platform_driver_unregister(&ehci_fsl_driver);
713}
714module_exit(ehci_fsl_cleanup);
715
716MODULE_DESCRIPTION(DRIVER_DESC);
717MODULE_LICENSE("GPL");
718MODULE_ALIAS("platform:" DRV_NAME);