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1/*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
31#include <linux/clk.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
35#include <linux/platform_device.h>
36#include <linux/dma-mapping.h>
37#include <linux/atmel_pdc.h>
38#include <linux/atmel_serial.h>
39#include <linux/uaccess.h>
40
41#include <asm/io.h>
42#include <asm/ioctls.h>
43
44#include <asm/mach/serial_at91.h>
45#include <mach/board.h>
46
47#ifdef CONFIG_ARM
48#include <mach/cpu.h>
49#include <mach/gpio.h>
50#endif
51
52#define PDC_BUFFER_SIZE 512
53/* Revisit: We should calculate this based on the actual port settings */
54#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
62static void atmel_start_rx(struct uart_port *port);
63static void atmel_stop_rx(struct uart_port *port);
64
65#ifdef CONFIG_SERIAL_ATMEL_TTYAT
66
67/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
68 * should coexist with the 8250 driver, such as if we have an external 16C550
69 * UART. */
70#define SERIAL_ATMEL_MAJOR 204
71#define MINOR_START 154
72#define ATMEL_DEVICENAME "ttyAT"
73
74#else
75
76/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
77 * name, but it is legally reserved for the 8250 driver. */
78#define SERIAL_ATMEL_MAJOR TTY_MAJOR
79#define MINOR_START 64
80#define ATMEL_DEVICENAME "ttyS"
81
82#endif
83
84#define ATMEL_ISR_PASS_LIMIT 256
85
86/* UART registers. CR is write-only, hence no GET macro */
87#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
88#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
89#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
90#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
91#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
92#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
93#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
94#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
95#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
96#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
97#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
98#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
99#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
100
101 /* PDC registers */
102#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
103#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
104
105#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
106#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
107#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
108#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
109#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
110
111#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
112#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
113#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
114
115static int (*atmel_open_hook)(struct uart_port *);
116static void (*atmel_close_hook)(struct uart_port *);
117
118struct atmel_dma_buffer {
119 unsigned char *buf;
120 dma_addr_t dma_addr;
121 unsigned int dma_size;
122 unsigned int ofs;
123};
124
125struct atmel_uart_char {
126 u16 status;
127 u16 ch;
128};
129
130#define ATMEL_SERIAL_RINGSIZE 1024
131
132/*
133 * We wrap our port structure around the generic uart_port.
134 */
135struct atmel_uart_port {
136 struct uart_port uart; /* uart */
137 struct clk *clk; /* uart clock */
138 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
139 u32 backup_imr; /* IMR saved during suspend */
140 int break_active; /* break being received */
141
142 short use_dma_rx; /* enable PDC receiver */
143 short pdc_rx_idx; /* current PDC RX buffer */
144 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
145
146 short use_dma_tx; /* enable PDC transmitter */
147 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
148
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152
153 struct circ_buf rx_ring;
154
155 struct serial_rs485 rs485; /* rs485 settings */
156 unsigned int tx_done_mask;
157};
158
159static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
160
161#ifdef SUPPORT_SYSRQ
162static struct console atmel_console;
163#endif
164
165static inline struct atmel_uart_port *
166to_atmel_uart_port(struct uart_port *uart)
167{
168 return container_of(uart, struct atmel_uart_port, uart);
169}
170
171#ifdef CONFIG_SERIAL_ATMEL_PDC
172static bool atmel_use_dma_rx(struct uart_port *port)
173{
174 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
175
176 return atmel_port->use_dma_rx;
177}
178
179static bool atmel_use_dma_tx(struct uart_port *port)
180{
181 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
182
183 return atmel_port->use_dma_tx;
184}
185#else
186static bool atmel_use_dma_rx(struct uart_port *port)
187{
188 return false;
189}
190
191static bool atmel_use_dma_tx(struct uart_port *port)
192{
193 return false;
194}
195#endif
196
197/* Enable or disable the rs485 support */
198void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
199{
200 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
201 unsigned int mode;
202
203 spin_lock(&port->lock);
204
205 /* Disable interrupts */
206 UART_PUT_IDR(port, atmel_port->tx_done_mask);
207
208 mode = UART_GET_MR(port);
209
210 /* Resetting serial mode to RS232 (0x0) */
211 mode &= ~ATMEL_US_USMODE;
212
213 atmel_port->rs485 = *rs485conf;
214
215 if (rs485conf->flags & SER_RS485_ENABLED) {
216 dev_dbg(port->dev, "Setting UART to RS485\n");
217 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
218 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
219 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
220 mode |= ATMEL_US_USMODE_RS485;
221 } else {
222 dev_dbg(port->dev, "Setting UART to RS232\n");
223 if (atmel_use_dma_tx(port))
224 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
225 ATMEL_US_TXBUFE;
226 else
227 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
228 }
229 UART_PUT_MR(port, mode);
230
231 /* Enable interrupts */
232 UART_PUT_IER(port, atmel_port->tx_done_mask);
233
234 spin_unlock(&port->lock);
235
236}
237
238/*
239 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
240 */
241static u_int atmel_tx_empty(struct uart_port *port)
242{
243 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
244}
245
246/*
247 * Set state of the modem control output lines
248 */
249static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
250{
251 unsigned int control = 0;
252 unsigned int mode;
253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
254
255#ifdef CONFIG_ARCH_AT91RM9200
256 if (cpu_is_at91rm9200()) {
257 /*
258 * AT91RM9200 Errata #39: RTS0 is not internally connected
259 * to PA21. We need to drive the pin manually.
260 */
261 if (port->mapbase == AT91RM9200_BASE_US0) {
262 if (mctrl & TIOCM_RTS)
263 at91_set_gpio_value(AT91_PIN_PA21, 0);
264 else
265 at91_set_gpio_value(AT91_PIN_PA21, 1);
266 }
267 }
268#endif
269
270 if (mctrl & TIOCM_RTS)
271 control |= ATMEL_US_RTSEN;
272 else
273 control |= ATMEL_US_RTSDIS;
274
275 if (mctrl & TIOCM_DTR)
276 control |= ATMEL_US_DTREN;
277 else
278 control |= ATMEL_US_DTRDIS;
279
280 UART_PUT_CR(port, control);
281
282 /* Local loopback mode? */
283 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
284 if (mctrl & TIOCM_LOOP)
285 mode |= ATMEL_US_CHMODE_LOC_LOOP;
286 else
287 mode |= ATMEL_US_CHMODE_NORMAL;
288
289 /* Resetting serial mode to RS232 (0x0) */
290 mode &= ~ATMEL_US_USMODE;
291
292 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
293 dev_dbg(port->dev, "Setting UART to RS485\n");
294 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
295 UART_PUT_TTGR(port,
296 atmel_port->rs485.delay_rts_after_send);
297 mode |= ATMEL_US_USMODE_RS485;
298 } else {
299 dev_dbg(port->dev, "Setting UART to RS232\n");
300 }
301 UART_PUT_MR(port, mode);
302}
303
304/*
305 * Get state of the modem control input lines
306 */
307static u_int atmel_get_mctrl(struct uart_port *port)
308{
309 unsigned int status, ret = 0;
310
311 status = UART_GET_CSR(port);
312
313 /*
314 * The control signals are active low.
315 */
316 if (!(status & ATMEL_US_DCD))
317 ret |= TIOCM_CD;
318 if (!(status & ATMEL_US_CTS))
319 ret |= TIOCM_CTS;
320 if (!(status & ATMEL_US_DSR))
321 ret |= TIOCM_DSR;
322 if (!(status & ATMEL_US_RI))
323 ret |= TIOCM_RI;
324
325 return ret;
326}
327
328/*
329 * Stop transmitting.
330 */
331static void atmel_stop_tx(struct uart_port *port)
332{
333 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
334
335 if (atmel_use_dma_tx(port)) {
336 /* disable PDC transmit */
337 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
338 }
339 /* Disable interrupts */
340 UART_PUT_IDR(port, atmel_port->tx_done_mask);
341
342 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
343 atmel_start_rx(port);
344}
345
346/*
347 * Start transmitting.
348 */
349static void atmel_start_tx(struct uart_port *port)
350{
351 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
352
353 if (atmel_use_dma_tx(port)) {
354 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
355 /* The transmitter is already running. Yes, we
356 really need this.*/
357 return;
358
359 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
360 atmel_stop_rx(port);
361
362 /* re-enable PDC transmit */
363 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
364 }
365 /* Enable interrupts */
366 UART_PUT_IER(port, atmel_port->tx_done_mask);
367}
368
369/*
370 * start receiving - port is in process of being opened.
371 */
372static void atmel_start_rx(struct uart_port *port)
373{
374 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
375
376 if (atmel_use_dma_rx(port)) {
377 /* enable PDC controller */
378 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
379 port->read_status_mask);
380 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
381 } else {
382 UART_PUT_IER(port, ATMEL_US_RXRDY);
383 }
384}
385
386/*
387 * Stop receiving - port is in process of being closed.
388 */
389static void atmel_stop_rx(struct uart_port *port)
390{
391 if (atmel_use_dma_rx(port)) {
392 /* disable PDC receive */
393 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
394 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
395 port->read_status_mask);
396 } else {
397 UART_PUT_IDR(port, ATMEL_US_RXRDY);
398 }
399}
400
401/*
402 * Enable modem status interrupts
403 */
404static void atmel_enable_ms(struct uart_port *port)
405{
406 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
407 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
408}
409
410/*
411 * Control the transmission of a break signal
412 */
413static void atmel_break_ctl(struct uart_port *port, int break_state)
414{
415 if (break_state != 0)
416 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
417 else
418 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
419}
420
421/*
422 * Stores the incoming character in the ring buffer
423 */
424static void
425atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
426 unsigned int ch)
427{
428 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
429 struct circ_buf *ring = &atmel_port->rx_ring;
430 struct atmel_uart_char *c;
431
432 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
433 /* Buffer overflow, ignore char */
434 return;
435
436 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
437 c->status = status;
438 c->ch = ch;
439
440 /* Make sure the character is stored before we update head. */
441 smp_wmb();
442
443 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
444}
445
446/*
447 * Deal with parity, framing and overrun errors.
448 */
449static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
450{
451 /* clear error */
452 UART_PUT_CR(port, ATMEL_US_RSTSTA);
453
454 if (status & ATMEL_US_RXBRK) {
455 /* ignore side-effect */
456 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
457 port->icount.brk++;
458 }
459 if (status & ATMEL_US_PARE)
460 port->icount.parity++;
461 if (status & ATMEL_US_FRAME)
462 port->icount.frame++;
463 if (status & ATMEL_US_OVRE)
464 port->icount.overrun++;
465}
466
467/*
468 * Characters received (called from interrupt handler)
469 */
470static void atmel_rx_chars(struct uart_port *port)
471{
472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
473 unsigned int status, ch;
474
475 status = UART_GET_CSR(port);
476 while (status & ATMEL_US_RXRDY) {
477 ch = UART_GET_CHAR(port);
478
479 /*
480 * note that the error handling code is
481 * out of the main execution path
482 */
483 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
484 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
485 || atmel_port->break_active)) {
486
487 /* clear error */
488 UART_PUT_CR(port, ATMEL_US_RSTSTA);
489
490 if (status & ATMEL_US_RXBRK
491 && !atmel_port->break_active) {
492 atmel_port->break_active = 1;
493 UART_PUT_IER(port, ATMEL_US_RXBRK);
494 } else {
495 /*
496 * This is either the end-of-break
497 * condition or we've received at
498 * least one character without RXBRK
499 * being set. In both cases, the next
500 * RXBRK will indicate start-of-break.
501 */
502 UART_PUT_IDR(port, ATMEL_US_RXBRK);
503 status &= ~ATMEL_US_RXBRK;
504 atmel_port->break_active = 0;
505 }
506 }
507
508 atmel_buffer_rx_char(port, status, ch);
509 status = UART_GET_CSR(port);
510 }
511
512 tasklet_schedule(&atmel_port->tasklet);
513}
514
515/*
516 * Transmit characters (called from tasklet with TXRDY interrupt
517 * disabled)
518 */
519static void atmel_tx_chars(struct uart_port *port)
520{
521 struct circ_buf *xmit = &port->state->xmit;
522 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
523
524 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
525 UART_PUT_CHAR(port, port->x_char);
526 port->icount.tx++;
527 port->x_char = 0;
528 }
529 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
530 return;
531
532 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
533 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
534 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
535 port->icount.tx++;
536 if (uart_circ_empty(xmit))
537 break;
538 }
539
540 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
541 uart_write_wakeup(port);
542
543 if (!uart_circ_empty(xmit))
544 /* Enable interrupts */
545 UART_PUT_IER(port, atmel_port->tx_done_mask);
546}
547
548/*
549 * receive interrupt handler.
550 */
551static void
552atmel_handle_receive(struct uart_port *port, unsigned int pending)
553{
554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
555
556 if (atmel_use_dma_rx(port)) {
557 /*
558 * PDC receive. Just schedule the tasklet and let it
559 * figure out the details.
560 *
561 * TODO: We're not handling error flags correctly at
562 * the moment.
563 */
564 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
565 UART_PUT_IDR(port, (ATMEL_US_ENDRX
566 | ATMEL_US_TIMEOUT));
567 tasklet_schedule(&atmel_port->tasklet);
568 }
569
570 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
571 ATMEL_US_FRAME | ATMEL_US_PARE))
572 atmel_pdc_rxerr(port, pending);
573 }
574
575 /* Interrupt receive */
576 if (pending & ATMEL_US_RXRDY)
577 atmel_rx_chars(port);
578 else if (pending & ATMEL_US_RXBRK) {
579 /*
580 * End of break detected. If it came along with a
581 * character, atmel_rx_chars will handle it.
582 */
583 UART_PUT_CR(port, ATMEL_US_RSTSTA);
584 UART_PUT_IDR(port, ATMEL_US_RXBRK);
585 atmel_port->break_active = 0;
586 }
587}
588
589/*
590 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
591 */
592static void
593atmel_handle_transmit(struct uart_port *port, unsigned int pending)
594{
595 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
596
597 if (pending & atmel_port->tx_done_mask) {
598 /* Either PDC or interrupt transmission */
599 UART_PUT_IDR(port, atmel_port->tx_done_mask);
600 tasklet_schedule(&atmel_port->tasklet);
601 }
602}
603
604/*
605 * status flags interrupt handler.
606 */
607static void
608atmel_handle_status(struct uart_port *port, unsigned int pending,
609 unsigned int status)
610{
611 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
612
613 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
614 | ATMEL_US_CTSIC)) {
615 atmel_port->irq_status = status;
616 tasklet_schedule(&atmel_port->tasklet);
617 }
618}
619
620/*
621 * Interrupt handler
622 */
623static irqreturn_t atmel_interrupt(int irq, void *dev_id)
624{
625 struct uart_port *port = dev_id;
626 unsigned int status, pending, pass_counter = 0;
627
628 do {
629 status = UART_GET_CSR(port);
630 pending = status & UART_GET_IMR(port);
631 if (!pending)
632 break;
633
634 atmel_handle_receive(port, pending);
635 atmel_handle_status(port, pending, status);
636 atmel_handle_transmit(port, pending);
637 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
638
639 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
640}
641
642/*
643 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
644 */
645static void atmel_tx_dma(struct uart_port *port)
646{
647 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
648 struct circ_buf *xmit = &port->state->xmit;
649 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
650 int count;
651
652 /* nothing left to transmit? */
653 if (UART_GET_TCR(port))
654 return;
655
656 xmit->tail += pdc->ofs;
657 xmit->tail &= UART_XMIT_SIZE - 1;
658
659 port->icount.tx += pdc->ofs;
660 pdc->ofs = 0;
661
662 /* more to transmit - setup next transfer */
663
664 /* disable PDC transmit */
665 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
666
667 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
668 dma_sync_single_for_device(port->dev,
669 pdc->dma_addr,
670 pdc->dma_size,
671 DMA_TO_DEVICE);
672
673 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
674 pdc->ofs = count;
675
676 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
677 UART_PUT_TCR(port, count);
678 /* re-enable PDC transmit */
679 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
680 /* Enable interrupts */
681 UART_PUT_IER(port, atmel_port->tx_done_mask);
682 } else {
683 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
684 /* DMA done, stop TX, start RX for RS485 */
685 atmel_start_rx(port);
686 }
687 }
688
689 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
690 uart_write_wakeup(port);
691}
692
693static void atmel_rx_from_ring(struct uart_port *port)
694{
695 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
696 struct circ_buf *ring = &atmel_port->rx_ring;
697 unsigned int flg;
698 unsigned int status;
699
700 while (ring->head != ring->tail) {
701 struct atmel_uart_char c;
702
703 /* Make sure c is loaded after head. */
704 smp_rmb();
705
706 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
707
708 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
709
710 port->icount.rx++;
711 status = c.status;
712 flg = TTY_NORMAL;
713
714 /*
715 * note that the error handling code is
716 * out of the main execution path
717 */
718 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
719 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
720 if (status & ATMEL_US_RXBRK) {
721 /* ignore side-effect */
722 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
723
724 port->icount.brk++;
725 if (uart_handle_break(port))
726 continue;
727 }
728 if (status & ATMEL_US_PARE)
729 port->icount.parity++;
730 if (status & ATMEL_US_FRAME)
731 port->icount.frame++;
732 if (status & ATMEL_US_OVRE)
733 port->icount.overrun++;
734
735 status &= port->read_status_mask;
736
737 if (status & ATMEL_US_RXBRK)
738 flg = TTY_BREAK;
739 else if (status & ATMEL_US_PARE)
740 flg = TTY_PARITY;
741 else if (status & ATMEL_US_FRAME)
742 flg = TTY_FRAME;
743 }
744
745
746 if (uart_handle_sysrq_char(port, c.ch))
747 continue;
748
749 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
750 }
751
752 /*
753 * Drop the lock here since it might end up calling
754 * uart_start(), which takes the lock.
755 */
756 spin_unlock(&port->lock);
757 tty_flip_buffer_push(port->state->port.tty);
758 spin_lock(&port->lock);
759}
760
761static void atmel_rx_from_dma(struct uart_port *port)
762{
763 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
764 struct tty_struct *tty = port->state->port.tty;
765 struct atmel_dma_buffer *pdc;
766 int rx_idx = atmel_port->pdc_rx_idx;
767 unsigned int head;
768 unsigned int tail;
769 unsigned int count;
770
771 do {
772 /* Reset the UART timeout early so that we don't miss one */
773 UART_PUT_CR(port, ATMEL_US_STTTO);
774
775 pdc = &atmel_port->pdc_rx[rx_idx];
776 head = UART_GET_RPR(port) - pdc->dma_addr;
777 tail = pdc->ofs;
778
779 /* If the PDC has switched buffers, RPR won't contain
780 * any address within the current buffer. Since head
781 * is unsigned, we just need a one-way comparison to
782 * find out.
783 *
784 * In this case, we just need to consume the entire
785 * buffer and resubmit it for DMA. This will clear the
786 * ENDRX bit as well, so that we can safely re-enable
787 * all interrupts below.
788 */
789 head = min(head, pdc->dma_size);
790
791 if (likely(head != tail)) {
792 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
793 pdc->dma_size, DMA_FROM_DEVICE);
794
795 /*
796 * head will only wrap around when we recycle
797 * the DMA buffer, and when that happens, we
798 * explicitly set tail to 0. So head will
799 * always be greater than tail.
800 */
801 count = head - tail;
802
803 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
804
805 dma_sync_single_for_device(port->dev, pdc->dma_addr,
806 pdc->dma_size, DMA_FROM_DEVICE);
807
808 port->icount.rx += count;
809 pdc->ofs = head;
810 }
811
812 /*
813 * If the current buffer is full, we need to check if
814 * the next one contains any additional data.
815 */
816 if (head >= pdc->dma_size) {
817 pdc->ofs = 0;
818 UART_PUT_RNPR(port, pdc->dma_addr);
819 UART_PUT_RNCR(port, pdc->dma_size);
820
821 rx_idx = !rx_idx;
822 atmel_port->pdc_rx_idx = rx_idx;
823 }
824 } while (head >= pdc->dma_size);
825
826 /*
827 * Drop the lock here since it might end up calling
828 * uart_start(), which takes the lock.
829 */
830 spin_unlock(&port->lock);
831 tty_flip_buffer_push(tty);
832 spin_lock(&port->lock);
833
834 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
835}
836
837/*
838 * tasklet handling tty stuff outside the interrupt handler.
839 */
840static void atmel_tasklet_func(unsigned long data)
841{
842 struct uart_port *port = (struct uart_port *)data;
843 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
844 unsigned int status;
845 unsigned int status_change;
846
847 /* The interrupt handler does not take the lock */
848 spin_lock(&port->lock);
849
850 if (atmel_use_dma_tx(port))
851 atmel_tx_dma(port);
852 else
853 atmel_tx_chars(port);
854
855 status = atmel_port->irq_status;
856 status_change = status ^ atmel_port->irq_status_prev;
857
858 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
859 | ATMEL_US_DCD | ATMEL_US_CTS)) {
860 /* TODO: All reads to CSR will clear these interrupts! */
861 if (status_change & ATMEL_US_RI)
862 port->icount.rng++;
863 if (status_change & ATMEL_US_DSR)
864 port->icount.dsr++;
865 if (status_change & ATMEL_US_DCD)
866 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
867 if (status_change & ATMEL_US_CTS)
868 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
869
870 wake_up_interruptible(&port->state->port.delta_msr_wait);
871
872 atmel_port->irq_status_prev = status;
873 }
874
875 if (atmel_use_dma_rx(port))
876 atmel_rx_from_dma(port);
877 else
878 atmel_rx_from_ring(port);
879
880 spin_unlock(&port->lock);
881}
882
883/*
884 * Perform initialization and enable port for reception
885 */
886static int atmel_startup(struct uart_port *port)
887{
888 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
889 struct tty_struct *tty = port->state->port.tty;
890 int retval;
891
892 /*
893 * Ensure that no interrupts are enabled otherwise when
894 * request_irq() is called we could get stuck trying to
895 * handle an unexpected interrupt
896 */
897 UART_PUT_IDR(port, -1);
898
899 /*
900 * Allocate the IRQ
901 */
902 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
903 tty ? tty->name : "atmel_serial", port);
904 if (retval) {
905 printk("atmel_serial: atmel_startup - Can't get irq\n");
906 return retval;
907 }
908
909 /*
910 * Initialize DMA (if necessary)
911 */
912 if (atmel_use_dma_rx(port)) {
913 int i;
914
915 for (i = 0; i < 2; i++) {
916 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
917
918 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
919 if (pdc->buf == NULL) {
920 if (i != 0) {
921 dma_unmap_single(port->dev,
922 atmel_port->pdc_rx[0].dma_addr,
923 PDC_BUFFER_SIZE,
924 DMA_FROM_DEVICE);
925 kfree(atmel_port->pdc_rx[0].buf);
926 }
927 free_irq(port->irq, port);
928 return -ENOMEM;
929 }
930 pdc->dma_addr = dma_map_single(port->dev,
931 pdc->buf,
932 PDC_BUFFER_SIZE,
933 DMA_FROM_DEVICE);
934 pdc->dma_size = PDC_BUFFER_SIZE;
935 pdc->ofs = 0;
936 }
937
938 atmel_port->pdc_rx_idx = 0;
939
940 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
941 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
942
943 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
944 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
945 }
946 if (atmel_use_dma_tx(port)) {
947 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
948 struct circ_buf *xmit = &port->state->xmit;
949
950 pdc->buf = xmit->buf;
951 pdc->dma_addr = dma_map_single(port->dev,
952 pdc->buf,
953 UART_XMIT_SIZE,
954 DMA_TO_DEVICE);
955 pdc->dma_size = UART_XMIT_SIZE;
956 pdc->ofs = 0;
957 }
958
959 /*
960 * If there is a specific "open" function (to register
961 * control line interrupts)
962 */
963 if (atmel_open_hook) {
964 retval = atmel_open_hook(port);
965 if (retval) {
966 free_irq(port->irq, port);
967 return retval;
968 }
969 }
970
971 /* Save current CSR for comparison in atmel_tasklet_func() */
972 atmel_port->irq_status_prev = UART_GET_CSR(port);
973 atmel_port->irq_status = atmel_port->irq_status_prev;
974
975 /*
976 * Finally, enable the serial port
977 */
978 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
979 /* enable xmit & rcvr */
980 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
981
982 if (atmel_use_dma_rx(port)) {
983 /* set UART timeout */
984 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
985 UART_PUT_CR(port, ATMEL_US_STTTO);
986
987 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
988 /* enable PDC controller */
989 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
990 } else {
991 /* enable receive only */
992 UART_PUT_IER(port, ATMEL_US_RXRDY);
993 }
994
995 return 0;
996}
997
998/*
999 * Disable the port
1000 */
1001static void atmel_shutdown(struct uart_port *port)
1002{
1003 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1004 /*
1005 * Ensure everything is stopped.
1006 */
1007 atmel_stop_rx(port);
1008 atmel_stop_tx(port);
1009
1010 /*
1011 * Shut-down the DMA.
1012 */
1013 if (atmel_use_dma_rx(port)) {
1014 int i;
1015
1016 for (i = 0; i < 2; i++) {
1017 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1018
1019 dma_unmap_single(port->dev,
1020 pdc->dma_addr,
1021 pdc->dma_size,
1022 DMA_FROM_DEVICE);
1023 kfree(pdc->buf);
1024 }
1025 }
1026 if (atmel_use_dma_tx(port)) {
1027 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1028
1029 dma_unmap_single(port->dev,
1030 pdc->dma_addr,
1031 pdc->dma_size,
1032 DMA_TO_DEVICE);
1033 }
1034
1035 /*
1036 * Disable all interrupts, port and break condition.
1037 */
1038 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1039 UART_PUT_IDR(port, -1);
1040
1041 /*
1042 * Free the interrupt
1043 */
1044 free_irq(port->irq, port);
1045
1046 /*
1047 * If there is a specific "close" function (to unregister
1048 * control line interrupts)
1049 */
1050 if (atmel_close_hook)
1051 atmel_close_hook(port);
1052}
1053
1054/*
1055 * Flush any TX data submitted for DMA. Called when the TX circular
1056 * buffer is reset.
1057 */
1058static void atmel_flush_buffer(struct uart_port *port)
1059{
1060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1061
1062 if (atmel_use_dma_tx(port)) {
1063 UART_PUT_TCR(port, 0);
1064 atmel_port->pdc_tx.ofs = 0;
1065 }
1066}
1067
1068/*
1069 * Power / Clock management.
1070 */
1071static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1072 unsigned int oldstate)
1073{
1074 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1075
1076 switch (state) {
1077 case 0:
1078 /*
1079 * Enable the peripheral clock for this serial port.
1080 * This is called on uart_open() or a resume event.
1081 */
1082 clk_enable(atmel_port->clk);
1083
1084 /* re-enable interrupts if we disabled some on suspend */
1085 UART_PUT_IER(port, atmel_port->backup_imr);
1086 break;
1087 case 3:
1088 /* Back up the interrupt mask and disable all interrupts */
1089 atmel_port->backup_imr = UART_GET_IMR(port);
1090 UART_PUT_IDR(port, -1);
1091
1092 /*
1093 * Disable the peripheral clock for this serial port.
1094 * This is called on uart_close() or a suspend event.
1095 */
1096 clk_disable(atmel_port->clk);
1097 break;
1098 default:
1099 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1100 }
1101}
1102
1103/*
1104 * Change the port parameters
1105 */
1106static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1107 struct ktermios *old)
1108{
1109 unsigned long flags;
1110 unsigned int mode, imr, quot, baud;
1111 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1112
1113 /* Get current mode register */
1114 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1115 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1116 | ATMEL_US_USMODE);
1117
1118 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1119 quot = uart_get_divisor(port, baud);
1120
1121 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1122 quot /= 8;
1123 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1124 }
1125
1126 /* byte size */
1127 switch (termios->c_cflag & CSIZE) {
1128 case CS5:
1129 mode |= ATMEL_US_CHRL_5;
1130 break;
1131 case CS6:
1132 mode |= ATMEL_US_CHRL_6;
1133 break;
1134 case CS7:
1135 mode |= ATMEL_US_CHRL_7;
1136 break;
1137 default:
1138 mode |= ATMEL_US_CHRL_8;
1139 break;
1140 }
1141
1142 /* stop bits */
1143 if (termios->c_cflag & CSTOPB)
1144 mode |= ATMEL_US_NBSTOP_2;
1145
1146 /* parity */
1147 if (termios->c_cflag & PARENB) {
1148 /* Mark or Space parity */
1149 if (termios->c_cflag & CMSPAR) {
1150 if (termios->c_cflag & PARODD)
1151 mode |= ATMEL_US_PAR_MARK;
1152 else
1153 mode |= ATMEL_US_PAR_SPACE;
1154 } else if (termios->c_cflag & PARODD)
1155 mode |= ATMEL_US_PAR_ODD;
1156 else
1157 mode |= ATMEL_US_PAR_EVEN;
1158 } else
1159 mode |= ATMEL_US_PAR_NONE;
1160
1161 /* hardware handshake (RTS/CTS) */
1162 if (termios->c_cflag & CRTSCTS)
1163 mode |= ATMEL_US_USMODE_HWHS;
1164 else
1165 mode |= ATMEL_US_USMODE_NORMAL;
1166
1167 spin_lock_irqsave(&port->lock, flags);
1168
1169 port->read_status_mask = ATMEL_US_OVRE;
1170 if (termios->c_iflag & INPCK)
1171 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1172 if (termios->c_iflag & (BRKINT | PARMRK))
1173 port->read_status_mask |= ATMEL_US_RXBRK;
1174
1175 if (atmel_use_dma_rx(port))
1176 /* need to enable error interrupts */
1177 UART_PUT_IER(port, port->read_status_mask);
1178
1179 /*
1180 * Characters to ignore
1181 */
1182 port->ignore_status_mask = 0;
1183 if (termios->c_iflag & IGNPAR)
1184 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1185 if (termios->c_iflag & IGNBRK) {
1186 port->ignore_status_mask |= ATMEL_US_RXBRK;
1187 /*
1188 * If we're ignoring parity and break indicators,
1189 * ignore overruns too (for real raw support).
1190 */
1191 if (termios->c_iflag & IGNPAR)
1192 port->ignore_status_mask |= ATMEL_US_OVRE;
1193 }
1194 /* TODO: Ignore all characters if CREAD is set.*/
1195
1196 /* update the per-port timeout */
1197 uart_update_timeout(port, termios->c_cflag, baud);
1198
1199 /*
1200 * save/disable interrupts. The tty layer will ensure that the
1201 * transmitter is empty if requested by the caller, so there's
1202 * no need to wait for it here.
1203 */
1204 imr = UART_GET_IMR(port);
1205 UART_PUT_IDR(port, -1);
1206
1207 /* disable receiver and transmitter */
1208 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1209
1210 /* Resetting serial mode to RS232 (0x0) */
1211 mode &= ~ATMEL_US_USMODE;
1212
1213 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1214 dev_dbg(port->dev, "Setting UART to RS485\n");
1215 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1216 UART_PUT_TTGR(port,
1217 atmel_port->rs485.delay_rts_after_send);
1218 mode |= ATMEL_US_USMODE_RS485;
1219 } else {
1220 dev_dbg(port->dev, "Setting UART to RS232\n");
1221 }
1222
1223 /* set the parity, stop bits and data size */
1224 UART_PUT_MR(port, mode);
1225
1226 /* set the baud rate */
1227 UART_PUT_BRGR(port, quot);
1228 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1229 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1230
1231 /* restore interrupts */
1232 UART_PUT_IER(port, imr);
1233
1234 /* CTS flow-control and modem-status interrupts */
1235 if (UART_ENABLE_MS(port, termios->c_cflag))
1236 port->ops->enable_ms(port);
1237
1238 spin_unlock_irqrestore(&port->lock, flags);
1239}
1240
1241static void atmel_set_ldisc(struct uart_port *port, int new)
1242{
1243 int line = port->line;
1244
1245 if (line >= port->state->port.tty->driver->num)
1246 return;
1247
1248 if (port->state->port.tty->ldisc->ops->num == N_PPS) {
1249 port->flags |= UPF_HARDPPS_CD;
1250 atmel_enable_ms(port);
1251 } else {
1252 port->flags &= ~UPF_HARDPPS_CD;
1253 }
1254}
1255
1256/*
1257 * Return string describing the specified port
1258 */
1259static const char *atmel_type(struct uart_port *port)
1260{
1261 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1262}
1263
1264/*
1265 * Release the memory region(s) being used by 'port'.
1266 */
1267static void atmel_release_port(struct uart_port *port)
1268{
1269 struct platform_device *pdev = to_platform_device(port->dev);
1270 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1271
1272 release_mem_region(port->mapbase, size);
1273
1274 if (port->flags & UPF_IOREMAP) {
1275 iounmap(port->membase);
1276 port->membase = NULL;
1277 }
1278}
1279
1280/*
1281 * Request the memory region(s) being used by 'port'.
1282 */
1283static int atmel_request_port(struct uart_port *port)
1284{
1285 struct platform_device *pdev = to_platform_device(port->dev);
1286 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1287
1288 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1289 return -EBUSY;
1290
1291 if (port->flags & UPF_IOREMAP) {
1292 port->membase = ioremap(port->mapbase, size);
1293 if (port->membase == NULL) {
1294 release_mem_region(port->mapbase, size);
1295 return -ENOMEM;
1296 }
1297 }
1298
1299 return 0;
1300}
1301
1302/*
1303 * Configure/autoconfigure the port.
1304 */
1305static void atmel_config_port(struct uart_port *port, int flags)
1306{
1307 if (flags & UART_CONFIG_TYPE) {
1308 port->type = PORT_ATMEL;
1309 atmel_request_port(port);
1310 }
1311}
1312
1313/*
1314 * Verify the new serial_struct (for TIOCSSERIAL).
1315 */
1316static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1317{
1318 int ret = 0;
1319 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1320 ret = -EINVAL;
1321 if (port->irq != ser->irq)
1322 ret = -EINVAL;
1323 if (ser->io_type != SERIAL_IO_MEM)
1324 ret = -EINVAL;
1325 if (port->uartclk / 16 != ser->baud_base)
1326 ret = -EINVAL;
1327 if ((void *)port->mapbase != ser->iomem_base)
1328 ret = -EINVAL;
1329 if (port->iobase != ser->port)
1330 ret = -EINVAL;
1331 if (ser->hub6 != 0)
1332 ret = -EINVAL;
1333 return ret;
1334}
1335
1336#ifdef CONFIG_CONSOLE_POLL
1337static int atmel_poll_get_char(struct uart_port *port)
1338{
1339 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1340 cpu_relax();
1341
1342 return UART_GET_CHAR(port);
1343}
1344
1345static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1346{
1347 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1348 cpu_relax();
1349
1350 UART_PUT_CHAR(port, ch);
1351}
1352#endif
1353
1354static int
1355atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1356{
1357 struct serial_rs485 rs485conf;
1358
1359 switch (cmd) {
1360 case TIOCSRS485:
1361 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1362 sizeof(rs485conf)))
1363 return -EFAULT;
1364
1365 atmel_config_rs485(port, &rs485conf);
1366 break;
1367
1368 case TIOCGRS485:
1369 if (copy_to_user((struct serial_rs485 *) arg,
1370 &(to_atmel_uart_port(port)->rs485),
1371 sizeof(rs485conf)))
1372 return -EFAULT;
1373 break;
1374
1375 default:
1376 return -ENOIOCTLCMD;
1377 }
1378 return 0;
1379}
1380
1381
1382
1383static struct uart_ops atmel_pops = {
1384 .tx_empty = atmel_tx_empty,
1385 .set_mctrl = atmel_set_mctrl,
1386 .get_mctrl = atmel_get_mctrl,
1387 .stop_tx = atmel_stop_tx,
1388 .start_tx = atmel_start_tx,
1389 .stop_rx = atmel_stop_rx,
1390 .enable_ms = atmel_enable_ms,
1391 .break_ctl = atmel_break_ctl,
1392 .startup = atmel_startup,
1393 .shutdown = atmel_shutdown,
1394 .flush_buffer = atmel_flush_buffer,
1395 .set_termios = atmel_set_termios,
1396 .set_ldisc = atmel_set_ldisc,
1397 .type = atmel_type,
1398 .release_port = atmel_release_port,
1399 .request_port = atmel_request_port,
1400 .config_port = atmel_config_port,
1401 .verify_port = atmel_verify_port,
1402 .pm = atmel_serial_pm,
1403 .ioctl = atmel_ioctl,
1404#ifdef CONFIG_CONSOLE_POLL
1405 .poll_get_char = atmel_poll_get_char,
1406 .poll_put_char = atmel_poll_put_char,
1407#endif
1408};
1409
1410/*
1411 * Configure the port from the platform device resource info.
1412 */
1413static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1414 struct platform_device *pdev)
1415{
1416 struct uart_port *port = &atmel_port->uart;
1417 struct atmel_uart_data *data = pdev->dev.platform_data;
1418
1419 port->iotype = UPIO_MEM;
1420 port->flags = UPF_BOOT_AUTOCONF;
1421 port->ops = &atmel_pops;
1422 port->fifosize = 1;
1423 port->line = data->num;
1424 port->dev = &pdev->dev;
1425 port->mapbase = pdev->resource[0].start;
1426 port->irq = pdev->resource[1].start;
1427
1428 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1429 (unsigned long)port);
1430
1431 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1432
1433 if (data->regs)
1434 /* Already mapped by setup code */
1435 port->membase = data->regs;
1436 else {
1437 port->flags |= UPF_IOREMAP;
1438 port->membase = NULL;
1439 }
1440
1441 /* for console, the clock could already be configured */
1442 if (!atmel_port->clk) {
1443 atmel_port->clk = clk_get(&pdev->dev, "usart");
1444 clk_enable(atmel_port->clk);
1445 port->uartclk = clk_get_rate(atmel_port->clk);
1446 clk_disable(atmel_port->clk);
1447 /* only enable clock when USART is in use */
1448 }
1449
1450 atmel_port->use_dma_rx = data->use_dma_rx;
1451 atmel_port->use_dma_tx = data->use_dma_tx;
1452 atmel_port->rs485 = data->rs485;
1453 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
1454 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
1455 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
1456 else if (atmel_use_dma_tx(port)) {
1457 port->fifosize = PDC_BUFFER_SIZE;
1458 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
1459 } else {
1460 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
1461 }
1462}
1463
1464/*
1465 * Register board-specific modem-control line handlers.
1466 */
1467void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1468{
1469 if (fns->enable_ms)
1470 atmel_pops.enable_ms = fns->enable_ms;
1471 if (fns->get_mctrl)
1472 atmel_pops.get_mctrl = fns->get_mctrl;
1473 if (fns->set_mctrl)
1474 atmel_pops.set_mctrl = fns->set_mctrl;
1475 atmel_open_hook = fns->open;
1476 atmel_close_hook = fns->close;
1477 atmel_pops.pm = fns->pm;
1478 atmel_pops.set_wake = fns->set_wake;
1479}
1480
1481#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1482static void atmel_console_putchar(struct uart_port *port, int ch)
1483{
1484 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1485 cpu_relax();
1486 UART_PUT_CHAR(port, ch);
1487}
1488
1489/*
1490 * Interrupts are disabled on entering
1491 */
1492static void atmel_console_write(struct console *co, const char *s, u_int count)
1493{
1494 struct uart_port *port = &atmel_ports[co->index].uart;
1495 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1496 unsigned int status, imr;
1497 unsigned int pdc_tx;
1498
1499 /*
1500 * First, save IMR and then disable interrupts
1501 */
1502 imr = UART_GET_IMR(port);
1503 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1504
1505 /* Store PDC transmit status and disable it */
1506 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1507 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1508
1509 uart_console_write(port, s, count, atmel_console_putchar);
1510
1511 /*
1512 * Finally, wait for transmitter to become empty
1513 * and restore IMR
1514 */
1515 do {
1516 status = UART_GET_CSR(port);
1517 } while (!(status & ATMEL_US_TXRDY));
1518
1519 /* Restore PDC transmit status */
1520 if (pdc_tx)
1521 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1522
1523 /* set interrupts back the way they were */
1524 UART_PUT_IER(port, imr);
1525}
1526
1527/*
1528 * If the port was already initialised (eg, by a boot loader),
1529 * try to determine the current setup.
1530 */
1531static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1532 int *parity, int *bits)
1533{
1534 unsigned int mr, quot;
1535
1536 /*
1537 * If the baud rate generator isn't running, the port wasn't
1538 * initialized by the boot loader.
1539 */
1540 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1541 if (!quot)
1542 return;
1543
1544 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1545 if (mr == ATMEL_US_CHRL_8)
1546 *bits = 8;
1547 else
1548 *bits = 7;
1549
1550 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1551 if (mr == ATMEL_US_PAR_EVEN)
1552 *parity = 'e';
1553 else if (mr == ATMEL_US_PAR_ODD)
1554 *parity = 'o';
1555
1556 /*
1557 * The serial core only rounds down when matching this to a
1558 * supported baud rate. Make sure we don't end up slightly
1559 * lower than one of those, as it would make us fall through
1560 * to a much lower baud rate than we really want.
1561 */
1562 *baud = port->uartclk / (16 * (quot - 1));
1563}
1564
1565static int __init atmel_console_setup(struct console *co, char *options)
1566{
1567 struct uart_port *port = &atmel_ports[co->index].uart;
1568 int baud = 115200;
1569 int bits = 8;
1570 int parity = 'n';
1571 int flow = 'n';
1572
1573 if (port->membase == NULL) {
1574 /* Port not initialized yet - delay setup */
1575 return -ENODEV;
1576 }
1577
1578 clk_enable(atmel_ports[co->index].clk);
1579
1580 UART_PUT_IDR(port, -1);
1581 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1582 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1583
1584 if (options)
1585 uart_parse_options(options, &baud, &parity, &bits, &flow);
1586 else
1587 atmel_console_get_options(port, &baud, &parity, &bits);
1588
1589 return uart_set_options(port, co, baud, parity, bits, flow);
1590}
1591
1592static struct uart_driver atmel_uart;
1593
1594static struct console atmel_console = {
1595 .name = ATMEL_DEVICENAME,
1596 .write = atmel_console_write,
1597 .device = uart_console_device,
1598 .setup = atmel_console_setup,
1599 .flags = CON_PRINTBUFFER,
1600 .index = -1,
1601 .data = &atmel_uart,
1602};
1603
1604#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1605
1606/*
1607 * Early console initialization (before VM subsystem initialized).
1608 */
1609static int __init atmel_console_init(void)
1610{
1611 if (atmel_default_console_device) {
1612 struct atmel_uart_data *pdata =
1613 atmel_default_console_device->dev.platform_data;
1614
1615 add_preferred_console(ATMEL_DEVICENAME, pdata->num, NULL);
1616 atmel_init_port(&atmel_ports[pdata->num],
1617 atmel_default_console_device);
1618 register_console(&atmel_console);
1619 }
1620
1621 return 0;
1622}
1623
1624console_initcall(atmel_console_init);
1625
1626/*
1627 * Late console initialization.
1628 */
1629static int __init atmel_late_console_init(void)
1630{
1631 if (atmel_default_console_device
1632 && !(atmel_console.flags & CON_ENABLED))
1633 register_console(&atmel_console);
1634
1635 return 0;
1636}
1637
1638core_initcall(atmel_late_console_init);
1639
1640static inline bool atmel_is_console_port(struct uart_port *port)
1641{
1642 return port->cons && port->cons->index == port->line;
1643}
1644
1645#else
1646#define ATMEL_CONSOLE_DEVICE NULL
1647
1648static inline bool atmel_is_console_port(struct uart_port *port)
1649{
1650 return false;
1651}
1652#endif
1653
1654static struct uart_driver atmel_uart = {
1655 .owner = THIS_MODULE,
1656 .driver_name = "atmel_serial",
1657 .dev_name = ATMEL_DEVICENAME,
1658 .major = SERIAL_ATMEL_MAJOR,
1659 .minor = MINOR_START,
1660 .nr = ATMEL_MAX_UART,
1661 .cons = ATMEL_CONSOLE_DEVICE,
1662};
1663
1664#ifdef CONFIG_PM
1665static bool atmel_serial_clk_will_stop(void)
1666{
1667#ifdef CONFIG_ARCH_AT91
1668 return at91_suspend_entering_slow_clock();
1669#else
1670 return false;
1671#endif
1672}
1673
1674static int atmel_serial_suspend(struct platform_device *pdev,
1675 pm_message_t state)
1676{
1677 struct uart_port *port = platform_get_drvdata(pdev);
1678 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1679
1680 if (atmel_is_console_port(port) && console_suspend_enabled) {
1681 /* Drain the TX shifter */
1682 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1683 cpu_relax();
1684 }
1685
1686 /* we can not wake up if we're running on slow clock */
1687 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
1688 if (atmel_serial_clk_will_stop())
1689 device_set_wakeup_enable(&pdev->dev, 0);
1690
1691 uart_suspend_port(&atmel_uart, port);
1692
1693 return 0;
1694}
1695
1696static int atmel_serial_resume(struct platform_device *pdev)
1697{
1698 struct uart_port *port = platform_get_drvdata(pdev);
1699 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1700
1701 uart_resume_port(&atmel_uart, port);
1702 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1703
1704 return 0;
1705}
1706#else
1707#define atmel_serial_suspend NULL
1708#define atmel_serial_resume NULL
1709#endif
1710
1711static int __devinit atmel_serial_probe(struct platform_device *pdev)
1712{
1713 struct atmel_uart_port *port;
1714 struct atmel_uart_data *pdata = pdev->dev.platform_data;
1715 void *data;
1716 int ret;
1717
1718 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1719
1720 port = &atmel_ports[pdata->num];
1721 port->backup_imr = 0;
1722
1723 atmel_init_port(port, pdev);
1724
1725 if (!atmel_use_dma_rx(&port->uart)) {
1726 ret = -ENOMEM;
1727 data = kmalloc(sizeof(struct atmel_uart_char)
1728 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
1729 if (!data)
1730 goto err_alloc_ring;
1731 port->rx_ring.buf = data;
1732 }
1733
1734 ret = uart_add_one_port(&atmel_uart, &port->uart);
1735 if (ret)
1736 goto err_add_port;
1737
1738#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1739 if (atmel_is_console_port(&port->uart)
1740 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1741 /*
1742 * The serial core enabled the clock for us, so undo
1743 * the clk_enable() in atmel_console_setup()
1744 */
1745 clk_disable(port->clk);
1746 }
1747#endif
1748
1749 device_init_wakeup(&pdev->dev, 1);
1750 platform_set_drvdata(pdev, port);
1751
1752 if (port->rs485.flags & SER_RS485_ENABLED) {
1753 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
1754 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
1755 }
1756
1757 return 0;
1758
1759err_add_port:
1760 kfree(port->rx_ring.buf);
1761 port->rx_ring.buf = NULL;
1762err_alloc_ring:
1763 if (!atmel_is_console_port(&port->uart)) {
1764 clk_put(port->clk);
1765 port->clk = NULL;
1766 }
1767
1768 return ret;
1769}
1770
1771static int __devexit atmel_serial_remove(struct platform_device *pdev)
1772{
1773 struct uart_port *port = platform_get_drvdata(pdev);
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1775 int ret = 0;
1776
1777 device_init_wakeup(&pdev->dev, 0);
1778 platform_set_drvdata(pdev, NULL);
1779
1780 ret = uart_remove_one_port(&atmel_uart, port);
1781
1782 tasklet_kill(&atmel_port->tasklet);
1783 kfree(atmel_port->rx_ring.buf);
1784
1785 /* "port" is allocated statically, so we shouldn't free it */
1786
1787 clk_put(atmel_port->clk);
1788
1789 return ret;
1790}
1791
1792static struct platform_driver atmel_serial_driver = {
1793 .probe = atmel_serial_probe,
1794 .remove = __devexit_p(atmel_serial_remove),
1795 .suspend = atmel_serial_suspend,
1796 .resume = atmel_serial_resume,
1797 .driver = {
1798 .name = "atmel_usart",
1799 .owner = THIS_MODULE,
1800 },
1801};
1802
1803static int __init atmel_serial_init(void)
1804{
1805 int ret;
1806
1807 ret = uart_register_driver(&atmel_uart);
1808 if (ret)
1809 return ret;
1810
1811 ret = platform_driver_register(&atmel_serial_driver);
1812 if (ret)
1813 uart_unregister_driver(&atmel_uart);
1814
1815 return ret;
1816}
1817
1818static void __exit atmel_serial_exit(void)
1819{
1820 platform_driver_unregister(&atmel_serial_driver);
1821 uart_unregister_driver(&atmel_uart);
1822}
1823
1824module_init(atmel_serial_init);
1825module_exit(atmel_serial_exit);
1826
1827MODULE_AUTHOR("Rick Bronson");
1828MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1829MODULE_LICENSE("GPL");
1830MODULE_ALIAS("platform:atmel_usart");
1/*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
30#include <linux/clk.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
34#include <linux/platform_device.h>
35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/of_gpio.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40#include <linux/atmel_pdc.h>
41#include <linux/atmel_serial.h>
42#include <linux/uaccess.h>
43#include <linux/platform_data/atmel.h>
44#include <linux/timer.h>
45#include <linux/gpio.h>
46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
48#include <linux/irq.h>
49#include <linux/suspend.h>
50
51#include <asm/io.h>
52#include <asm/ioctls.h>
53
54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
73#include "serial_mctrl_gpio.h"
74
75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
83#define SERIAL_ATMEL_MAJOR 204
84#define MINOR_START 154
85#define ATMEL_DEVICENAME "ttyAT"
86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
92#define MINOR_START 64
93#define ATMEL_DEVICENAME "ttyS"
94
95#endif
96
97#define ATMEL_ISR_PASS_LIMIT 256
98
99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
111/*
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115 * DMA mode.
116 */
117#define ATMEL_SERIAL_RINGSIZE 1024
118
119/*
120 * at91: 6 USARTs and one DBGU port (SAM9260)
121 * avr32: 4
122 */
123#define ATMEL_MAX_UART 7
124
125/*
126 * We wrap our port structure around the generic uart_port.
127 */
128struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
134
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
143
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
158 unsigned int tx_len;
159
160 struct circ_buf rx_ring;
161
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
164 u32 fifo_size;
165 u32 rts_high;
166 u32 rts_low;
167 bool ms_irq_enabled;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
170 bool has_hw_timer;
171 struct timer_list uart_timer;
172
173 bool suspended;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
177
178 int (*prepare_rx)(struct uart_port *port);
179 int (*prepare_tx)(struct uart_port *port);
180 void (*schedule_rx)(struct uart_port *port);
181 void (*schedule_tx)(struct uart_port *port);
182 void (*release_rx)(struct uart_port *port);
183 void (*release_tx)(struct uart_port *port);
184};
185
186static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
187static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
188
189#ifdef SUPPORT_SYSRQ
190static struct console atmel_console;
191#endif
192
193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart" },
196 { .compatible = "atmel,at91sam9260-usart" },
197 { /* sentinel */ }
198};
199#endif
200
201static inline struct atmel_uart_port *
202to_atmel_uart_port(struct uart_port *uart)
203{
204 return container_of(uart, struct atmel_uart_port, uart);
205}
206
207static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208{
209 return __raw_readl(port->membase + reg);
210}
211
212static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213{
214 __raw_writel(value, port->membase + reg);
215}
216
217#ifdef CONFIG_AVR32
218
219/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
220static inline u8 atmel_uart_read_char(struct uart_port *port)
221{
222 return __raw_readl(port->membase + ATMEL_US_RHR);
223}
224
225static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
226{
227 __raw_writel(value, port->membase + ATMEL_US_THR);
228}
229
230#else
231
232static inline u8 atmel_uart_read_char(struct uart_port *port)
233{
234 return __raw_readb(port->membase + ATMEL_US_RHR);
235}
236
237static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
238{
239 __raw_writeb(value, port->membase + ATMEL_US_THR);
240}
241
242#endif
243
244#ifdef CONFIG_SERIAL_ATMEL_PDC
245static bool atmel_use_pdc_rx(struct uart_port *port)
246{
247 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248
249 return atmel_port->use_pdc_rx;
250}
251
252static bool atmel_use_pdc_tx(struct uart_port *port)
253{
254 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
255
256 return atmel_port->use_pdc_tx;
257}
258#else
259static bool atmel_use_pdc_rx(struct uart_port *port)
260{
261 return false;
262}
263
264static bool atmel_use_pdc_tx(struct uart_port *port)
265{
266 return false;
267}
268#endif
269
270static bool atmel_use_dma_tx(struct uart_port *port)
271{
272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273
274 return atmel_port->use_dma_tx;
275}
276
277static bool atmel_use_dma_rx(struct uart_port *port)
278{
279 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
280
281 return atmel_port->use_dma_rx;
282}
283
284static bool atmel_use_fifo(struct uart_port *port)
285{
286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
287
288 return atmel_port->fifo_size;
289}
290
291static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
292 struct tasklet_struct *t)
293{
294 if (!atomic_read(&atmel_port->tasklet_shutdown))
295 tasklet_schedule(t);
296}
297
298static unsigned int atmel_get_lines_status(struct uart_port *port)
299{
300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
301 unsigned int status, ret = 0;
302
303 status = atmel_uart_readl(port, ATMEL_US_CSR);
304
305 mctrl_gpio_get(atmel_port->gpios, &ret);
306
307 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
308 UART_GPIO_CTS))) {
309 if (ret & TIOCM_CTS)
310 status &= ~ATMEL_US_CTS;
311 else
312 status |= ATMEL_US_CTS;
313 }
314
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
316 UART_GPIO_DSR))) {
317 if (ret & TIOCM_DSR)
318 status &= ~ATMEL_US_DSR;
319 else
320 status |= ATMEL_US_DSR;
321 }
322
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 UART_GPIO_RI))) {
325 if (ret & TIOCM_RI)
326 status &= ~ATMEL_US_RI;
327 else
328 status |= ATMEL_US_RI;
329 }
330
331 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
332 UART_GPIO_DCD))) {
333 if (ret & TIOCM_CD)
334 status &= ~ATMEL_US_DCD;
335 else
336 status |= ATMEL_US_DCD;
337 }
338
339 return status;
340}
341
342/* Enable or disable the rs485 support */
343static int atmel_config_rs485(struct uart_port *port,
344 struct serial_rs485 *rs485conf)
345{
346 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
347 unsigned int mode;
348
349 /* Disable interrupts */
350 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
351
352 mode = atmel_uart_readl(port, ATMEL_US_MR);
353
354 /* Resetting serial mode to RS232 (0x0) */
355 mode &= ~ATMEL_US_USMODE;
356
357 port->rs485 = *rs485conf;
358
359 if (rs485conf->flags & SER_RS485_ENABLED) {
360 dev_dbg(port->dev, "Setting UART to RS485\n");
361 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
362 atmel_uart_writel(port, ATMEL_US_TTGR,
363 rs485conf->delay_rts_after_send);
364 mode |= ATMEL_US_USMODE_RS485;
365 } else {
366 dev_dbg(port->dev, "Setting UART to RS232\n");
367 if (atmel_use_pdc_tx(port))
368 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
369 ATMEL_US_TXBUFE;
370 else
371 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
372 }
373 atmel_uart_writel(port, ATMEL_US_MR, mode);
374
375 /* Enable interrupts */
376 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
377
378 return 0;
379}
380
381/*
382 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
383 */
384static u_int atmel_tx_empty(struct uart_port *port)
385{
386 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
387 TIOCSER_TEMT :
388 0;
389}
390
391/*
392 * Set state of the modem control output lines
393 */
394static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
395{
396 unsigned int control = 0;
397 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
398 unsigned int rts_paused, rts_ready;
399 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
400
401 /* override mode to RS485 if needed, otherwise keep the current mode */
402 if (port->rs485.flags & SER_RS485_ENABLED) {
403 atmel_uart_writel(port, ATMEL_US_TTGR,
404 port->rs485.delay_rts_after_send);
405 mode &= ~ATMEL_US_USMODE;
406 mode |= ATMEL_US_USMODE_RS485;
407 }
408
409 /* set the RTS line state according to the mode */
410 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
411 /* force RTS line to high level */
412 rts_paused = ATMEL_US_RTSEN;
413
414 /* give the control of the RTS line back to the hardware */
415 rts_ready = ATMEL_US_RTSDIS;
416 } else {
417 /* force RTS line to high level */
418 rts_paused = ATMEL_US_RTSDIS;
419
420 /* force RTS line to low level */
421 rts_ready = ATMEL_US_RTSEN;
422 }
423
424 if (mctrl & TIOCM_RTS)
425 control |= rts_ready;
426 else
427 control |= rts_paused;
428
429 if (mctrl & TIOCM_DTR)
430 control |= ATMEL_US_DTREN;
431 else
432 control |= ATMEL_US_DTRDIS;
433
434 atmel_uart_writel(port, ATMEL_US_CR, control);
435
436 mctrl_gpio_set(atmel_port->gpios, mctrl);
437
438 /* Local loopback mode? */
439 mode &= ~ATMEL_US_CHMODE;
440 if (mctrl & TIOCM_LOOP)
441 mode |= ATMEL_US_CHMODE_LOC_LOOP;
442 else
443 mode |= ATMEL_US_CHMODE_NORMAL;
444
445 atmel_uart_writel(port, ATMEL_US_MR, mode);
446}
447
448/*
449 * Get state of the modem control input lines
450 */
451static u_int atmel_get_mctrl(struct uart_port *port)
452{
453 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
454 unsigned int ret = 0, status;
455
456 status = atmel_uart_readl(port, ATMEL_US_CSR);
457
458 /*
459 * The control signals are active low.
460 */
461 if (!(status & ATMEL_US_DCD))
462 ret |= TIOCM_CD;
463 if (!(status & ATMEL_US_CTS))
464 ret |= TIOCM_CTS;
465 if (!(status & ATMEL_US_DSR))
466 ret |= TIOCM_DSR;
467 if (!(status & ATMEL_US_RI))
468 ret |= TIOCM_RI;
469
470 return mctrl_gpio_get(atmel_port->gpios, &ret);
471}
472
473/*
474 * Stop transmitting.
475 */
476static void atmel_stop_tx(struct uart_port *port)
477{
478 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
479
480 if (atmel_use_pdc_tx(port)) {
481 /* disable PDC transmit */
482 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
483 }
484
485 /*
486 * Disable the transmitter.
487 * This is mandatory when DMA is used, otherwise the DMA buffer
488 * is fully transmitted.
489 */
490 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
491
492 /* Disable interrupts */
493 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
494
495 if ((port->rs485.flags & SER_RS485_ENABLED) &&
496 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
497 atmel_start_rx(port);
498}
499
500/*
501 * Start transmitting.
502 */
503static void atmel_start_tx(struct uart_port *port)
504{
505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
506
507 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
508 & ATMEL_PDC_TXTEN))
509 /* The transmitter is already running. Yes, we
510 really need this.*/
511 return;
512
513 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
514 if ((port->rs485.flags & SER_RS485_ENABLED) &&
515 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
516 atmel_stop_rx(port);
517
518 if (atmel_use_pdc_tx(port))
519 /* re-enable PDC transmit */
520 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
521
522 /* Enable interrupts */
523 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
524
525 /* re-enable the transmitter */
526 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
527}
528
529/*
530 * start receiving - port is in process of being opened.
531 */
532static void atmel_start_rx(struct uart_port *port)
533{
534 /* reset status and receiver */
535 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
536
537 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
538
539 if (atmel_use_pdc_rx(port)) {
540 /* enable PDC controller */
541 atmel_uart_writel(port, ATMEL_US_IER,
542 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
543 port->read_status_mask);
544 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
545 } else {
546 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
547 }
548}
549
550/*
551 * Stop receiving - port is in process of being closed.
552 */
553static void atmel_stop_rx(struct uart_port *port)
554{
555 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
556
557 if (atmel_use_pdc_rx(port)) {
558 /* disable PDC receive */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
560 atmel_uart_writel(port, ATMEL_US_IDR,
561 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
562 port->read_status_mask);
563 } else {
564 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
565 }
566}
567
568/*
569 * Enable modem status interrupts
570 */
571static void atmel_enable_ms(struct uart_port *port)
572{
573 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
574 uint32_t ier = 0;
575
576 /*
577 * Interrupt should not be enabled twice
578 */
579 if (atmel_port->ms_irq_enabled)
580 return;
581
582 atmel_port->ms_irq_enabled = true;
583
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
585 ier |= ATMEL_US_CTSIC;
586
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
588 ier |= ATMEL_US_DSRIC;
589
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
591 ier |= ATMEL_US_RIIC;
592
593 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
594 ier |= ATMEL_US_DCDIC;
595
596 atmel_uart_writel(port, ATMEL_US_IER, ier);
597
598 mctrl_gpio_enable_ms(atmel_port->gpios);
599}
600
601/*
602 * Disable modem status interrupts
603 */
604static void atmel_disable_ms(struct uart_port *port)
605{
606 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
607 uint32_t idr = 0;
608
609 /*
610 * Interrupt should not be disabled twice
611 */
612 if (!atmel_port->ms_irq_enabled)
613 return;
614
615 atmel_port->ms_irq_enabled = false;
616
617 mctrl_gpio_disable_ms(atmel_port->gpios);
618
619 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
620 idr |= ATMEL_US_CTSIC;
621
622 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
623 idr |= ATMEL_US_DSRIC;
624
625 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
626 idr |= ATMEL_US_RIIC;
627
628 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
629 idr |= ATMEL_US_DCDIC;
630
631 atmel_uart_writel(port, ATMEL_US_IDR, idr);
632}
633
634/*
635 * Control the transmission of a break signal
636 */
637static void atmel_break_ctl(struct uart_port *port, int break_state)
638{
639 if (break_state != 0)
640 /* start break */
641 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
642 else
643 /* stop break */
644 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
645}
646
647/*
648 * Stores the incoming character in the ring buffer
649 */
650static void
651atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
652 unsigned int ch)
653{
654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
655 struct circ_buf *ring = &atmel_port->rx_ring;
656 struct atmel_uart_char *c;
657
658 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
659 /* Buffer overflow, ignore char */
660 return;
661
662 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
663 c->status = status;
664 c->ch = ch;
665
666 /* Make sure the character is stored before we update head. */
667 smp_wmb();
668
669 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
670}
671
672/*
673 * Deal with parity, framing and overrun errors.
674 */
675static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
676{
677 /* clear error */
678 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
679
680 if (status & ATMEL_US_RXBRK) {
681 /* ignore side-effect */
682 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
683 port->icount.brk++;
684 }
685 if (status & ATMEL_US_PARE)
686 port->icount.parity++;
687 if (status & ATMEL_US_FRAME)
688 port->icount.frame++;
689 if (status & ATMEL_US_OVRE)
690 port->icount.overrun++;
691}
692
693/*
694 * Characters received (called from interrupt handler)
695 */
696static void atmel_rx_chars(struct uart_port *port)
697{
698 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
699 unsigned int status, ch;
700
701 status = atmel_uart_readl(port, ATMEL_US_CSR);
702 while (status & ATMEL_US_RXRDY) {
703 ch = atmel_uart_read_char(port);
704
705 /*
706 * note that the error handling code is
707 * out of the main execution path
708 */
709 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
710 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
711 || atmel_port->break_active)) {
712
713 /* clear error */
714 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
715
716 if (status & ATMEL_US_RXBRK
717 && !atmel_port->break_active) {
718 atmel_port->break_active = 1;
719 atmel_uart_writel(port, ATMEL_US_IER,
720 ATMEL_US_RXBRK);
721 } else {
722 /*
723 * This is either the end-of-break
724 * condition or we've received at
725 * least one character without RXBRK
726 * being set. In both cases, the next
727 * RXBRK will indicate start-of-break.
728 */
729 atmel_uart_writel(port, ATMEL_US_IDR,
730 ATMEL_US_RXBRK);
731 status &= ~ATMEL_US_RXBRK;
732 atmel_port->break_active = 0;
733 }
734 }
735
736 atmel_buffer_rx_char(port, status, ch);
737 status = atmel_uart_readl(port, ATMEL_US_CSR);
738 }
739
740 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
741}
742
743/*
744 * Transmit characters (called from tasklet with TXRDY interrupt
745 * disabled)
746 */
747static void atmel_tx_chars(struct uart_port *port)
748{
749 struct circ_buf *xmit = &port->state->xmit;
750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
751
752 if (port->x_char &&
753 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
754 atmel_uart_write_char(port, port->x_char);
755 port->icount.tx++;
756 port->x_char = 0;
757 }
758 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
759 return;
760
761 while (atmel_uart_readl(port, ATMEL_US_CSR) &
762 atmel_port->tx_done_mask) {
763 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
764 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
765 port->icount.tx++;
766 if (uart_circ_empty(xmit))
767 break;
768 }
769
770 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
771 uart_write_wakeup(port);
772
773 if (!uart_circ_empty(xmit))
774 /* Enable interrupts */
775 atmel_uart_writel(port, ATMEL_US_IER,
776 atmel_port->tx_done_mask);
777}
778
779static void atmel_complete_tx_dma(void *arg)
780{
781 struct atmel_uart_port *atmel_port = arg;
782 struct uart_port *port = &atmel_port->uart;
783 struct circ_buf *xmit = &port->state->xmit;
784 struct dma_chan *chan = atmel_port->chan_tx;
785 unsigned long flags;
786
787 spin_lock_irqsave(&port->lock, flags);
788
789 if (chan)
790 dmaengine_terminate_all(chan);
791 xmit->tail += atmel_port->tx_len;
792 xmit->tail &= UART_XMIT_SIZE - 1;
793
794 port->icount.tx += atmel_port->tx_len;
795
796 spin_lock_irq(&atmel_port->lock_tx);
797 async_tx_ack(atmel_port->desc_tx);
798 atmel_port->cookie_tx = -EINVAL;
799 atmel_port->desc_tx = NULL;
800 spin_unlock_irq(&atmel_port->lock_tx);
801
802 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
803 uart_write_wakeup(port);
804
805 /*
806 * xmit is a circular buffer so, if we have just send data from
807 * xmit->tail to the end of xmit->buf, now we have to transmit the
808 * remaining data from the beginning of xmit->buf to xmit->head.
809 */
810 if (!uart_circ_empty(xmit))
811 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
812 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
813 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
814 /* DMA done, stop TX, start RX for RS485 */
815 atmel_start_rx(port);
816 }
817
818 spin_unlock_irqrestore(&port->lock, flags);
819}
820
821static void atmel_release_tx_dma(struct uart_port *port)
822{
823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
824 struct dma_chan *chan = atmel_port->chan_tx;
825
826 if (chan) {
827 dmaengine_terminate_all(chan);
828 dma_release_channel(chan);
829 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
830 DMA_TO_DEVICE);
831 }
832
833 atmel_port->desc_tx = NULL;
834 atmel_port->chan_tx = NULL;
835 atmel_port->cookie_tx = -EINVAL;
836}
837
838/*
839 * Called from tasklet with TXRDY interrupt is disabled.
840 */
841static void atmel_tx_dma(struct uart_port *port)
842{
843 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
844 struct circ_buf *xmit = &port->state->xmit;
845 struct dma_chan *chan = atmel_port->chan_tx;
846 struct dma_async_tx_descriptor *desc;
847 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
848 unsigned int tx_len, part1_len, part2_len, sg_len;
849 dma_addr_t phys_addr;
850
851 /* Make sure we have an idle channel */
852 if (atmel_port->desc_tx != NULL)
853 return;
854
855 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
856 /*
857 * DMA is idle now.
858 * Port xmit buffer is already mapped,
859 * and it is one page... Just adjust
860 * offsets and lengths. Since it is a circular buffer,
861 * we have to transmit till the end, and then the rest.
862 * Take the port lock to get a
863 * consistent xmit buffer state.
864 */
865 tx_len = CIRC_CNT_TO_END(xmit->head,
866 xmit->tail,
867 UART_XMIT_SIZE);
868
869 if (atmel_port->fifo_size) {
870 /* multi data mode */
871 part1_len = (tx_len & ~0x3); /* DWORD access */
872 part2_len = (tx_len & 0x3); /* BYTE access */
873 } else {
874 /* single data (legacy) mode */
875 part1_len = 0;
876 part2_len = tx_len; /* BYTE access only */
877 }
878
879 sg_init_table(sgl, 2);
880 sg_len = 0;
881 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
882 if (part1_len) {
883 sg = &sgl[sg_len++];
884 sg_dma_address(sg) = phys_addr;
885 sg_dma_len(sg) = part1_len;
886
887 phys_addr += part1_len;
888 }
889
890 if (part2_len) {
891 sg = &sgl[sg_len++];
892 sg_dma_address(sg) = phys_addr;
893 sg_dma_len(sg) = part2_len;
894 }
895
896 /*
897 * save tx_len so atmel_complete_tx_dma() will increase
898 * xmit->tail correctly
899 */
900 atmel_port->tx_len = tx_len;
901
902 desc = dmaengine_prep_slave_sg(chan,
903 sgl,
904 sg_len,
905 DMA_MEM_TO_DEV,
906 DMA_PREP_INTERRUPT |
907 DMA_CTRL_ACK);
908 if (!desc) {
909 dev_err(port->dev, "Failed to send via dma!\n");
910 return;
911 }
912
913 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
914
915 atmel_port->desc_tx = desc;
916 desc->callback = atmel_complete_tx_dma;
917 desc->callback_param = atmel_port;
918 atmel_port->cookie_tx = dmaengine_submit(desc);
919 }
920
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
922 uart_write_wakeup(port);
923}
924
925static int atmel_prepare_tx_dma(struct uart_port *port)
926{
927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
928 dma_cap_mask_t mask;
929 struct dma_slave_config config;
930 int ret, nent;
931
932 dma_cap_zero(mask);
933 dma_cap_set(DMA_SLAVE, mask);
934
935 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
936 if (atmel_port->chan_tx == NULL)
937 goto chan_err;
938 dev_info(port->dev, "using %s for tx DMA transfers\n",
939 dma_chan_name(atmel_port->chan_tx));
940
941 spin_lock_init(&atmel_port->lock_tx);
942 sg_init_table(&atmel_port->sg_tx, 1);
943 /* UART circular tx buffer is an aligned page. */
944 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
945 sg_set_page(&atmel_port->sg_tx,
946 virt_to_page(port->state->xmit.buf),
947 UART_XMIT_SIZE,
948 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
949 nent = dma_map_sg(port->dev,
950 &atmel_port->sg_tx,
951 1,
952 DMA_TO_DEVICE);
953
954 if (!nent) {
955 dev_dbg(port->dev, "need to release resource of dma\n");
956 goto chan_err;
957 } else {
958 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
959 sg_dma_len(&atmel_port->sg_tx),
960 port->state->xmit.buf,
961 &sg_dma_address(&atmel_port->sg_tx));
962 }
963
964 /* Configure the slave DMA */
965 memset(&config, 0, sizeof(config));
966 config.direction = DMA_MEM_TO_DEV;
967 config.dst_addr_width = (atmel_port->fifo_size) ?
968 DMA_SLAVE_BUSWIDTH_4_BYTES :
969 DMA_SLAVE_BUSWIDTH_1_BYTE;
970 config.dst_addr = port->mapbase + ATMEL_US_THR;
971 config.dst_maxburst = 1;
972
973 ret = dmaengine_slave_config(atmel_port->chan_tx,
974 &config);
975 if (ret) {
976 dev_err(port->dev, "DMA tx slave configuration failed\n");
977 goto chan_err;
978 }
979
980 return 0;
981
982chan_err:
983 dev_err(port->dev, "TX channel not available, switch to pio\n");
984 atmel_port->use_dma_tx = 0;
985 if (atmel_port->chan_tx)
986 atmel_release_tx_dma(port);
987 return -EINVAL;
988}
989
990static void atmel_complete_rx_dma(void *arg)
991{
992 struct uart_port *port = arg;
993 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
994
995 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
996}
997
998static void atmel_release_rx_dma(struct uart_port *port)
999{
1000 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1001 struct dma_chan *chan = atmel_port->chan_rx;
1002
1003 if (chan) {
1004 dmaengine_terminate_all(chan);
1005 dma_release_channel(chan);
1006 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1007 DMA_FROM_DEVICE);
1008 }
1009
1010 atmel_port->desc_rx = NULL;
1011 atmel_port->chan_rx = NULL;
1012 atmel_port->cookie_rx = -EINVAL;
1013}
1014
1015static void atmel_rx_from_dma(struct uart_port *port)
1016{
1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1018 struct tty_port *tport = &port->state->port;
1019 struct circ_buf *ring = &atmel_port->rx_ring;
1020 struct dma_chan *chan = atmel_port->chan_rx;
1021 struct dma_tx_state state;
1022 enum dma_status dmastat;
1023 size_t count;
1024
1025
1026 /* Reset the UART timeout early so that we don't miss one */
1027 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1028 dmastat = dmaengine_tx_status(chan,
1029 atmel_port->cookie_rx,
1030 &state);
1031 /* Restart a new tasklet if DMA status is error */
1032 if (dmastat == DMA_ERROR) {
1033 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1034 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1035 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1036 return;
1037 }
1038
1039 /* CPU claims ownership of RX DMA buffer */
1040 dma_sync_sg_for_cpu(port->dev,
1041 &atmel_port->sg_rx,
1042 1,
1043 DMA_FROM_DEVICE);
1044
1045 /*
1046 * ring->head points to the end of data already written by the DMA.
1047 * ring->tail points to the beginning of data to be read by the
1048 * framework.
1049 * The current transfer size should not be larger than the dma buffer
1050 * length.
1051 */
1052 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1053 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1054 /*
1055 * At this point ring->head may point to the first byte right after the
1056 * last byte of the dma buffer:
1057 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1058 *
1059 * However ring->tail must always points inside the dma buffer:
1060 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1061 *
1062 * Since we use a ring buffer, we have to handle the case
1063 * where head is lower than tail. In such a case, we first read from
1064 * tail to the end of the buffer then reset tail.
1065 */
1066 if (ring->head < ring->tail) {
1067 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1068
1069 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1070 ring->tail = 0;
1071 port->icount.rx += count;
1072 }
1073
1074 /* Finally we read data from tail to head */
1075 if (ring->tail < ring->head) {
1076 count = ring->head - ring->tail;
1077
1078 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1079 /* Wrap ring->head if needed */
1080 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1081 ring->head = 0;
1082 ring->tail = ring->head;
1083 port->icount.rx += count;
1084 }
1085
1086 /* USART retreives ownership of RX DMA buffer */
1087 dma_sync_sg_for_device(port->dev,
1088 &atmel_port->sg_rx,
1089 1,
1090 DMA_FROM_DEVICE);
1091
1092 /*
1093 * Drop the lock here since it might end up calling
1094 * uart_start(), which takes the lock.
1095 */
1096 spin_unlock(&port->lock);
1097 tty_flip_buffer_push(tport);
1098 spin_lock(&port->lock);
1099
1100 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1101}
1102
1103static int atmel_prepare_rx_dma(struct uart_port *port)
1104{
1105 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1106 struct dma_async_tx_descriptor *desc;
1107 dma_cap_mask_t mask;
1108 struct dma_slave_config config;
1109 struct circ_buf *ring;
1110 int ret, nent;
1111
1112 ring = &atmel_port->rx_ring;
1113
1114 dma_cap_zero(mask);
1115 dma_cap_set(DMA_CYCLIC, mask);
1116
1117 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1118 if (atmel_port->chan_rx == NULL)
1119 goto chan_err;
1120 dev_info(port->dev, "using %s for rx DMA transfers\n",
1121 dma_chan_name(atmel_port->chan_rx));
1122
1123 spin_lock_init(&atmel_port->lock_rx);
1124 sg_init_table(&atmel_port->sg_rx, 1);
1125 /* UART circular rx buffer is an aligned page. */
1126 BUG_ON(!PAGE_ALIGNED(ring->buf));
1127 sg_set_page(&atmel_port->sg_rx,
1128 virt_to_page(ring->buf),
1129 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1130 (unsigned long)ring->buf & ~PAGE_MASK);
1131 nent = dma_map_sg(port->dev,
1132 &atmel_port->sg_rx,
1133 1,
1134 DMA_FROM_DEVICE);
1135
1136 if (!nent) {
1137 dev_dbg(port->dev, "need to release resource of dma\n");
1138 goto chan_err;
1139 } else {
1140 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1141 sg_dma_len(&atmel_port->sg_rx),
1142 ring->buf,
1143 &sg_dma_address(&atmel_port->sg_rx));
1144 }
1145
1146 /* Configure the slave DMA */
1147 memset(&config, 0, sizeof(config));
1148 config.direction = DMA_DEV_TO_MEM;
1149 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1150 config.src_addr = port->mapbase + ATMEL_US_RHR;
1151 config.src_maxburst = 1;
1152
1153 ret = dmaengine_slave_config(atmel_port->chan_rx,
1154 &config);
1155 if (ret) {
1156 dev_err(port->dev, "DMA rx slave configuration failed\n");
1157 goto chan_err;
1158 }
1159 /*
1160 * Prepare a cyclic dma transfer, assign 2 descriptors,
1161 * each one is half ring buffer size
1162 */
1163 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1164 sg_dma_address(&atmel_port->sg_rx),
1165 sg_dma_len(&atmel_port->sg_rx),
1166 sg_dma_len(&atmel_port->sg_rx)/2,
1167 DMA_DEV_TO_MEM,
1168 DMA_PREP_INTERRUPT);
1169 desc->callback = atmel_complete_rx_dma;
1170 desc->callback_param = port;
1171 atmel_port->desc_rx = desc;
1172 atmel_port->cookie_rx = dmaengine_submit(desc);
1173
1174 return 0;
1175
1176chan_err:
1177 dev_err(port->dev, "RX channel not available, switch to pio\n");
1178 atmel_port->use_dma_rx = 0;
1179 if (atmel_port->chan_rx)
1180 atmel_release_rx_dma(port);
1181 return -EINVAL;
1182}
1183
1184static void atmel_uart_timer_callback(unsigned long data)
1185{
1186 struct uart_port *port = (void *)data;
1187 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1188
1189 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1190 tasklet_schedule(&atmel_port->tasklet_rx);
1191 mod_timer(&atmel_port->uart_timer,
1192 jiffies + uart_poll_timeout(port));
1193 }
1194}
1195
1196/*
1197 * receive interrupt handler.
1198 */
1199static void
1200atmel_handle_receive(struct uart_port *port, unsigned int pending)
1201{
1202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1203
1204 if (atmel_use_pdc_rx(port)) {
1205 /*
1206 * PDC receive. Just schedule the tasklet and let it
1207 * figure out the details.
1208 *
1209 * TODO: We're not handling error flags correctly at
1210 * the moment.
1211 */
1212 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1213 atmel_uart_writel(port, ATMEL_US_IDR,
1214 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1215 atmel_tasklet_schedule(atmel_port,
1216 &atmel_port->tasklet_rx);
1217 }
1218
1219 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1220 ATMEL_US_FRAME | ATMEL_US_PARE))
1221 atmel_pdc_rxerr(port, pending);
1222 }
1223
1224 if (atmel_use_dma_rx(port)) {
1225 if (pending & ATMEL_US_TIMEOUT) {
1226 atmel_uart_writel(port, ATMEL_US_IDR,
1227 ATMEL_US_TIMEOUT);
1228 atmel_tasklet_schedule(atmel_port,
1229 &atmel_port->tasklet_rx);
1230 }
1231 }
1232
1233 /* Interrupt receive */
1234 if (pending & ATMEL_US_RXRDY)
1235 atmel_rx_chars(port);
1236 else if (pending & ATMEL_US_RXBRK) {
1237 /*
1238 * End of break detected. If it came along with a
1239 * character, atmel_rx_chars will handle it.
1240 */
1241 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1242 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1243 atmel_port->break_active = 0;
1244 }
1245}
1246
1247/*
1248 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1249 */
1250static void
1251atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1252{
1253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1254
1255 if (pending & atmel_port->tx_done_mask) {
1256 /* Either PDC or interrupt transmission */
1257 atmel_uart_writel(port, ATMEL_US_IDR,
1258 atmel_port->tx_done_mask);
1259 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1260 }
1261}
1262
1263/*
1264 * status flags interrupt handler.
1265 */
1266static void
1267atmel_handle_status(struct uart_port *port, unsigned int pending,
1268 unsigned int status)
1269{
1270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1271 unsigned int status_change;
1272
1273 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1274 | ATMEL_US_CTSIC)) {
1275 status_change = status ^ atmel_port->irq_status_prev;
1276 atmel_port->irq_status_prev = status;
1277
1278 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1279 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1280 /* TODO: All reads to CSR will clear these interrupts! */
1281 if (status_change & ATMEL_US_RI)
1282 port->icount.rng++;
1283 if (status_change & ATMEL_US_DSR)
1284 port->icount.dsr++;
1285 if (status_change & ATMEL_US_DCD)
1286 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1287 if (status_change & ATMEL_US_CTS)
1288 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1289
1290 wake_up_interruptible(&port->state->port.delta_msr_wait);
1291 }
1292 }
1293}
1294
1295/*
1296 * Interrupt handler
1297 */
1298static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1299{
1300 struct uart_port *port = dev_id;
1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1302 unsigned int status, pending, mask, pass_counter = 0;
1303
1304 spin_lock(&atmel_port->lock_suspended);
1305
1306 do {
1307 status = atmel_get_lines_status(port);
1308 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1309 pending = status & mask;
1310 if (!pending)
1311 break;
1312
1313 if (atmel_port->suspended) {
1314 atmel_port->pending |= pending;
1315 atmel_port->pending_status = status;
1316 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1317 pm_system_wakeup();
1318 break;
1319 }
1320
1321 atmel_handle_receive(port, pending);
1322 atmel_handle_status(port, pending, status);
1323 atmel_handle_transmit(port, pending);
1324 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1325
1326 spin_unlock(&atmel_port->lock_suspended);
1327
1328 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1329}
1330
1331static void atmel_release_tx_pdc(struct uart_port *port)
1332{
1333 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1334 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1335
1336 dma_unmap_single(port->dev,
1337 pdc->dma_addr,
1338 pdc->dma_size,
1339 DMA_TO_DEVICE);
1340}
1341
1342/*
1343 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1344 */
1345static void atmel_tx_pdc(struct uart_port *port)
1346{
1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 struct circ_buf *xmit = &port->state->xmit;
1349 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1350 int count;
1351
1352 /* nothing left to transmit? */
1353 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1354 return;
1355
1356 xmit->tail += pdc->ofs;
1357 xmit->tail &= UART_XMIT_SIZE - 1;
1358
1359 port->icount.tx += pdc->ofs;
1360 pdc->ofs = 0;
1361
1362 /* more to transmit - setup next transfer */
1363
1364 /* disable PDC transmit */
1365 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1366
1367 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1368 dma_sync_single_for_device(port->dev,
1369 pdc->dma_addr,
1370 pdc->dma_size,
1371 DMA_TO_DEVICE);
1372
1373 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1374 pdc->ofs = count;
1375
1376 atmel_uart_writel(port, ATMEL_PDC_TPR,
1377 pdc->dma_addr + xmit->tail);
1378 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1379 /* re-enable PDC transmit */
1380 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1381 /* Enable interrupts */
1382 atmel_uart_writel(port, ATMEL_US_IER,
1383 atmel_port->tx_done_mask);
1384 } else {
1385 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1386 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1387 /* DMA done, stop TX, start RX for RS485 */
1388 atmel_start_rx(port);
1389 }
1390 }
1391
1392 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1393 uart_write_wakeup(port);
1394}
1395
1396static int atmel_prepare_tx_pdc(struct uart_port *port)
1397{
1398 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1399 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1400 struct circ_buf *xmit = &port->state->xmit;
1401
1402 pdc->buf = xmit->buf;
1403 pdc->dma_addr = dma_map_single(port->dev,
1404 pdc->buf,
1405 UART_XMIT_SIZE,
1406 DMA_TO_DEVICE);
1407 pdc->dma_size = UART_XMIT_SIZE;
1408 pdc->ofs = 0;
1409
1410 return 0;
1411}
1412
1413static void atmel_rx_from_ring(struct uart_port *port)
1414{
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 struct circ_buf *ring = &atmel_port->rx_ring;
1417 unsigned int flg;
1418 unsigned int status;
1419
1420 while (ring->head != ring->tail) {
1421 struct atmel_uart_char c;
1422
1423 /* Make sure c is loaded after head. */
1424 smp_rmb();
1425
1426 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1427
1428 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1429
1430 port->icount.rx++;
1431 status = c.status;
1432 flg = TTY_NORMAL;
1433
1434 /*
1435 * note that the error handling code is
1436 * out of the main execution path
1437 */
1438 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1439 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1440 if (status & ATMEL_US_RXBRK) {
1441 /* ignore side-effect */
1442 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1443
1444 port->icount.brk++;
1445 if (uart_handle_break(port))
1446 continue;
1447 }
1448 if (status & ATMEL_US_PARE)
1449 port->icount.parity++;
1450 if (status & ATMEL_US_FRAME)
1451 port->icount.frame++;
1452 if (status & ATMEL_US_OVRE)
1453 port->icount.overrun++;
1454
1455 status &= port->read_status_mask;
1456
1457 if (status & ATMEL_US_RXBRK)
1458 flg = TTY_BREAK;
1459 else if (status & ATMEL_US_PARE)
1460 flg = TTY_PARITY;
1461 else if (status & ATMEL_US_FRAME)
1462 flg = TTY_FRAME;
1463 }
1464
1465
1466 if (uart_handle_sysrq_char(port, c.ch))
1467 continue;
1468
1469 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1470 }
1471
1472 /*
1473 * Drop the lock here since it might end up calling
1474 * uart_start(), which takes the lock.
1475 */
1476 spin_unlock(&port->lock);
1477 tty_flip_buffer_push(&port->state->port);
1478 spin_lock(&port->lock);
1479}
1480
1481static void atmel_release_rx_pdc(struct uart_port *port)
1482{
1483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1484 int i;
1485
1486 for (i = 0; i < 2; i++) {
1487 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1488
1489 dma_unmap_single(port->dev,
1490 pdc->dma_addr,
1491 pdc->dma_size,
1492 DMA_FROM_DEVICE);
1493 kfree(pdc->buf);
1494 }
1495}
1496
1497static void atmel_rx_from_pdc(struct uart_port *port)
1498{
1499 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1500 struct tty_port *tport = &port->state->port;
1501 struct atmel_dma_buffer *pdc;
1502 int rx_idx = atmel_port->pdc_rx_idx;
1503 unsigned int head;
1504 unsigned int tail;
1505 unsigned int count;
1506
1507 do {
1508 /* Reset the UART timeout early so that we don't miss one */
1509 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1510
1511 pdc = &atmel_port->pdc_rx[rx_idx];
1512 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1513 tail = pdc->ofs;
1514
1515 /* If the PDC has switched buffers, RPR won't contain
1516 * any address within the current buffer. Since head
1517 * is unsigned, we just need a one-way comparison to
1518 * find out.
1519 *
1520 * In this case, we just need to consume the entire
1521 * buffer and resubmit it for DMA. This will clear the
1522 * ENDRX bit as well, so that we can safely re-enable
1523 * all interrupts below.
1524 */
1525 head = min(head, pdc->dma_size);
1526
1527 if (likely(head != tail)) {
1528 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1529 pdc->dma_size, DMA_FROM_DEVICE);
1530
1531 /*
1532 * head will only wrap around when we recycle
1533 * the DMA buffer, and when that happens, we
1534 * explicitly set tail to 0. So head will
1535 * always be greater than tail.
1536 */
1537 count = head - tail;
1538
1539 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1540 count);
1541
1542 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1543 pdc->dma_size, DMA_FROM_DEVICE);
1544
1545 port->icount.rx += count;
1546 pdc->ofs = head;
1547 }
1548
1549 /*
1550 * If the current buffer is full, we need to check if
1551 * the next one contains any additional data.
1552 */
1553 if (head >= pdc->dma_size) {
1554 pdc->ofs = 0;
1555 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1556 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1557
1558 rx_idx = !rx_idx;
1559 atmel_port->pdc_rx_idx = rx_idx;
1560 }
1561 } while (head >= pdc->dma_size);
1562
1563 /*
1564 * Drop the lock here since it might end up calling
1565 * uart_start(), which takes the lock.
1566 */
1567 spin_unlock(&port->lock);
1568 tty_flip_buffer_push(tport);
1569 spin_lock(&port->lock);
1570
1571 atmel_uart_writel(port, ATMEL_US_IER,
1572 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1573}
1574
1575static int atmel_prepare_rx_pdc(struct uart_port *port)
1576{
1577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1578 int i;
1579
1580 for (i = 0; i < 2; i++) {
1581 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1582
1583 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1584 if (pdc->buf == NULL) {
1585 if (i != 0) {
1586 dma_unmap_single(port->dev,
1587 atmel_port->pdc_rx[0].dma_addr,
1588 PDC_BUFFER_SIZE,
1589 DMA_FROM_DEVICE);
1590 kfree(atmel_port->pdc_rx[0].buf);
1591 }
1592 atmel_port->use_pdc_rx = 0;
1593 return -ENOMEM;
1594 }
1595 pdc->dma_addr = dma_map_single(port->dev,
1596 pdc->buf,
1597 PDC_BUFFER_SIZE,
1598 DMA_FROM_DEVICE);
1599 pdc->dma_size = PDC_BUFFER_SIZE;
1600 pdc->ofs = 0;
1601 }
1602
1603 atmel_port->pdc_rx_idx = 0;
1604
1605 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1606 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1607
1608 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1609 atmel_port->pdc_rx[1].dma_addr);
1610 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1611
1612 return 0;
1613}
1614
1615/*
1616 * tasklet handling tty stuff outside the interrupt handler.
1617 */
1618static void atmel_tasklet_rx_func(unsigned long data)
1619{
1620 struct uart_port *port = (struct uart_port *)data;
1621 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1622
1623 /* The interrupt handler does not take the lock */
1624 spin_lock(&port->lock);
1625 atmel_port->schedule_rx(port);
1626 spin_unlock(&port->lock);
1627}
1628
1629static void atmel_tasklet_tx_func(unsigned long data)
1630{
1631 struct uart_port *port = (struct uart_port *)data;
1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1633
1634 /* The interrupt handler does not take the lock */
1635 spin_lock(&port->lock);
1636 atmel_port->schedule_tx(port);
1637 spin_unlock(&port->lock);
1638}
1639
1640static void atmel_init_property(struct atmel_uart_port *atmel_port,
1641 struct platform_device *pdev)
1642{
1643 struct device_node *np = pdev->dev.of_node;
1644 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1645
1646 if (np) {
1647 /* DMA/PDC usage specification */
1648 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1649 if (of_property_read_bool(np, "dmas")) {
1650 atmel_port->use_dma_rx = true;
1651 atmel_port->use_pdc_rx = false;
1652 } else {
1653 atmel_port->use_dma_rx = false;
1654 atmel_port->use_pdc_rx = true;
1655 }
1656 } else {
1657 atmel_port->use_dma_rx = false;
1658 atmel_port->use_pdc_rx = false;
1659 }
1660
1661 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1662 if (of_property_read_bool(np, "dmas")) {
1663 atmel_port->use_dma_tx = true;
1664 atmel_port->use_pdc_tx = false;
1665 } else {
1666 atmel_port->use_dma_tx = false;
1667 atmel_port->use_pdc_tx = true;
1668 }
1669 } else {
1670 atmel_port->use_dma_tx = false;
1671 atmel_port->use_pdc_tx = false;
1672 }
1673
1674 } else {
1675 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1676 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1677 atmel_port->use_dma_rx = false;
1678 atmel_port->use_dma_tx = false;
1679 }
1680
1681}
1682
1683static void atmel_init_rs485(struct uart_port *port,
1684 struct platform_device *pdev)
1685{
1686 struct device_node *np = pdev->dev.of_node;
1687 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1688
1689 if (np) {
1690 struct serial_rs485 *rs485conf = &port->rs485;
1691 u32 rs485_delay[2];
1692 /* rs485 properties */
1693 if (of_property_read_u32_array(np, "rs485-rts-delay",
1694 rs485_delay, 2) == 0) {
1695 rs485conf->delay_rts_before_send = rs485_delay[0];
1696 rs485conf->delay_rts_after_send = rs485_delay[1];
1697 rs485conf->flags = 0;
1698 }
1699
1700 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1701 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1702
1703 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1704 NULL))
1705 rs485conf->flags |= SER_RS485_ENABLED;
1706 } else {
1707 port->rs485 = pdata->rs485;
1708 }
1709
1710}
1711
1712static void atmel_set_ops(struct uart_port *port)
1713{
1714 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1715
1716 if (atmel_use_dma_rx(port)) {
1717 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1718 atmel_port->schedule_rx = &atmel_rx_from_dma;
1719 atmel_port->release_rx = &atmel_release_rx_dma;
1720 } else if (atmel_use_pdc_rx(port)) {
1721 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1722 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1723 atmel_port->release_rx = &atmel_release_rx_pdc;
1724 } else {
1725 atmel_port->prepare_rx = NULL;
1726 atmel_port->schedule_rx = &atmel_rx_from_ring;
1727 atmel_port->release_rx = NULL;
1728 }
1729
1730 if (atmel_use_dma_tx(port)) {
1731 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1732 atmel_port->schedule_tx = &atmel_tx_dma;
1733 atmel_port->release_tx = &atmel_release_tx_dma;
1734 } else if (atmel_use_pdc_tx(port)) {
1735 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1736 atmel_port->schedule_tx = &atmel_tx_pdc;
1737 atmel_port->release_tx = &atmel_release_tx_pdc;
1738 } else {
1739 atmel_port->prepare_tx = NULL;
1740 atmel_port->schedule_tx = &atmel_tx_chars;
1741 atmel_port->release_tx = NULL;
1742 }
1743}
1744
1745/*
1746 * Get ip name usart or uart
1747 */
1748static void atmel_get_ip_name(struct uart_port *port)
1749{
1750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1751 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1752 u32 version;
1753 u32 usart, dbgu_uart, new_uart;
1754 /* ASCII decoding for IP version */
1755 usart = 0x55534152; /* USAR(T) */
1756 dbgu_uart = 0x44424755; /* DBGU */
1757 new_uart = 0x55415254; /* UART */
1758
1759 /*
1760 * Only USART devices from at91sam9260 SOC implement fractional
1761 * baudrate.
1762 */
1763 atmel_port->has_frac_baudrate = false;
1764 atmel_port->has_hw_timer = false;
1765
1766 if (name == new_uart) {
1767 dev_dbg(port->dev, "Uart with hw timer");
1768 atmel_port->has_hw_timer = true;
1769 atmel_port->rtor = ATMEL_UA_RTOR;
1770 } else if (name == usart) {
1771 dev_dbg(port->dev, "Usart\n");
1772 atmel_port->has_frac_baudrate = true;
1773 atmel_port->has_hw_timer = true;
1774 atmel_port->rtor = ATMEL_US_RTOR;
1775 } else if (name == dbgu_uart) {
1776 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1777 } else {
1778 /* fallback for older SoCs: use version field */
1779 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1780 switch (version) {
1781 case 0x302:
1782 case 0x10213:
1783 dev_dbg(port->dev, "This version is usart\n");
1784 atmel_port->has_frac_baudrate = true;
1785 atmel_port->has_hw_timer = true;
1786 atmel_port->rtor = ATMEL_US_RTOR;
1787 break;
1788 case 0x203:
1789 case 0x10202:
1790 dev_dbg(port->dev, "This version is uart\n");
1791 break;
1792 default:
1793 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1794 }
1795 }
1796}
1797
1798/*
1799 * Perform initialization and enable port for reception
1800 */
1801static int atmel_startup(struct uart_port *port)
1802{
1803 struct platform_device *pdev = to_platform_device(port->dev);
1804 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1805 struct tty_struct *tty = port->state->port.tty;
1806 int retval;
1807
1808 /*
1809 * Ensure that no interrupts are enabled otherwise when
1810 * request_irq() is called we could get stuck trying to
1811 * handle an unexpected interrupt
1812 */
1813 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1814 atmel_port->ms_irq_enabled = false;
1815
1816 /*
1817 * Allocate the IRQ
1818 */
1819 retval = request_irq(port->irq, atmel_interrupt,
1820 IRQF_SHARED | IRQF_COND_SUSPEND,
1821 tty ? tty->name : "atmel_serial", port);
1822 if (retval) {
1823 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1824 return retval;
1825 }
1826
1827 atomic_set(&atmel_port->tasklet_shutdown, 0);
1828 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1829 (unsigned long)port);
1830 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1831 (unsigned long)port);
1832
1833 /*
1834 * Initialize DMA (if necessary)
1835 */
1836 atmel_init_property(atmel_port, pdev);
1837 atmel_set_ops(port);
1838
1839 if (atmel_port->prepare_rx) {
1840 retval = atmel_port->prepare_rx(port);
1841 if (retval < 0)
1842 atmel_set_ops(port);
1843 }
1844
1845 if (atmel_port->prepare_tx) {
1846 retval = atmel_port->prepare_tx(port);
1847 if (retval < 0)
1848 atmel_set_ops(port);
1849 }
1850
1851 /*
1852 * Enable FIFO when available
1853 */
1854 if (atmel_port->fifo_size) {
1855 unsigned int txrdym = ATMEL_US_ONE_DATA;
1856 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1857 unsigned int fmr;
1858
1859 atmel_uart_writel(port, ATMEL_US_CR,
1860 ATMEL_US_FIFOEN |
1861 ATMEL_US_RXFCLR |
1862 ATMEL_US_TXFLCLR);
1863
1864 if (atmel_use_dma_tx(port))
1865 txrdym = ATMEL_US_FOUR_DATA;
1866
1867 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1868 if (atmel_port->rts_high &&
1869 atmel_port->rts_low)
1870 fmr |= ATMEL_US_FRTSC |
1871 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1872 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1873
1874 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1875 }
1876
1877 /* Save current CSR for comparison in atmel_tasklet_func() */
1878 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1879
1880 /*
1881 * Finally, enable the serial port
1882 */
1883 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1884 /* enable xmit & rcvr */
1885 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1886
1887 setup_timer(&atmel_port->uart_timer,
1888 atmel_uart_timer_callback,
1889 (unsigned long)port);
1890
1891 if (atmel_use_pdc_rx(port)) {
1892 /* set UART timeout */
1893 if (!atmel_port->has_hw_timer) {
1894 mod_timer(&atmel_port->uart_timer,
1895 jiffies + uart_poll_timeout(port));
1896 /* set USART timeout */
1897 } else {
1898 atmel_uart_writel(port, atmel_port->rtor,
1899 PDC_RX_TIMEOUT);
1900 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1901
1902 atmel_uart_writel(port, ATMEL_US_IER,
1903 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1904 }
1905 /* enable PDC controller */
1906 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1907 } else if (atmel_use_dma_rx(port)) {
1908 /* set UART timeout */
1909 if (!atmel_port->has_hw_timer) {
1910 mod_timer(&atmel_port->uart_timer,
1911 jiffies + uart_poll_timeout(port));
1912 /* set USART timeout */
1913 } else {
1914 atmel_uart_writel(port, atmel_port->rtor,
1915 PDC_RX_TIMEOUT);
1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1917
1918 atmel_uart_writel(port, ATMEL_US_IER,
1919 ATMEL_US_TIMEOUT);
1920 }
1921 } else {
1922 /* enable receive only */
1923 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1924 }
1925
1926 return 0;
1927}
1928
1929/*
1930 * Flush any TX data submitted for DMA. Called when the TX circular
1931 * buffer is reset.
1932 */
1933static void atmel_flush_buffer(struct uart_port *port)
1934{
1935 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1936
1937 if (atmel_use_pdc_tx(port)) {
1938 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1939 atmel_port->pdc_tx.ofs = 0;
1940 }
1941 /*
1942 * in uart_flush_buffer(), the xmit circular buffer has just
1943 * been cleared, so we have to reset tx_len accordingly.
1944 */
1945 atmel_port->tx_len = 0;
1946}
1947
1948/*
1949 * Disable the port
1950 */
1951static void atmel_shutdown(struct uart_port *port)
1952{
1953 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1954
1955 /* Disable modem control lines interrupts */
1956 atmel_disable_ms(port);
1957
1958 /* Disable interrupts at device level */
1959 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1960
1961 /* Prevent spurious interrupts from scheduling the tasklet */
1962 atomic_inc(&atmel_port->tasklet_shutdown);
1963
1964 /*
1965 * Prevent any tasklets being scheduled during
1966 * cleanup
1967 */
1968 del_timer_sync(&atmel_port->uart_timer);
1969
1970 /* Make sure that no interrupt is on the fly */
1971 synchronize_irq(port->irq);
1972
1973 /*
1974 * Clear out any scheduled tasklets before
1975 * we destroy the buffers
1976 */
1977 tasklet_kill(&atmel_port->tasklet_rx);
1978 tasklet_kill(&atmel_port->tasklet_tx);
1979
1980 /*
1981 * Ensure everything is stopped and
1982 * disable port and break condition.
1983 */
1984 atmel_stop_rx(port);
1985 atmel_stop_tx(port);
1986
1987 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1988
1989 /*
1990 * Shut-down the DMA.
1991 */
1992 if (atmel_port->release_rx)
1993 atmel_port->release_rx(port);
1994 if (atmel_port->release_tx)
1995 atmel_port->release_tx(port);
1996
1997 /*
1998 * Reset ring buffer pointers
1999 */
2000 atmel_port->rx_ring.head = 0;
2001 atmel_port->rx_ring.tail = 0;
2002
2003 /*
2004 * Free the interrupts
2005 */
2006 free_irq(port->irq, port);
2007
2008 atmel_flush_buffer(port);
2009}
2010
2011/*
2012 * Power / Clock management.
2013 */
2014static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2015 unsigned int oldstate)
2016{
2017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2018
2019 switch (state) {
2020 case 0:
2021 /*
2022 * Enable the peripheral clock for this serial port.
2023 * This is called on uart_open() or a resume event.
2024 */
2025 clk_prepare_enable(atmel_port->clk);
2026
2027 /* re-enable interrupts if we disabled some on suspend */
2028 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2029 break;
2030 case 3:
2031 /* Back up the interrupt mask and disable all interrupts */
2032 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2033 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2034
2035 /*
2036 * Disable the peripheral clock for this serial port.
2037 * This is called on uart_close() or a suspend event.
2038 */
2039 clk_disable_unprepare(atmel_port->clk);
2040 break;
2041 default:
2042 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2043 }
2044}
2045
2046/*
2047 * Change the port parameters
2048 */
2049static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2050 struct ktermios *old)
2051{
2052 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2053 unsigned long flags;
2054 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2055
2056 /* save the current mode register */
2057 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2058
2059 /* reset the mode, clock divisor, parity, stop bits and data size */
2060 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2061 ATMEL_US_PAR | ATMEL_US_USMODE);
2062
2063 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2064
2065 /* byte size */
2066 switch (termios->c_cflag & CSIZE) {
2067 case CS5:
2068 mode |= ATMEL_US_CHRL_5;
2069 break;
2070 case CS6:
2071 mode |= ATMEL_US_CHRL_6;
2072 break;
2073 case CS7:
2074 mode |= ATMEL_US_CHRL_7;
2075 break;
2076 default:
2077 mode |= ATMEL_US_CHRL_8;
2078 break;
2079 }
2080
2081 /* stop bits */
2082 if (termios->c_cflag & CSTOPB)
2083 mode |= ATMEL_US_NBSTOP_2;
2084
2085 /* parity */
2086 if (termios->c_cflag & PARENB) {
2087 /* Mark or Space parity */
2088 if (termios->c_cflag & CMSPAR) {
2089 if (termios->c_cflag & PARODD)
2090 mode |= ATMEL_US_PAR_MARK;
2091 else
2092 mode |= ATMEL_US_PAR_SPACE;
2093 } else if (termios->c_cflag & PARODD)
2094 mode |= ATMEL_US_PAR_ODD;
2095 else
2096 mode |= ATMEL_US_PAR_EVEN;
2097 } else
2098 mode |= ATMEL_US_PAR_NONE;
2099
2100 spin_lock_irqsave(&port->lock, flags);
2101
2102 port->read_status_mask = ATMEL_US_OVRE;
2103 if (termios->c_iflag & INPCK)
2104 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2105 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2106 port->read_status_mask |= ATMEL_US_RXBRK;
2107
2108 if (atmel_use_pdc_rx(port))
2109 /* need to enable error interrupts */
2110 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2111
2112 /*
2113 * Characters to ignore
2114 */
2115 port->ignore_status_mask = 0;
2116 if (termios->c_iflag & IGNPAR)
2117 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2118 if (termios->c_iflag & IGNBRK) {
2119 port->ignore_status_mask |= ATMEL_US_RXBRK;
2120 /*
2121 * If we're ignoring parity and break indicators,
2122 * ignore overruns too (for real raw support).
2123 */
2124 if (termios->c_iflag & IGNPAR)
2125 port->ignore_status_mask |= ATMEL_US_OVRE;
2126 }
2127 /* TODO: Ignore all characters if CREAD is set.*/
2128
2129 /* update the per-port timeout */
2130 uart_update_timeout(port, termios->c_cflag, baud);
2131
2132 /*
2133 * save/disable interrupts. The tty layer will ensure that the
2134 * transmitter is empty if requested by the caller, so there's
2135 * no need to wait for it here.
2136 */
2137 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2138 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2139
2140 /* disable receiver and transmitter */
2141 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2142
2143 /* mode */
2144 if (port->rs485.flags & SER_RS485_ENABLED) {
2145 atmel_uart_writel(port, ATMEL_US_TTGR,
2146 port->rs485.delay_rts_after_send);
2147 mode |= ATMEL_US_USMODE_RS485;
2148 } else if (termios->c_cflag & CRTSCTS) {
2149 /* RS232 with hardware handshake (RTS/CTS) */
2150 if (atmel_use_fifo(port) &&
2151 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2152 /*
2153 * with ATMEL_US_USMODE_HWHS set, the controller will
2154 * be able to drive the RTS pin high/low when the RX
2155 * FIFO is above RXFTHRES/below RXFTHRES2.
2156 * It will also disable the transmitter when the CTS
2157 * pin is high.
2158 * This mode is not activated if CTS pin is a GPIO
2159 * because in this case, the transmitter is always
2160 * disabled (there must be an internal pull-up
2161 * responsible for this behaviour).
2162 * If the RTS pin is a GPIO, the controller won't be
2163 * able to drive it according to the FIFO thresholds,
2164 * but it will be handled by the driver.
2165 */
2166 mode |= ATMEL_US_USMODE_HWHS;
2167 } else {
2168 /*
2169 * For platforms without FIFO, the flow control is
2170 * handled by the driver.
2171 */
2172 mode |= ATMEL_US_USMODE_NORMAL;
2173 }
2174 } else {
2175 /* RS232 without hadware handshake */
2176 mode |= ATMEL_US_USMODE_NORMAL;
2177 }
2178
2179 /* set the mode, clock divisor, parity, stop bits and data size */
2180 atmel_uart_writel(port, ATMEL_US_MR, mode);
2181
2182 /*
2183 * when switching the mode, set the RTS line state according to the
2184 * new mode, otherwise keep the former state
2185 */
2186 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2187 unsigned int rts_state;
2188
2189 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2190 /* let the hardware control the RTS line */
2191 rts_state = ATMEL_US_RTSDIS;
2192 } else {
2193 /* force RTS line to low level */
2194 rts_state = ATMEL_US_RTSEN;
2195 }
2196
2197 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2198 }
2199
2200 /*
2201 * Set the baud rate:
2202 * Fractional baudrate allows to setup output frequency more
2203 * accurately. This feature is enabled only when using normal mode.
2204 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2205 * Currently, OVER is always set to 0 so we get
2206 * baudrate = selected clock / (16 * (CD + FP / 8))
2207 * then
2208 * 8 CD + FP = selected clock / (2 * baudrate)
2209 */
2210 if (atmel_port->has_frac_baudrate &&
2211 (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2212 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2213 cd = div >> 3;
2214 fp = div & ATMEL_US_FP_MASK;
2215 } else {
2216 cd = uart_get_divisor(port, baud);
2217 }
2218
2219 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2220 cd /= 8;
2221 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2222 }
2223 quot = cd | fp << ATMEL_US_FP_OFFSET;
2224
2225 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2226 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2228
2229 /* restore interrupts */
2230 atmel_uart_writel(port, ATMEL_US_IER, imr);
2231
2232 /* CTS flow-control and modem-status interrupts */
2233 if (UART_ENABLE_MS(port, termios->c_cflag))
2234 atmel_enable_ms(port);
2235 else
2236 atmel_disable_ms(port);
2237
2238 spin_unlock_irqrestore(&port->lock, flags);
2239}
2240
2241static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2242{
2243 if (termios->c_line == N_PPS) {
2244 port->flags |= UPF_HARDPPS_CD;
2245 spin_lock_irq(&port->lock);
2246 atmel_enable_ms(port);
2247 spin_unlock_irq(&port->lock);
2248 } else {
2249 port->flags &= ~UPF_HARDPPS_CD;
2250 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2251 spin_lock_irq(&port->lock);
2252 atmel_disable_ms(port);
2253 spin_unlock_irq(&port->lock);
2254 }
2255 }
2256}
2257
2258/*
2259 * Return string describing the specified port
2260 */
2261static const char *atmel_type(struct uart_port *port)
2262{
2263 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2264}
2265
2266/*
2267 * Release the memory region(s) being used by 'port'.
2268 */
2269static void atmel_release_port(struct uart_port *port)
2270{
2271 struct platform_device *pdev = to_platform_device(port->dev);
2272 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2273
2274 release_mem_region(port->mapbase, size);
2275
2276 if (port->flags & UPF_IOREMAP) {
2277 iounmap(port->membase);
2278 port->membase = NULL;
2279 }
2280}
2281
2282/*
2283 * Request the memory region(s) being used by 'port'.
2284 */
2285static int atmel_request_port(struct uart_port *port)
2286{
2287 struct platform_device *pdev = to_platform_device(port->dev);
2288 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2289
2290 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2291 return -EBUSY;
2292
2293 if (port->flags & UPF_IOREMAP) {
2294 port->membase = ioremap(port->mapbase, size);
2295 if (port->membase == NULL) {
2296 release_mem_region(port->mapbase, size);
2297 return -ENOMEM;
2298 }
2299 }
2300
2301 return 0;
2302}
2303
2304/*
2305 * Configure/autoconfigure the port.
2306 */
2307static void atmel_config_port(struct uart_port *port, int flags)
2308{
2309 if (flags & UART_CONFIG_TYPE) {
2310 port->type = PORT_ATMEL;
2311 atmel_request_port(port);
2312 }
2313}
2314
2315/*
2316 * Verify the new serial_struct (for TIOCSSERIAL).
2317 */
2318static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2319{
2320 int ret = 0;
2321 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2322 ret = -EINVAL;
2323 if (port->irq != ser->irq)
2324 ret = -EINVAL;
2325 if (ser->io_type != SERIAL_IO_MEM)
2326 ret = -EINVAL;
2327 if (port->uartclk / 16 != ser->baud_base)
2328 ret = -EINVAL;
2329 if (port->mapbase != (unsigned long)ser->iomem_base)
2330 ret = -EINVAL;
2331 if (port->iobase != ser->port)
2332 ret = -EINVAL;
2333 if (ser->hub6 != 0)
2334 ret = -EINVAL;
2335 return ret;
2336}
2337
2338#ifdef CONFIG_CONSOLE_POLL
2339static int atmel_poll_get_char(struct uart_port *port)
2340{
2341 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2342 cpu_relax();
2343
2344 return atmel_uart_read_char(port);
2345}
2346
2347static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2348{
2349 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2350 cpu_relax();
2351
2352 atmel_uart_write_char(port, ch);
2353}
2354#endif
2355
2356static const struct uart_ops atmel_pops = {
2357 .tx_empty = atmel_tx_empty,
2358 .set_mctrl = atmel_set_mctrl,
2359 .get_mctrl = atmel_get_mctrl,
2360 .stop_tx = atmel_stop_tx,
2361 .start_tx = atmel_start_tx,
2362 .stop_rx = atmel_stop_rx,
2363 .enable_ms = atmel_enable_ms,
2364 .break_ctl = atmel_break_ctl,
2365 .startup = atmel_startup,
2366 .shutdown = atmel_shutdown,
2367 .flush_buffer = atmel_flush_buffer,
2368 .set_termios = atmel_set_termios,
2369 .set_ldisc = atmel_set_ldisc,
2370 .type = atmel_type,
2371 .release_port = atmel_release_port,
2372 .request_port = atmel_request_port,
2373 .config_port = atmel_config_port,
2374 .verify_port = atmel_verify_port,
2375 .pm = atmel_serial_pm,
2376#ifdef CONFIG_CONSOLE_POLL
2377 .poll_get_char = atmel_poll_get_char,
2378 .poll_put_char = atmel_poll_put_char,
2379#endif
2380};
2381
2382/*
2383 * Configure the port from the platform device resource info.
2384 */
2385static int atmel_init_port(struct atmel_uart_port *atmel_port,
2386 struct platform_device *pdev)
2387{
2388 int ret;
2389 struct uart_port *port = &atmel_port->uart;
2390 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2391
2392 atmel_init_property(atmel_port, pdev);
2393 atmel_set_ops(port);
2394
2395 atmel_init_rs485(port, pdev);
2396
2397 port->iotype = UPIO_MEM;
2398 port->flags = UPF_BOOT_AUTOCONF;
2399 port->ops = &atmel_pops;
2400 port->fifosize = 1;
2401 port->dev = &pdev->dev;
2402 port->mapbase = pdev->resource[0].start;
2403 port->irq = pdev->resource[1].start;
2404 port->rs485_config = atmel_config_rs485;
2405
2406 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2407
2408 if (pdata && pdata->regs) {
2409 /* Already mapped by setup code */
2410 port->membase = pdata->regs;
2411 } else {
2412 port->flags |= UPF_IOREMAP;
2413 port->membase = NULL;
2414 }
2415
2416 /* for console, the clock could already be configured */
2417 if (!atmel_port->clk) {
2418 atmel_port->clk = clk_get(&pdev->dev, "usart");
2419 if (IS_ERR(atmel_port->clk)) {
2420 ret = PTR_ERR(atmel_port->clk);
2421 atmel_port->clk = NULL;
2422 return ret;
2423 }
2424 ret = clk_prepare_enable(atmel_port->clk);
2425 if (ret) {
2426 clk_put(atmel_port->clk);
2427 atmel_port->clk = NULL;
2428 return ret;
2429 }
2430 port->uartclk = clk_get_rate(atmel_port->clk);
2431 clk_disable_unprepare(atmel_port->clk);
2432 /* only enable clock when USART is in use */
2433 }
2434
2435 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2436 if (port->rs485.flags & SER_RS485_ENABLED)
2437 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2438 else if (atmel_use_pdc_tx(port)) {
2439 port->fifosize = PDC_BUFFER_SIZE;
2440 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2441 } else {
2442 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2443 }
2444
2445 return 0;
2446}
2447
2448struct platform_device *atmel_default_console_device; /* the serial console device */
2449
2450#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2451static void atmel_console_putchar(struct uart_port *port, int ch)
2452{
2453 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2454 cpu_relax();
2455 atmel_uart_write_char(port, ch);
2456}
2457
2458/*
2459 * Interrupts are disabled on entering
2460 */
2461static void atmel_console_write(struct console *co, const char *s, u_int count)
2462{
2463 struct uart_port *port = &atmel_ports[co->index].uart;
2464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2465 unsigned int status, imr;
2466 unsigned int pdc_tx;
2467
2468 /*
2469 * First, save IMR and then disable interrupts
2470 */
2471 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2472 atmel_uart_writel(port, ATMEL_US_IDR,
2473 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2474
2475 /* Store PDC transmit status and disable it */
2476 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2477 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2478
2479 /* Make sure that tx path is actually able to send characters */
2480 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2481
2482 uart_console_write(port, s, count, atmel_console_putchar);
2483
2484 /*
2485 * Finally, wait for transmitter to become empty
2486 * and restore IMR
2487 */
2488 do {
2489 status = atmel_uart_readl(port, ATMEL_US_CSR);
2490 } while (!(status & ATMEL_US_TXRDY));
2491
2492 /* Restore PDC transmit status */
2493 if (pdc_tx)
2494 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2495
2496 /* set interrupts back the way they were */
2497 atmel_uart_writel(port, ATMEL_US_IER, imr);
2498}
2499
2500/*
2501 * If the port was already initialised (eg, by a boot loader),
2502 * try to determine the current setup.
2503 */
2504static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2505 int *parity, int *bits)
2506{
2507 unsigned int mr, quot;
2508
2509 /*
2510 * If the baud rate generator isn't running, the port wasn't
2511 * initialized by the boot loader.
2512 */
2513 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2514 if (!quot)
2515 return;
2516
2517 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2518 if (mr == ATMEL_US_CHRL_8)
2519 *bits = 8;
2520 else
2521 *bits = 7;
2522
2523 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2524 if (mr == ATMEL_US_PAR_EVEN)
2525 *parity = 'e';
2526 else if (mr == ATMEL_US_PAR_ODD)
2527 *parity = 'o';
2528
2529 /*
2530 * The serial core only rounds down when matching this to a
2531 * supported baud rate. Make sure we don't end up slightly
2532 * lower than one of those, as it would make us fall through
2533 * to a much lower baud rate than we really want.
2534 */
2535 *baud = port->uartclk / (16 * (quot - 1));
2536}
2537
2538static int __init atmel_console_setup(struct console *co, char *options)
2539{
2540 int ret;
2541 struct uart_port *port = &atmel_ports[co->index].uart;
2542 int baud = 115200;
2543 int bits = 8;
2544 int parity = 'n';
2545 int flow = 'n';
2546
2547 if (port->membase == NULL) {
2548 /* Port not initialized yet - delay setup */
2549 return -ENODEV;
2550 }
2551
2552 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2553 if (ret)
2554 return ret;
2555
2556 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2557 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2558 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2559
2560 if (options)
2561 uart_parse_options(options, &baud, &parity, &bits, &flow);
2562 else
2563 atmel_console_get_options(port, &baud, &parity, &bits);
2564
2565 return uart_set_options(port, co, baud, parity, bits, flow);
2566}
2567
2568static struct uart_driver atmel_uart;
2569
2570static struct console atmel_console = {
2571 .name = ATMEL_DEVICENAME,
2572 .write = atmel_console_write,
2573 .device = uart_console_device,
2574 .setup = atmel_console_setup,
2575 .flags = CON_PRINTBUFFER,
2576 .index = -1,
2577 .data = &atmel_uart,
2578};
2579
2580#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2581
2582/*
2583 * Early console initialization (before VM subsystem initialized).
2584 */
2585static int __init atmel_console_init(void)
2586{
2587 int ret;
2588 if (atmel_default_console_device) {
2589 struct atmel_uart_data *pdata =
2590 dev_get_platdata(&atmel_default_console_device->dev);
2591 int id = pdata->num;
2592 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2593
2594 atmel_port->backup_imr = 0;
2595 atmel_port->uart.line = id;
2596
2597 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2598 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2599 if (ret)
2600 return ret;
2601 register_console(&atmel_console);
2602 }
2603
2604 return 0;
2605}
2606
2607console_initcall(atmel_console_init);
2608
2609/*
2610 * Late console initialization.
2611 */
2612static int __init atmel_late_console_init(void)
2613{
2614 if (atmel_default_console_device
2615 && !(atmel_console.flags & CON_ENABLED))
2616 register_console(&atmel_console);
2617
2618 return 0;
2619}
2620
2621core_initcall(atmel_late_console_init);
2622
2623static inline bool atmel_is_console_port(struct uart_port *port)
2624{
2625 return port->cons && port->cons->index == port->line;
2626}
2627
2628#else
2629#define ATMEL_CONSOLE_DEVICE NULL
2630
2631static inline bool atmel_is_console_port(struct uart_port *port)
2632{
2633 return false;
2634}
2635#endif
2636
2637static struct uart_driver atmel_uart = {
2638 .owner = THIS_MODULE,
2639 .driver_name = "atmel_serial",
2640 .dev_name = ATMEL_DEVICENAME,
2641 .major = SERIAL_ATMEL_MAJOR,
2642 .minor = MINOR_START,
2643 .nr = ATMEL_MAX_UART,
2644 .cons = ATMEL_CONSOLE_DEVICE,
2645};
2646
2647#ifdef CONFIG_PM
2648static bool atmel_serial_clk_will_stop(void)
2649{
2650#ifdef CONFIG_ARCH_AT91
2651 return at91_suspend_entering_slow_clock();
2652#else
2653 return false;
2654#endif
2655}
2656
2657static int atmel_serial_suspend(struct platform_device *pdev,
2658 pm_message_t state)
2659{
2660 struct uart_port *port = platform_get_drvdata(pdev);
2661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2662
2663 if (atmel_is_console_port(port) && console_suspend_enabled) {
2664 /* Drain the TX shifter */
2665 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2666 ATMEL_US_TXEMPTY))
2667 cpu_relax();
2668 }
2669
2670 /* we can not wake up if we're running on slow clock */
2671 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2672 if (atmel_serial_clk_will_stop()) {
2673 unsigned long flags;
2674
2675 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2676 atmel_port->suspended = true;
2677 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2678 device_set_wakeup_enable(&pdev->dev, 0);
2679 }
2680
2681 uart_suspend_port(&atmel_uart, port);
2682
2683 return 0;
2684}
2685
2686static int atmel_serial_resume(struct platform_device *pdev)
2687{
2688 struct uart_port *port = platform_get_drvdata(pdev);
2689 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2690 unsigned long flags;
2691
2692 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2693 if (atmel_port->pending) {
2694 atmel_handle_receive(port, atmel_port->pending);
2695 atmel_handle_status(port, atmel_port->pending,
2696 atmel_port->pending_status);
2697 atmel_handle_transmit(port, atmel_port->pending);
2698 atmel_port->pending = 0;
2699 }
2700 atmel_port->suspended = false;
2701 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2702
2703 uart_resume_port(&atmel_uart, port);
2704 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2705
2706 return 0;
2707}
2708#else
2709#define atmel_serial_suspend NULL
2710#define atmel_serial_resume NULL
2711#endif
2712
2713static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2714 struct platform_device *pdev)
2715{
2716 atmel_port->fifo_size = 0;
2717 atmel_port->rts_low = 0;
2718 atmel_port->rts_high = 0;
2719
2720 if (of_property_read_u32(pdev->dev.of_node,
2721 "atmel,fifo-size",
2722 &atmel_port->fifo_size))
2723 return;
2724
2725 if (!atmel_port->fifo_size)
2726 return;
2727
2728 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2729 atmel_port->fifo_size = 0;
2730 dev_err(&pdev->dev, "Invalid FIFO size\n");
2731 return;
2732 }
2733
2734 /*
2735 * 0 <= rts_low <= rts_high <= fifo_size
2736 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2737 * to flush their internal TX FIFO, commonly up to 16 data, before
2738 * actually stopping to send new data. So we try to set the RTS High
2739 * Threshold to a reasonably high value respecting this 16 data
2740 * empirical rule when possible.
2741 */
2742 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2743 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2744 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2745 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2746
2747 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2748 atmel_port->fifo_size);
2749 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2750 atmel_port->rts_high);
2751 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2752 atmel_port->rts_low);
2753}
2754
2755static int atmel_serial_probe(struct platform_device *pdev)
2756{
2757 struct atmel_uart_port *atmel_port;
2758 struct device_node *np = pdev->dev.of_node;
2759 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2760 void *data;
2761 int ret = -ENODEV;
2762 bool rs485_enabled;
2763
2764 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2765
2766 if (np)
2767 ret = of_alias_get_id(np, "serial");
2768 else
2769 if (pdata)
2770 ret = pdata->num;
2771
2772 if (ret < 0)
2773 /* port id not found in platform data nor device-tree aliases:
2774 * auto-enumerate it */
2775 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2776
2777 if (ret >= ATMEL_MAX_UART) {
2778 ret = -ENODEV;
2779 goto err;
2780 }
2781
2782 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2783 /* port already in use */
2784 ret = -EBUSY;
2785 goto err;
2786 }
2787
2788 atmel_port = &atmel_ports[ret];
2789 atmel_port->backup_imr = 0;
2790 atmel_port->uart.line = ret;
2791 atmel_serial_probe_fifos(atmel_port, pdev);
2792
2793 atomic_set(&atmel_port->tasklet_shutdown, 0);
2794 spin_lock_init(&atmel_port->lock_suspended);
2795
2796 ret = atmel_init_port(atmel_port, pdev);
2797 if (ret)
2798 goto err_clear_bit;
2799
2800 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2801 if (IS_ERR(atmel_port->gpios)) {
2802 ret = PTR_ERR(atmel_port->gpios);
2803 goto err_clear_bit;
2804 }
2805
2806 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2807 ret = -ENOMEM;
2808 data = kmalloc(sizeof(struct atmel_uart_char)
2809 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2810 if (!data)
2811 goto err_alloc_ring;
2812 atmel_port->rx_ring.buf = data;
2813 }
2814
2815 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2816
2817 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2818 if (ret)
2819 goto err_add_port;
2820
2821#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2822 if (atmel_is_console_port(&atmel_port->uart)
2823 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2824 /*
2825 * The serial core enabled the clock for us, so undo
2826 * the clk_prepare_enable() in atmel_console_setup()
2827 */
2828 clk_disable_unprepare(atmel_port->clk);
2829 }
2830#endif
2831
2832 device_init_wakeup(&pdev->dev, 1);
2833 platform_set_drvdata(pdev, atmel_port);
2834
2835 /*
2836 * The peripheral clock has been disabled by atmel_init_port():
2837 * enable it before accessing I/O registers
2838 */
2839 clk_prepare_enable(atmel_port->clk);
2840
2841 if (rs485_enabled) {
2842 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2843 ATMEL_US_USMODE_NORMAL);
2844 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2845 ATMEL_US_RTSEN);
2846 }
2847
2848 /*
2849 * Get port name of usart or uart
2850 */
2851 atmel_get_ip_name(&atmel_port->uart);
2852
2853 /*
2854 * The peripheral clock can now safely be disabled till the port
2855 * is used
2856 */
2857 clk_disable_unprepare(atmel_port->clk);
2858
2859 return 0;
2860
2861err_add_port:
2862 kfree(atmel_port->rx_ring.buf);
2863 atmel_port->rx_ring.buf = NULL;
2864err_alloc_ring:
2865 if (!atmel_is_console_port(&atmel_port->uart)) {
2866 clk_put(atmel_port->clk);
2867 atmel_port->clk = NULL;
2868 }
2869err_clear_bit:
2870 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2871err:
2872 return ret;
2873}
2874
2875/*
2876 * Even if the driver is not modular, it makes sense to be able to
2877 * unbind a device: there can be many bound devices, and there are
2878 * situations where dynamic binding and unbinding can be useful.
2879 *
2880 * For example, a connected device can require a specific firmware update
2881 * protocol that needs bitbanging on IO lines, but use the regular serial
2882 * port in the normal case.
2883 */
2884static int atmel_serial_remove(struct platform_device *pdev)
2885{
2886 struct uart_port *port = platform_get_drvdata(pdev);
2887 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2888 int ret = 0;
2889
2890 tasklet_kill(&atmel_port->tasklet_rx);
2891 tasklet_kill(&atmel_port->tasklet_tx);
2892
2893 device_init_wakeup(&pdev->dev, 0);
2894
2895 ret = uart_remove_one_port(&atmel_uart, port);
2896
2897 kfree(atmel_port->rx_ring.buf);
2898
2899 /* "port" is allocated statically, so we shouldn't free it */
2900
2901 clear_bit(port->line, atmel_ports_in_use);
2902
2903 clk_put(atmel_port->clk);
2904 atmel_port->clk = NULL;
2905
2906 return ret;
2907}
2908
2909static struct platform_driver atmel_serial_driver = {
2910 .probe = atmel_serial_probe,
2911 .remove = atmel_serial_remove,
2912 .suspend = atmel_serial_suspend,
2913 .resume = atmel_serial_resume,
2914 .driver = {
2915 .name = "atmel_usart",
2916 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2917 },
2918};
2919
2920static int __init atmel_serial_init(void)
2921{
2922 int ret;
2923
2924 ret = uart_register_driver(&atmel_uart);
2925 if (ret)
2926 return ret;
2927
2928 ret = platform_driver_register(&atmel_serial_driver);
2929 if (ret)
2930 uart_unregister_driver(&atmel_uart);
2931
2932 return ret;
2933}
2934device_initcall(atmel_serial_init);