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1#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8 *
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code.
11 */
12#define pr_fmt(fmt) "hw perfevents: " fmt
13
14#include <linux/bitmap.h>
15#include <linux/cpumask.h>
16#include <linux/cpu_pm.h>
17#include <linux/export.h>
18#include <linux/kernel.h>
19#include <linux/of_device.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/irq.h>
25#include <linux/irqdesc.h>
26
27#include <asm/cputype.h>
28#include <asm/irq_regs.h>
29
30static int
31armpmu_map_cache_event(const unsigned (*cache_map)
32 [PERF_COUNT_HW_CACHE_MAX]
33 [PERF_COUNT_HW_CACHE_OP_MAX]
34 [PERF_COUNT_HW_CACHE_RESULT_MAX],
35 u64 config)
36{
37 unsigned int cache_type, cache_op, cache_result, ret;
38
39 cache_type = (config >> 0) & 0xff;
40 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
41 return -EINVAL;
42
43 cache_op = (config >> 8) & 0xff;
44 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
45 return -EINVAL;
46
47 cache_result = (config >> 16) & 0xff;
48 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
49 return -EINVAL;
50
51 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
52
53 if (ret == CACHE_OP_UNSUPPORTED)
54 return -ENOENT;
55
56 return ret;
57}
58
59static int
60armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
61{
62 int mapping;
63
64 if (config >= PERF_COUNT_HW_MAX)
65 return -EINVAL;
66
67 mapping = (*event_map)[config];
68 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
69}
70
71static int
72armpmu_map_raw_event(u32 raw_event_mask, u64 config)
73{
74 return (int)(config & raw_event_mask);
75}
76
77int
78armpmu_map_event(struct perf_event *event,
79 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
80 const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
84 u32 raw_event_mask)
85{
86 u64 config = event->attr.config;
87 int type = event->attr.type;
88
89 if (type == event->pmu->type)
90 return armpmu_map_raw_event(raw_event_mask, config);
91
92 switch (type) {
93 case PERF_TYPE_HARDWARE:
94 return armpmu_map_hw_event(event_map, config);
95 case PERF_TYPE_HW_CACHE:
96 return armpmu_map_cache_event(cache_map, config);
97 case PERF_TYPE_RAW:
98 return armpmu_map_raw_event(raw_event_mask, config);
99 }
100
101 return -ENOENT;
102}
103
104int armpmu_event_set_period(struct perf_event *event)
105{
106 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
107 struct hw_perf_event *hwc = &event->hw;
108 s64 left = local64_read(&hwc->period_left);
109 s64 period = hwc->sample_period;
110 int ret = 0;
111
112 if (unlikely(left <= -period)) {
113 left = period;
114 local64_set(&hwc->period_left, left);
115 hwc->last_period = period;
116 ret = 1;
117 }
118
119 if (unlikely(left <= 0)) {
120 left += period;
121 local64_set(&hwc->period_left, left);
122 hwc->last_period = period;
123 ret = 1;
124 }
125
126 /*
127 * Limit the maximum period to prevent the counter value
128 * from overtaking the one we are about to program. In
129 * effect we are reducing max_period to account for
130 * interrupt latency (and we are being very conservative).
131 */
132 if (left > (armpmu->max_period >> 1))
133 left = armpmu->max_period >> 1;
134
135 local64_set(&hwc->prev_count, (u64)-left);
136
137 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
138
139 perf_event_update_userpage(event);
140
141 return ret;
142}
143
144u64 armpmu_event_update(struct perf_event *event)
145{
146 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
147 struct hw_perf_event *hwc = &event->hw;
148 u64 delta, prev_raw_count, new_raw_count;
149
150again:
151 prev_raw_count = local64_read(&hwc->prev_count);
152 new_raw_count = armpmu->read_counter(event);
153
154 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
155 new_raw_count) != prev_raw_count)
156 goto again;
157
158 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
159
160 local64_add(delta, &event->count);
161 local64_sub(delta, &hwc->period_left);
162
163 return new_raw_count;
164}
165
166static void
167armpmu_read(struct perf_event *event)
168{
169 armpmu_event_update(event);
170}
171
172static void
173armpmu_stop(struct perf_event *event, int flags)
174{
175 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
176 struct hw_perf_event *hwc = &event->hw;
177
178 /*
179 * ARM pmu always has to update the counter, so ignore
180 * PERF_EF_UPDATE, see comments in armpmu_start().
181 */
182 if (!(hwc->state & PERF_HES_STOPPED)) {
183 armpmu->disable(event);
184 armpmu_event_update(event);
185 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
186 }
187}
188
189static void armpmu_start(struct perf_event *event, int flags)
190{
191 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
192 struct hw_perf_event *hwc = &event->hw;
193
194 /*
195 * ARM pmu always has to reprogram the period, so ignore
196 * PERF_EF_RELOAD, see the comment below.
197 */
198 if (flags & PERF_EF_RELOAD)
199 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
200
201 hwc->state = 0;
202 /*
203 * Set the period again. Some counters can't be stopped, so when we
204 * were stopped we simply disabled the IRQ source and the counter
205 * may have been left counting. If we don't do this step then we may
206 * get an interrupt too soon or *way* too late if the overflow has
207 * happened since disabling.
208 */
209 armpmu_event_set_period(event);
210 armpmu->enable(event);
211}
212
213static void
214armpmu_del(struct perf_event *event, int flags)
215{
216 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
217 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
218 struct hw_perf_event *hwc = &event->hw;
219 int idx = hwc->idx;
220
221 armpmu_stop(event, PERF_EF_UPDATE);
222 hw_events->events[idx] = NULL;
223 clear_bit(idx, hw_events->used_mask);
224 if (armpmu->clear_event_idx)
225 armpmu->clear_event_idx(hw_events, event);
226
227 perf_event_update_userpage(event);
228}
229
230static int
231armpmu_add(struct perf_event *event, int flags)
232{
233 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
234 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
235 struct hw_perf_event *hwc = &event->hw;
236 int idx;
237 int err = 0;
238
239 /* An event following a process won't be stopped earlier */
240 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
241 return -ENOENT;
242
243 perf_pmu_disable(event->pmu);
244
245 /* If we don't have a space for the counter then finish early. */
246 idx = armpmu->get_event_idx(hw_events, event);
247 if (idx < 0) {
248 err = idx;
249 goto out;
250 }
251
252 /*
253 * If there is an event in the counter we are going to use then make
254 * sure it is disabled.
255 */
256 event->hw.idx = idx;
257 armpmu->disable(event);
258 hw_events->events[idx] = event;
259
260 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
261 if (flags & PERF_EF_START)
262 armpmu_start(event, PERF_EF_RELOAD);
263
264 /* Propagate our changes to the userspace mapping. */
265 perf_event_update_userpage(event);
266
267out:
268 perf_pmu_enable(event->pmu);
269 return err;
270}
271
272static int
273validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
274 struct perf_event *event)
275{
276 struct arm_pmu *armpmu;
277
278 if (is_software_event(event))
279 return 1;
280
281 /*
282 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
283 * core perf code won't check that the pmu->ctx == leader->ctx
284 * until after pmu->event_init(event).
285 */
286 if (event->pmu != pmu)
287 return 0;
288
289 if (event->state < PERF_EVENT_STATE_OFF)
290 return 1;
291
292 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
293 return 1;
294
295 armpmu = to_arm_pmu(event->pmu);
296 return armpmu->get_event_idx(hw_events, event) >= 0;
297}
298
299static int
300validate_group(struct perf_event *event)
301{
302 struct perf_event *sibling, *leader = event->group_leader;
303 struct pmu_hw_events fake_pmu;
304
305 /*
306 * Initialise the fake PMU. We only need to populate the
307 * used_mask for the purposes of validation.
308 */
309 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
310
311 if (!validate_event(event->pmu, &fake_pmu, leader))
312 return -EINVAL;
313
314 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
315 if (!validate_event(event->pmu, &fake_pmu, sibling))
316 return -EINVAL;
317 }
318
319 if (!validate_event(event->pmu, &fake_pmu, event))
320 return -EINVAL;
321
322 return 0;
323}
324
325static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
326{
327 struct arm_pmu *armpmu;
328 struct platform_device *plat_device;
329 struct arm_pmu_platdata *plat;
330 int ret;
331 u64 start_clock, finish_clock;
332
333 /*
334 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
335 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
336 * do any necessary shifting, we just need to perform the first
337 * dereference.
338 */
339 armpmu = *(void **)dev;
340 plat_device = armpmu->plat_device;
341 plat = dev_get_platdata(&plat_device->dev);
342
343 start_clock = sched_clock();
344 if (plat && plat->handle_irq)
345 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
346 else
347 ret = armpmu->handle_irq(irq, armpmu);
348 finish_clock = sched_clock();
349
350 perf_sample_event_took(finish_clock - start_clock);
351 return ret;
352}
353
354static void
355armpmu_release_hardware(struct arm_pmu *armpmu)
356{
357 armpmu->free_irq(armpmu);
358}
359
360static int
361armpmu_reserve_hardware(struct arm_pmu *armpmu)
362{
363 int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
364 if (err) {
365 armpmu_release_hardware(armpmu);
366 return err;
367 }
368
369 return 0;
370}
371
372static void
373hw_perf_event_destroy(struct perf_event *event)
374{
375 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
376 atomic_t *active_events = &armpmu->active_events;
377 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
378
379 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
380 armpmu_release_hardware(armpmu);
381 mutex_unlock(pmu_reserve_mutex);
382 }
383}
384
385static int
386event_requires_mode_exclusion(struct perf_event_attr *attr)
387{
388 return attr->exclude_idle || attr->exclude_user ||
389 attr->exclude_kernel || attr->exclude_hv;
390}
391
392static int
393__hw_perf_event_init(struct perf_event *event)
394{
395 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
396 struct hw_perf_event *hwc = &event->hw;
397 int mapping;
398
399 mapping = armpmu->map_event(event);
400
401 if (mapping < 0) {
402 pr_debug("event %x:%llx not supported\n", event->attr.type,
403 event->attr.config);
404 return mapping;
405 }
406
407 /*
408 * We don't assign an index until we actually place the event onto
409 * hardware. Use -1 to signify that we haven't decided where to put it
410 * yet. For SMP systems, each core has it's own PMU so we can't do any
411 * clever allocation or constraints checking at this point.
412 */
413 hwc->idx = -1;
414 hwc->config_base = 0;
415 hwc->config = 0;
416 hwc->event_base = 0;
417
418 /*
419 * Check whether we need to exclude the counter from certain modes.
420 */
421 if ((!armpmu->set_event_filter ||
422 armpmu->set_event_filter(hwc, &event->attr)) &&
423 event_requires_mode_exclusion(&event->attr)) {
424 pr_debug("ARM performance counters do not support "
425 "mode exclusion\n");
426 return -EOPNOTSUPP;
427 }
428
429 /*
430 * Store the event encoding into the config_base field.
431 */
432 hwc->config_base |= (unsigned long)mapping;
433
434 if (!is_sampling_event(event)) {
435 /*
436 * For non-sampling runs, limit the sample_period to half
437 * of the counter width. That way, the new counter value
438 * is far less likely to overtake the previous one unless
439 * you have some serious IRQ latency issues.
440 */
441 hwc->sample_period = armpmu->max_period >> 1;
442 hwc->last_period = hwc->sample_period;
443 local64_set(&hwc->period_left, hwc->sample_period);
444 }
445
446 if (event->group_leader != event) {
447 if (validate_group(event) != 0)
448 return -EINVAL;
449 }
450
451 return 0;
452}
453
454static int armpmu_event_init(struct perf_event *event)
455{
456 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
457 int err = 0;
458 atomic_t *active_events = &armpmu->active_events;
459
460 /*
461 * Reject CPU-affine events for CPUs that are of a different class to
462 * that which this PMU handles. Process-following events (where
463 * event->cpu == -1) can be migrated between CPUs, and thus we have to
464 * reject them later (in armpmu_add) if they're scheduled on a
465 * different class of CPU.
466 */
467 if (event->cpu != -1 &&
468 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
469 return -ENOENT;
470
471 /* does not support taken branch sampling */
472 if (has_branch_stack(event))
473 return -EOPNOTSUPP;
474
475 if (armpmu->map_event(event) == -ENOENT)
476 return -ENOENT;
477
478 event->destroy = hw_perf_event_destroy;
479
480 if (!atomic_inc_not_zero(active_events)) {
481 mutex_lock(&armpmu->reserve_mutex);
482 if (atomic_read(active_events) == 0)
483 err = armpmu_reserve_hardware(armpmu);
484
485 if (!err)
486 atomic_inc(active_events);
487 mutex_unlock(&armpmu->reserve_mutex);
488 }
489
490 if (err)
491 return err;
492
493 err = __hw_perf_event_init(event);
494 if (err)
495 hw_perf_event_destroy(event);
496
497 return err;
498}
499
500static void armpmu_enable(struct pmu *pmu)
501{
502 struct arm_pmu *armpmu = to_arm_pmu(pmu);
503 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
504 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
505
506 /* For task-bound events we may be called on other CPUs */
507 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
508 return;
509
510 if (enabled)
511 armpmu->start(armpmu);
512}
513
514static void armpmu_disable(struct pmu *pmu)
515{
516 struct arm_pmu *armpmu = to_arm_pmu(pmu);
517
518 /* For task-bound events we may be called on other CPUs */
519 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
520 return;
521
522 armpmu->stop(armpmu);
523}
524
525/*
526 * In heterogeneous systems, events are specific to a particular
527 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
528 * the same microarchitecture.
529 */
530static int armpmu_filter_match(struct perf_event *event)
531{
532 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
533 unsigned int cpu = smp_processor_id();
534 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
535}
536
537static ssize_t armpmu_cpumask_show(struct device *dev,
538 struct device_attribute *attr, char *buf)
539{
540 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
541 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
542}
543
544static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
545
546static struct attribute *armpmu_common_attrs[] = {
547 &dev_attr_cpus.attr,
548 NULL,
549};
550
551static struct attribute_group armpmu_common_attr_group = {
552 .attrs = armpmu_common_attrs,
553};
554
555static void armpmu_init(struct arm_pmu *armpmu)
556{
557 atomic_set(&armpmu->active_events, 0);
558 mutex_init(&armpmu->reserve_mutex);
559
560 armpmu->pmu = (struct pmu) {
561 .pmu_enable = armpmu_enable,
562 .pmu_disable = armpmu_disable,
563 .event_init = armpmu_event_init,
564 .add = armpmu_add,
565 .del = armpmu_del,
566 .start = armpmu_start,
567 .stop = armpmu_stop,
568 .read = armpmu_read,
569 .filter_match = armpmu_filter_match,
570 .attr_groups = armpmu->attr_groups,
571 };
572 armpmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
573 &armpmu_common_attr_group;
574}
575
576/* Set at runtime when we know what CPU type we are. */
577static struct arm_pmu *__oprofile_cpu_pmu;
578
579/*
580 * Despite the names, these two functions are CPU-specific and are used
581 * by the OProfile/perf code.
582 */
583const char *perf_pmu_name(void)
584{
585 if (!__oprofile_cpu_pmu)
586 return NULL;
587
588 return __oprofile_cpu_pmu->name;
589}
590EXPORT_SYMBOL_GPL(perf_pmu_name);
591
592int perf_num_counters(void)
593{
594 int max_events = 0;
595
596 if (__oprofile_cpu_pmu != NULL)
597 max_events = __oprofile_cpu_pmu->num_events;
598
599 return max_events;
600}
601EXPORT_SYMBOL_GPL(perf_num_counters);
602
603static void cpu_pmu_enable_percpu_irq(void *data)
604{
605 int irq = *(int *)data;
606
607 enable_percpu_irq(irq, IRQ_TYPE_NONE);
608}
609
610static void cpu_pmu_disable_percpu_irq(void *data)
611{
612 int irq = *(int *)data;
613
614 disable_percpu_irq(irq);
615}
616
617static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
618{
619 int i, irq, irqs;
620 struct platform_device *pmu_device = cpu_pmu->plat_device;
621 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
622
623 irqs = min(pmu_device->num_resources, num_possible_cpus());
624
625 irq = platform_get_irq(pmu_device, 0);
626 if (irq > 0 && irq_is_percpu(irq)) {
627 on_each_cpu_mask(&cpu_pmu->supported_cpus,
628 cpu_pmu_disable_percpu_irq, &irq, 1);
629 free_percpu_irq(irq, &hw_events->percpu_pmu);
630 } else {
631 for (i = 0; i < irqs; ++i) {
632 int cpu = i;
633
634 if (cpu_pmu->irq_affinity)
635 cpu = cpu_pmu->irq_affinity[i];
636
637 if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
638 continue;
639 irq = platform_get_irq(pmu_device, i);
640 if (irq > 0)
641 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
642 }
643 }
644}
645
646static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
647{
648 int i, err, irq, irqs;
649 struct platform_device *pmu_device = cpu_pmu->plat_device;
650 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
651
652 if (!pmu_device)
653 return -ENODEV;
654
655 irqs = min(pmu_device->num_resources, num_possible_cpus());
656 if (irqs < 1) {
657 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
658 return 0;
659 }
660
661 irq = platform_get_irq(pmu_device, 0);
662 if (irq > 0 && irq_is_percpu(irq)) {
663 err = request_percpu_irq(irq, handler, "arm-pmu",
664 &hw_events->percpu_pmu);
665 if (err) {
666 pr_err("unable to request IRQ%d for ARM PMU counters\n",
667 irq);
668 return err;
669 }
670
671 on_each_cpu_mask(&cpu_pmu->supported_cpus,
672 cpu_pmu_enable_percpu_irq, &irq, 1);
673 } else {
674 for (i = 0; i < irqs; ++i) {
675 int cpu = i;
676
677 err = 0;
678 irq = platform_get_irq(pmu_device, i);
679 if (irq < 0)
680 continue;
681
682 if (cpu_pmu->irq_affinity)
683 cpu = cpu_pmu->irq_affinity[i];
684
685 /*
686 * If we have a single PMU interrupt that we can't shift,
687 * assume that we're running on a uniprocessor machine and
688 * continue. Otherwise, continue without this interrupt.
689 */
690 if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
691 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
692 irq, cpu);
693 continue;
694 }
695
696 err = request_irq(irq, handler,
697 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
698 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
699 if (err) {
700 pr_err("unable to request IRQ%d for ARM PMU counters\n",
701 irq);
702 return err;
703 }
704
705 cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
706 }
707 }
708
709 return 0;
710}
711
712/*
713 * PMU hardware loses all context when a CPU goes offline.
714 * When a CPU is hotplugged back in, since some hardware registers are
715 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
716 * junk values out of them.
717 */
718static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
719{
720 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
721
722 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
723 return 0;
724 if (pmu->reset)
725 pmu->reset(pmu);
726 return 0;
727}
728
729#ifdef CONFIG_CPU_PM
730static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
731{
732 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
733 struct perf_event *event;
734 int idx;
735
736 for (idx = 0; idx < armpmu->num_events; idx++) {
737 /*
738 * If the counter is not used skip it, there is no
739 * need of stopping/restarting it.
740 */
741 if (!test_bit(idx, hw_events->used_mask))
742 continue;
743
744 event = hw_events->events[idx];
745
746 switch (cmd) {
747 case CPU_PM_ENTER:
748 /*
749 * Stop and update the counter
750 */
751 armpmu_stop(event, PERF_EF_UPDATE);
752 break;
753 case CPU_PM_EXIT:
754 case CPU_PM_ENTER_FAILED:
755 /*
756 * Restore and enable the counter.
757 * armpmu_start() indirectly calls
758 *
759 * perf_event_update_userpage()
760 *
761 * that requires RCU read locking to be functional,
762 * wrap the call within RCU_NONIDLE to make the
763 * RCU subsystem aware this cpu is not idle from
764 * an RCU perspective for the armpmu_start() call
765 * duration.
766 */
767 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
768 break;
769 default:
770 break;
771 }
772 }
773}
774
775static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
776 void *v)
777{
778 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
779 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
780 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
781
782 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
783 return NOTIFY_DONE;
784
785 /*
786 * Always reset the PMU registers on power-up even if
787 * there are no events running.
788 */
789 if (cmd == CPU_PM_EXIT && armpmu->reset)
790 armpmu->reset(armpmu);
791
792 if (!enabled)
793 return NOTIFY_OK;
794
795 switch (cmd) {
796 case CPU_PM_ENTER:
797 armpmu->stop(armpmu);
798 cpu_pm_pmu_setup(armpmu, cmd);
799 break;
800 case CPU_PM_EXIT:
801 cpu_pm_pmu_setup(armpmu, cmd);
802 case CPU_PM_ENTER_FAILED:
803 armpmu->start(armpmu);
804 break;
805 default:
806 return NOTIFY_DONE;
807 }
808
809 return NOTIFY_OK;
810}
811
812static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
813{
814 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
815 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
816}
817
818static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
819{
820 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
821}
822#else
823static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
824static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
825#endif
826
827static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
828{
829 int err;
830 int cpu;
831 struct pmu_hw_events __percpu *cpu_hw_events;
832
833 cpu_hw_events = alloc_percpu(struct pmu_hw_events);
834 if (!cpu_hw_events)
835 return -ENOMEM;
836
837 err = cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
838 &cpu_pmu->node);
839 if (err)
840 goto out_free;
841
842 err = cpu_pm_pmu_register(cpu_pmu);
843 if (err)
844 goto out_unregister;
845
846 for_each_possible_cpu(cpu) {
847 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
848 raw_spin_lock_init(&events->pmu_lock);
849 events->percpu_pmu = cpu_pmu;
850 }
851
852 cpu_pmu->hw_events = cpu_hw_events;
853 cpu_pmu->request_irq = cpu_pmu_request_irq;
854 cpu_pmu->free_irq = cpu_pmu_free_irq;
855
856 /* Ensure the PMU has sane values out of reset. */
857 if (cpu_pmu->reset)
858 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
859 cpu_pmu, 1);
860
861 /* If no interrupts available, set the corresponding capability flag */
862 if (!platform_get_irq(cpu_pmu->plat_device, 0))
863 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
864
865 /*
866 * This is a CPU PMU potentially in a heterogeneous configuration (e.g.
867 * big.LITTLE). This is not an uncore PMU, and we have taken ctx
868 * sharing into account (e.g. with our pmu::filter_match callback and
869 * pmu::event_init group validation).
870 */
871 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
872
873 return 0;
874
875out_unregister:
876 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
877 &cpu_pmu->node);
878out_free:
879 free_percpu(cpu_hw_events);
880 return err;
881}
882
883static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
884{
885 cpu_pm_pmu_unregister(cpu_pmu);
886 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
887 &cpu_pmu->node);
888 free_percpu(cpu_pmu->hw_events);
889}
890
891/*
892 * CPU PMU identification and probing.
893 */
894static int probe_current_pmu(struct arm_pmu *pmu,
895 const struct pmu_probe_info *info)
896{
897 int cpu = get_cpu();
898 unsigned int cpuid = read_cpuid_id();
899 int ret = -ENODEV;
900
901 pr_info("probing PMU on CPU %d\n", cpu);
902
903 for (; info->init != NULL; info++) {
904 if ((cpuid & info->mask) != info->cpuid)
905 continue;
906 ret = info->init(pmu);
907 break;
908 }
909
910 put_cpu();
911 return ret;
912}
913
914static int of_pmu_irq_cfg(struct arm_pmu *pmu)
915{
916 int *irqs, i = 0;
917 bool using_spi = false;
918 struct platform_device *pdev = pmu->plat_device;
919
920 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
921 if (!irqs)
922 return -ENOMEM;
923
924 do {
925 struct device_node *dn;
926 int cpu, irq;
927
928 /* See if we have an affinity entry */
929 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
930 if (!dn)
931 break;
932
933 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
934 irq = platform_get_irq(pdev, i);
935 if (irq > 0) {
936 bool spi = !irq_is_percpu(irq);
937
938 if (i > 0 && spi != using_spi) {
939 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
940 dn->name);
941 of_node_put(dn);
942 kfree(irqs);
943 return -EINVAL;
944 }
945
946 using_spi = spi;
947 }
948
949 /* Now look up the logical CPU number */
950 for_each_possible_cpu(cpu) {
951 struct device_node *cpu_dn;
952
953 cpu_dn = of_cpu_device_node_get(cpu);
954 of_node_put(cpu_dn);
955
956 if (dn == cpu_dn)
957 break;
958 }
959
960 if (cpu >= nr_cpu_ids) {
961 pr_warn("Failed to find logical CPU for %s\n",
962 dn->name);
963 of_node_put(dn);
964 cpumask_setall(&pmu->supported_cpus);
965 break;
966 }
967 of_node_put(dn);
968
969 /* For SPIs, we need to track the affinity per IRQ */
970 if (using_spi) {
971 if (i >= pdev->num_resources)
972 break;
973
974 irqs[i] = cpu;
975 }
976
977 /* Keep track of the CPUs containing this PMU type */
978 cpumask_set_cpu(cpu, &pmu->supported_cpus);
979 i++;
980 } while (1);
981
982 /* If we didn't manage to parse anything, try the interrupt affinity */
983 if (cpumask_weight(&pmu->supported_cpus) == 0) {
984 int irq = platform_get_irq(pdev, 0);
985
986 if (irq > 0 && irq_is_percpu(irq)) {
987 /* If using PPIs, check the affinity of the partition */
988 int ret;
989
990 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
991 if (ret) {
992 kfree(irqs);
993 return ret;
994 }
995 } else {
996 /* Otherwise default to all CPUs */
997 cpumask_setall(&pmu->supported_cpus);
998 }
999 }
1000
1001 /* If we matched up the IRQ affinities, use them to route the SPIs */
1002 if (using_spi && i == pdev->num_resources)
1003 pmu->irq_affinity = irqs;
1004 else
1005 kfree(irqs);
1006
1007 return 0;
1008}
1009
1010int arm_pmu_device_probe(struct platform_device *pdev,
1011 const struct of_device_id *of_table,
1012 const struct pmu_probe_info *probe_table)
1013{
1014 const struct of_device_id *of_id;
1015 const int (*init_fn)(struct arm_pmu *);
1016 struct device_node *node = pdev->dev.of_node;
1017 struct arm_pmu *pmu;
1018 int ret = -ENODEV;
1019
1020 pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
1021 if (!pmu) {
1022 pr_info("failed to allocate PMU device!\n");
1023 return -ENOMEM;
1024 }
1025
1026 armpmu_init(pmu);
1027
1028 pmu->plat_device = pdev;
1029
1030 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1031 init_fn = of_id->data;
1032
1033 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1034 "secure-reg-access");
1035
1036 /* arm64 systems boot only as non-secure */
1037 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1038 pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1039 pmu->secure_access = false;
1040 }
1041
1042 ret = of_pmu_irq_cfg(pmu);
1043 if (!ret)
1044 ret = init_fn(pmu);
1045 } else if (probe_table) {
1046 cpumask_setall(&pmu->supported_cpus);
1047 ret = probe_current_pmu(pmu, probe_table);
1048 }
1049
1050 if (ret) {
1051 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1052 goto out_free;
1053 }
1054
1055
1056 ret = cpu_pmu_init(pmu);
1057 if (ret)
1058 goto out_free;
1059
1060 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1061 if (ret)
1062 goto out_destroy;
1063
1064 if (!__oprofile_cpu_pmu)
1065 __oprofile_cpu_pmu = pmu;
1066
1067 pr_info("enabled with %s PMU driver, %d counters available\n",
1068 pmu->name, pmu->num_events);
1069
1070 return 0;
1071
1072out_destroy:
1073 cpu_pmu_destroy(pmu);
1074out_free:
1075 pr_info("%s: failed to register PMU devices!\n",
1076 of_node_full_name(node));
1077 kfree(pmu->irq_affinity);
1078 kfree(pmu);
1079 return ret;
1080}
1081
1082static int arm_pmu_hp_init(void)
1083{
1084 int ret;
1085
1086 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
1087 "perf/arm/pmu:starting",
1088 arm_perf_starting_cpu, NULL);
1089 if (ret)
1090 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1091 ret);
1092 return ret;
1093}
1094subsys_initcall(arm_pmu_hp_init);