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1/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "bcm-phy-lib.h"
15#include <linux/brcmphy.h>
16#include <linux/export.h>
17#include <linux/mdio.h>
18#include <linux/module.h>
19#include <linux/phy.h>
20#include <linux/ethtool.h>
21
22#define MII_BCM_CHANNEL_WIDTH 0x2000
23#define BCM_CL45VEN_EEE_ADV 0x3c
24
25int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
26{
27 int rc;
28
29 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
30 if (rc < 0)
31 return rc;
32
33 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
34}
35EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
36
37int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
38{
39 int val;
40
41 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
42 if (val < 0)
43 return val;
44
45 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
46
47 /* Restore default value. It's O.K. if this write fails. */
48 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
49
50 return val;
51}
52EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
53
54int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
55{
56 /* The register must be written to both the Shadow Register Select and
57 * the Shadow Read Register Selector
58 */
59 phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
60 regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
61 return phy_read(phydev, MII_BCM54XX_AUX_CTL);
62}
63EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
64
65int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
66{
67 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
68}
69EXPORT_SYMBOL(bcm54xx_auxctl_write);
70
71int bcm_phy_write_misc(struct phy_device *phydev,
72 u16 reg, u16 chl, u16 val)
73{
74 int rc;
75 int tmp;
76
77 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
78 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
79 if (rc < 0)
80 return rc;
81
82 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
83 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
84 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
85 if (rc < 0)
86 return rc;
87
88 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
89 rc = bcm_phy_write_exp(phydev, tmp, val);
90
91 return rc;
92}
93EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
94
95int bcm_phy_read_misc(struct phy_device *phydev,
96 u16 reg, u16 chl)
97{
98 int rc;
99 int tmp;
100
101 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
102 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
103 if (rc < 0)
104 return rc;
105
106 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
107 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
108 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
109 if (rc < 0)
110 return rc;
111
112 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
113 rc = bcm_phy_read_exp(phydev, tmp);
114
115 return rc;
116}
117EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
118
119int bcm_phy_ack_intr(struct phy_device *phydev)
120{
121 int reg;
122
123 /* Clear pending interrupts. */
124 reg = phy_read(phydev, MII_BCM54XX_ISR);
125 if (reg < 0)
126 return reg;
127
128 return 0;
129}
130EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
131
132int bcm_phy_config_intr(struct phy_device *phydev)
133{
134 int reg;
135
136 reg = phy_read(phydev, MII_BCM54XX_ECR);
137 if (reg < 0)
138 return reg;
139
140 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
141 reg &= ~MII_BCM54XX_ECR_IM;
142 else
143 reg |= MII_BCM54XX_ECR_IM;
144
145 return phy_write(phydev, MII_BCM54XX_ECR, reg);
146}
147EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
148
149int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
150{
151 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
152 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
153}
154EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
155
156int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
157 u16 val)
158{
159 return phy_write(phydev, MII_BCM54XX_SHD,
160 MII_BCM54XX_SHD_WRITE |
161 MII_BCM54XX_SHD_VAL(shadow) |
162 MII_BCM54XX_SHD_DATA(val));
163}
164EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
165
166int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
167{
168 int val;
169
170 if (dll_pwr_down) {
171 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
172 if (val < 0)
173 return val;
174
175 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
176 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
177 }
178
179 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
180 if (val < 0)
181 return val;
182
183 /* Clear APD bits */
184 val &= BCM_APD_CLR_MASK;
185
186 if (phydev->autoneg == AUTONEG_ENABLE)
187 val |= BCM54XX_SHD_APD_EN;
188 else
189 val |= BCM_NO_ANEG_APD_EN;
190
191 /* Enable energy detect single link pulse for easy wakeup */
192 val |= BCM_APD_SINGLELP_EN;
193
194 /* Enable Auto Power-Down (APD) for the PHY */
195 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
196}
197EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
198
199int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
200{
201 int val;
202
203 /* Enable EEE at PHY level */
204 val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
205 MDIO_MMD_AN);
206 if (val < 0)
207 return val;
208
209 if (enable)
210 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
211 else
212 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
213
214 phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
215 MDIO_MMD_AN, (u32)val);
216
217 /* Advertise EEE */
218 val = phy_read_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,
219 MDIO_MMD_AN);
220 if (val < 0)
221 return val;
222
223 if (enable)
224 val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
225 else
226 val &= ~(MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
227
228 phy_write_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV,
229 MDIO_MMD_AN, (u32)val);
230
231 return 0;
232}
233EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
234
235int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
236{
237 int val;
238
239 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
240 if (val < 0)
241 return val;
242
243 /* Check if wirespeed is enabled or not */
244 if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
245 *count = DOWNSHIFT_DEV_DISABLE;
246 return 0;
247 }
248
249 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
250 if (val < 0)
251 return val;
252
253 /* Downgrade after one link attempt */
254 if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
255 *count = 1;
256 } else {
257 /* Downgrade after configured retry count */
258 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
259 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
260 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
261 }
262
263 return 0;
264}
265EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
266
267int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
268{
269 int val = 0, ret = 0;
270
271 /* Range check the number given */
272 if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
273 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
274 count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
275 return -ERANGE;
276 }
277
278 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
279 if (val < 0)
280 return val;
281
282 /* Se the write enable bit */
283 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
284
285 if (count == DOWNSHIFT_DEV_DISABLE) {
286 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
287 return bcm54xx_auxctl_write(phydev,
288 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
289 val);
290 } else {
291 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
292 ret = bcm54xx_auxctl_write(phydev,
293 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
294 val);
295 if (ret < 0)
296 return ret;
297 }
298
299 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
300 val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
301 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
302 BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
303
304 switch (count) {
305 case 1:
306 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
307 break;
308 case DOWNSHIFT_DEV_DEFAULT_COUNT:
309 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
310 break;
311 default:
312 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
313 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
314 break;
315 }
316
317 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
318}
319EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
320
321struct bcm_phy_hw_stat {
322 const char *string;
323 u8 reg;
324 u8 shift;
325 u8 bits;
326};
327
328/* Counters freeze at either 0xffff or 0xff, better than nothing */
329static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
330 { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
331 { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
332 { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
333 { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
334 { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
335};
336
337int bcm_phy_get_sset_count(struct phy_device *phydev)
338{
339 return ARRAY_SIZE(bcm_phy_hw_stats);
340}
341EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
342
343void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
344{
345 unsigned int i;
346
347 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
348 memcpy(data + i * ETH_GSTRING_LEN,
349 bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
350}
351EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
352
353#ifndef UINT64_MAX
354#define UINT64_MAX (u64)(~((u64)0))
355#endif
356
357/* Caller is supposed to provide appropriate storage for the library code to
358 * access the shadow copy
359 */
360static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
361 unsigned int i)
362{
363 struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
364 int val;
365 u64 ret;
366
367 val = phy_read(phydev, stat.reg);
368 if (val < 0) {
369 ret = UINT64_MAX;
370 } else {
371 val >>= stat.shift;
372 val = val & ((1 << stat.bits) - 1);
373 shadow[i] += val;
374 ret = shadow[i];
375 }
376
377 return ret;
378}
379
380void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
381 struct ethtool_stats *stats, u64 *data)
382{
383 unsigned int i;
384
385 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
386 data[i] = bcm_phy_get_stat(phydev, shadow, i);
387}
388EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
389
390MODULE_DESCRIPTION("Broadcom PHY Library");
391MODULE_LICENSE("GPL v2");
392MODULE_AUTHOR("Broadcom Corporation");