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1/*
2 * This file is part of STM32 ADC driver
3 *
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
6 *
7 * License type: GPLv2
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.
16 * See the GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/iio/iio.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/of.h>
30
31#include "stm32-adc-core.h"
32
33/* STM32F4 - Registers for each ADC instance */
34#define STM32F4_ADC_SR 0x00
35#define STM32F4_ADC_CR1 0x04
36#define STM32F4_ADC_CR2 0x08
37#define STM32F4_ADC_SMPR1 0x0C
38#define STM32F4_ADC_SMPR2 0x10
39#define STM32F4_ADC_HTR 0x24
40#define STM32F4_ADC_LTR 0x28
41#define STM32F4_ADC_SQR1 0x2C
42#define STM32F4_ADC_SQR2 0x30
43#define STM32F4_ADC_SQR3 0x34
44#define STM32F4_ADC_JSQR 0x38
45#define STM32F4_ADC_JDR1 0x3C
46#define STM32F4_ADC_JDR2 0x40
47#define STM32F4_ADC_JDR3 0x44
48#define STM32F4_ADC_JDR4 0x48
49#define STM32F4_ADC_DR 0x4C
50
51/* STM32F4_ADC_SR - bit fields */
52#define STM32F4_STRT BIT(4)
53#define STM32F4_EOC BIT(1)
54
55/* STM32F4_ADC_CR1 - bit fields */
56#define STM32F4_SCAN BIT(8)
57#define STM32F4_EOCIE BIT(5)
58
59/* STM32F4_ADC_CR2 - bit fields */
60#define STM32F4_SWSTART BIT(30)
61#define STM32F4_EXTEN_MASK GENMASK(29, 28)
62#define STM32F4_EOCS BIT(10)
63#define STM32F4_ADON BIT(0)
64
65/* STM32F4_ADC_SQR1 - bit fields */
66#define STM32F4_L_SHIFT 20
67#define STM32F4_L_MASK GENMASK(23, 20)
68
69/* STM32F4_ADC_SQR3 - bit fields */
70#define STM32F4_SQ1_SHIFT 0
71#define STM32F4_SQ1_MASK GENMASK(4, 0)
72
73#define STM32_ADC_TIMEOUT_US 100000
74#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
75
76/**
77 * struct stm32_adc - private data of each ADC IIO instance
78 * @common: reference to ADC block common data
79 * @offset: ADC instance register offset in ADC block
80 * @completion: end of single conversion completion
81 * @buffer: data buffer
82 * @clk: clock for this adc instance
83 * @irq: interrupt for this adc instance
84 * @lock: spinlock
85 */
86struct stm32_adc {
87 struct stm32_adc_common *common;
88 u32 offset;
89 struct completion completion;
90 u16 *buffer;
91 struct clk *clk;
92 int irq;
93 spinlock_t lock; /* interrupt lock */
94};
95
96/**
97 * struct stm32_adc_chan_spec - specification of stm32 adc channel
98 * @type: IIO channel type
99 * @channel: channel number (single ended)
100 * @name: channel name (single ended)
101 */
102struct stm32_adc_chan_spec {
103 enum iio_chan_type type;
104 int channel;
105 const char *name;
106};
107
108/* Input definitions common for all STM32F4 instances */
109static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
110 { IIO_VOLTAGE, 0, "in0" },
111 { IIO_VOLTAGE, 1, "in1" },
112 { IIO_VOLTAGE, 2, "in2" },
113 { IIO_VOLTAGE, 3, "in3" },
114 { IIO_VOLTAGE, 4, "in4" },
115 { IIO_VOLTAGE, 5, "in5" },
116 { IIO_VOLTAGE, 6, "in6" },
117 { IIO_VOLTAGE, 7, "in7" },
118 { IIO_VOLTAGE, 8, "in8" },
119 { IIO_VOLTAGE, 9, "in9" },
120 { IIO_VOLTAGE, 10, "in10" },
121 { IIO_VOLTAGE, 11, "in11" },
122 { IIO_VOLTAGE, 12, "in12" },
123 { IIO_VOLTAGE, 13, "in13" },
124 { IIO_VOLTAGE, 14, "in14" },
125 { IIO_VOLTAGE, 15, "in15" },
126};
127
128/**
129 * STM32 ADC registers access routines
130 * @adc: stm32 adc instance
131 * @reg: reg offset in adc instance
132 *
133 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
134 * for adc1, adc2 and adc3.
135 */
136static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
137{
138 return readl_relaxed(adc->common->base + adc->offset + reg);
139}
140
141static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
142{
143 return readw_relaxed(adc->common->base + adc->offset + reg);
144}
145
146static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
147{
148 writel_relaxed(val, adc->common->base + adc->offset + reg);
149}
150
151static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
152{
153 unsigned long flags;
154
155 spin_lock_irqsave(&adc->lock, flags);
156 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
157 spin_unlock_irqrestore(&adc->lock, flags);
158}
159
160static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
161{
162 unsigned long flags;
163
164 spin_lock_irqsave(&adc->lock, flags);
165 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
166 spin_unlock_irqrestore(&adc->lock, flags);
167}
168
169/**
170 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
171 * @adc: stm32 adc instance
172 */
173static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
174{
175 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
176};
177
178/**
179 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
180 * @adc: stm32 adc instance
181 */
182static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
183{
184 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
185}
186
187/**
188 * stm32_adc_start_conv() - Start conversions for regular channels.
189 * @adc: stm32 adc instance
190 */
191static void stm32_adc_start_conv(struct stm32_adc *adc)
192{
193 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
194 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
195
196 /* Wait for Power-up time (tSTAB from datasheet) */
197 usleep_range(2, 3);
198
199 /* Software start ? (e.g. trigger detection disabled ?) */
200 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
201 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
202}
203
204static void stm32_adc_stop_conv(struct stm32_adc *adc)
205{
206 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
207 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
208
209 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
210 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_ADON);
211}
212
213/**
214 * stm32_adc_single_conv() - Performs a single conversion
215 * @indio_dev: IIO device
216 * @chan: IIO channel
217 * @res: conversion result
218 *
219 * The function performs a single conversion on a given channel:
220 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
221 * - Use SW trigger
222 * - Start conversion, then wait for interrupt completion.
223 */
224static int stm32_adc_single_conv(struct iio_dev *indio_dev,
225 const struct iio_chan_spec *chan,
226 int *res)
227{
228 struct stm32_adc *adc = iio_priv(indio_dev);
229 long timeout;
230 u32 val;
231 u16 result;
232 int ret;
233
234 reinit_completion(&adc->completion);
235
236 adc->buffer = &result;
237
238 /* Program chan number in regular sequence */
239 val = stm32_adc_readl(adc, STM32F4_ADC_SQR3);
240 val &= ~STM32F4_SQ1_MASK;
241 val |= chan->channel << STM32F4_SQ1_SHIFT;
242 stm32_adc_writel(adc, STM32F4_ADC_SQR3, val);
243
244 /* Set regular sequence len (0 for 1 conversion) */
245 stm32_adc_clr_bits(adc, STM32F4_ADC_SQR1, STM32F4_L_MASK);
246
247 /* Trigger detection disabled (conversion can be launched in SW) */
248 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
249
250 stm32_adc_conv_irq_enable(adc);
251
252 stm32_adc_start_conv(adc);
253
254 timeout = wait_for_completion_interruptible_timeout(
255 &adc->completion, STM32_ADC_TIMEOUT);
256 if (timeout == 0) {
257 ret = -ETIMEDOUT;
258 } else if (timeout < 0) {
259 ret = timeout;
260 } else {
261 *res = result;
262 ret = IIO_VAL_INT;
263 }
264
265 stm32_adc_stop_conv(adc);
266
267 stm32_adc_conv_irq_disable(adc);
268
269 return ret;
270}
271
272static int stm32_adc_read_raw(struct iio_dev *indio_dev,
273 struct iio_chan_spec const *chan,
274 int *val, int *val2, long mask)
275{
276 struct stm32_adc *adc = iio_priv(indio_dev);
277 int ret;
278
279 switch (mask) {
280 case IIO_CHAN_INFO_RAW:
281 ret = iio_device_claim_direct_mode(indio_dev);
282 if (ret)
283 return ret;
284 if (chan->type == IIO_VOLTAGE)
285 ret = stm32_adc_single_conv(indio_dev, chan, val);
286 else
287 ret = -EINVAL;
288 iio_device_release_direct_mode(indio_dev);
289 return ret;
290
291 case IIO_CHAN_INFO_SCALE:
292 *val = adc->common->vref_mv;
293 *val2 = chan->scan_type.realbits;
294 return IIO_VAL_FRACTIONAL_LOG2;
295
296 default:
297 return -EINVAL;
298 }
299}
300
301static irqreturn_t stm32_adc_isr(int irq, void *data)
302{
303 struct stm32_adc *adc = data;
304 u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
305
306 if (status & STM32F4_EOC) {
307 *adc->buffer = stm32_adc_readw(adc, STM32F4_ADC_DR);
308 complete(&adc->completion);
309 return IRQ_HANDLED;
310 }
311
312 return IRQ_NONE;
313}
314
315static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
316 const struct of_phandle_args *iiospec)
317{
318 int i;
319
320 for (i = 0; i < indio_dev->num_channels; i++)
321 if (indio_dev->channels[i].channel == iiospec->args[0])
322 return i;
323
324 return -EINVAL;
325}
326
327/**
328 * stm32_adc_debugfs_reg_access - read or write register value
329 *
330 * To read a value from an ADC register:
331 * echo [ADC reg offset] > direct_reg_access
332 * cat direct_reg_access
333 *
334 * To write a value in a ADC register:
335 * echo [ADC_reg_offset] [value] > direct_reg_access
336 */
337static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
338 unsigned reg, unsigned writeval,
339 unsigned *readval)
340{
341 struct stm32_adc *adc = iio_priv(indio_dev);
342
343 if (!readval)
344 stm32_adc_writel(adc, reg, writeval);
345 else
346 *readval = stm32_adc_readl(adc, reg);
347
348 return 0;
349}
350
351static const struct iio_info stm32_adc_iio_info = {
352 .read_raw = stm32_adc_read_raw,
353 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
354 .of_xlate = stm32_adc_of_xlate,
355 .driver_module = THIS_MODULE,
356};
357
358static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
359 struct iio_chan_spec *chan,
360 const struct stm32_adc_chan_spec *channel,
361 int scan_index)
362{
363 chan->type = channel->type;
364 chan->channel = channel->channel;
365 chan->datasheet_name = channel->name;
366 chan->scan_index = scan_index;
367 chan->indexed = 1;
368 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
369 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
370 chan->scan_type.sign = 'u';
371 chan->scan_type.realbits = 12;
372 chan->scan_type.storagebits = 16;
373}
374
375static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
376{
377 struct device_node *node = indio_dev->dev.of_node;
378 struct property *prop;
379 const __be32 *cur;
380 struct iio_chan_spec *channels;
381 int scan_index = 0, num_channels;
382 u32 val;
383
384 num_channels = of_property_count_u32_elems(node, "st,adc-channels");
385 if (num_channels < 0 ||
386 num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
387 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
388 return num_channels < 0 ? num_channels : -EINVAL;
389 }
390
391 channels = devm_kcalloc(&indio_dev->dev, num_channels,
392 sizeof(struct iio_chan_spec), GFP_KERNEL);
393 if (!channels)
394 return -ENOMEM;
395
396 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
397 if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
398 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
399 return -EINVAL;
400 }
401 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
402 &stm32f4_adc123_channels[val],
403 scan_index);
404 scan_index++;
405 }
406
407 indio_dev->num_channels = scan_index;
408 indio_dev->channels = channels;
409
410 return 0;
411}
412
413static int stm32_adc_probe(struct platform_device *pdev)
414{
415 struct iio_dev *indio_dev;
416 struct stm32_adc *adc;
417 int ret;
418
419 if (!pdev->dev.of_node)
420 return -ENODEV;
421
422 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
423 if (!indio_dev)
424 return -ENOMEM;
425
426 adc = iio_priv(indio_dev);
427 adc->common = dev_get_drvdata(pdev->dev.parent);
428 spin_lock_init(&adc->lock);
429 init_completion(&adc->completion);
430
431 indio_dev->name = dev_name(&pdev->dev);
432 indio_dev->dev.parent = &pdev->dev;
433 indio_dev->dev.of_node = pdev->dev.of_node;
434 indio_dev->info = &stm32_adc_iio_info;
435 indio_dev->modes = INDIO_DIRECT_MODE;
436
437 platform_set_drvdata(pdev, adc);
438
439 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
440 if (ret != 0) {
441 dev_err(&pdev->dev, "missing reg property\n");
442 return -EINVAL;
443 }
444
445 adc->irq = platform_get_irq(pdev, 0);
446 if (adc->irq < 0) {
447 dev_err(&pdev->dev, "failed to get irq\n");
448 return adc->irq;
449 }
450
451 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
452 0, pdev->name, adc);
453 if (ret) {
454 dev_err(&pdev->dev, "failed to request IRQ\n");
455 return ret;
456 }
457
458 adc->clk = devm_clk_get(&pdev->dev, NULL);
459 if (IS_ERR(adc->clk)) {
460 dev_err(&pdev->dev, "Can't get clock\n");
461 return PTR_ERR(adc->clk);
462 }
463
464 ret = clk_prepare_enable(adc->clk);
465 if (ret < 0) {
466 dev_err(&pdev->dev, "clk enable failed\n");
467 return ret;
468 }
469
470 ret = stm32_adc_chan_of_init(indio_dev);
471 if (ret < 0)
472 goto err_clk_disable;
473
474 ret = iio_device_register(indio_dev);
475 if (ret) {
476 dev_err(&pdev->dev, "iio dev register failed\n");
477 goto err_clk_disable;
478 }
479
480 return 0;
481
482err_clk_disable:
483 clk_disable_unprepare(adc->clk);
484
485 return ret;
486}
487
488static int stm32_adc_remove(struct platform_device *pdev)
489{
490 struct stm32_adc *adc = platform_get_drvdata(pdev);
491 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
492
493 iio_device_unregister(indio_dev);
494 clk_disable_unprepare(adc->clk);
495
496 return 0;
497}
498
499static const struct of_device_id stm32_adc_of_match[] = {
500 { .compatible = "st,stm32f4-adc" },
501 {},
502};
503MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
504
505static struct platform_driver stm32_adc_driver = {
506 .probe = stm32_adc_probe,
507 .remove = stm32_adc_remove,
508 .driver = {
509 .name = "stm32-adc",
510 .of_match_table = stm32_adc_of_match,
511 },
512};
513module_platform_driver(stm32_adc_driver);
514
515MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
516MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
517MODULE_LICENSE("GPL v2");
518MODULE_ALIAS("platform:stm32-adc");