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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "radeon_asic.h"
27#include "sid.h"
28#include "r600_dpm.h"
29#include "si_dpm.h"
30#include "atom.h"
31#include <linux/math64.h>
32#include <linux/seq_file.h>
33
34#define MC_CG_ARB_FREQ_F0 0x0a
35#define MC_CG_ARB_FREQ_F1 0x0b
36#define MC_CG_ARB_FREQ_F2 0x0c
37#define MC_CG_ARB_FREQ_F3 0x0d
38
39#define SMC_RAM_END 0x20000
40
41#define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43static const struct si_cac_config_reg cac_weights_tahiti[] =
44{
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106};
107
108static const struct si_cac_config_reg lcac_tahiti[] =
109{
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198};
199
200static const struct si_cac_config_reg cac_override_tahiti[] =
201{
202 { 0xFFFFFFFF }
203};
204
205static const struct si_powertune_data powertune_data_tahiti =
206{
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234};
235
236static const struct si_dte_data dte_data_tahiti =
237{
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252};
253
254static const struct si_dte_data dte_data_tahiti_le =
255{
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270};
271
272static const struct si_dte_data dte_data_tahiti_pro =
273{
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288};
289
290static const struct si_dte_data dte_data_new_zealand =
291{
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306};
307
308static const struct si_dte_data dte_data_aruba_pro =
309{
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324};
325
326static const struct si_dte_data dte_data_malta =
327{
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342};
343
344struct si_cac_config_reg cac_weights_pitcairn[] =
345{
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407};
408
409static const struct si_cac_config_reg lcac_pitcairn[] =
410{
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg cac_override_pitcairn[] =
501{
502 { 0xFFFFFFFF }
503};
504
505static const struct si_powertune_data powertune_data_pitcairn =
506{
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534};
535
536static const struct si_dte_data dte_data_pitcairn =
537{
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552};
553
554static const struct si_dte_data dte_data_curacao_xt =
555{
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570};
571
572static const struct si_dte_data dte_data_curacao_pro =
573{
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588};
589
590static const struct si_dte_data dte_data_neptune_xt =
591{
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606};
607
608static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609{
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671};
672
673static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674{
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736};
737
738static const struct si_cac_config_reg cac_weights_heathrow[] =
739{
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801};
802
803static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804{
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866};
867
868static const struct si_cac_config_reg cac_weights_cape_verde[] =
869{
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931};
932
933static const struct si_cac_config_reg lcac_cape_verde[] =
934{
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990};
991
992static const struct si_cac_config_reg cac_override_cape_verde[] =
993{
994 { 0xFFFFFFFF }
995};
996
997static const struct si_powertune_data powertune_data_cape_verde =
998{
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026};
1027
1028static const struct si_dte_data dte_data_cape_verde =
1029{
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044};
1045
1046static const struct si_dte_data dte_data_venus_xtx =
1047{
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062};
1063
1064static const struct si_dte_data dte_data_venus_xt =
1065{
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080};
1081
1082static const struct si_dte_data dte_data_venus_pro =
1083{
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098};
1099
1100struct si_cac_config_reg cac_weights_oland[] =
1101{
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163};
1164
1165static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166{
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228};
1229
1230static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231{
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293};
1294
1295static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296{
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358};
1359
1360static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361{
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423};
1424
1425static const struct si_cac_config_reg lcac_oland[] =
1426{
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470};
1471
1472static const struct si_cac_config_reg lcac_mars_pro[] =
1473{
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517};
1518
1519static const struct si_cac_config_reg cac_override_oland[] =
1520{
1521 { 0xFFFFFFFF }
1522};
1523
1524static const struct si_powertune_data powertune_data_oland =
1525{
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553};
1554
1555static const struct si_powertune_data powertune_data_mars_pro =
1556{
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584};
1585
1586static const struct si_dte_data dte_data_oland =
1587{
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602};
1603
1604static const struct si_dte_data dte_data_mars_pro =
1605{
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620};
1621
1622static const struct si_dte_data dte_data_sun_xt =
1623{
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638};
1639
1640
1641static const struct si_cac_config_reg cac_weights_hainan[] =
1642{
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704};
1705
1706static const struct si_powertune_data powertune_data_hainan =
1707{
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735};
1736
1737struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742extern int si_mc_load_microcode(struct radeon_device *rdev);
1743extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 u16 *std_voltage);
1751static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 u32 engine_clock,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764{
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767 return pi;
1768}
1769
1770static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772{
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 s64 tmp;
1776
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1786
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1795}
1796
1797static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1799 u16 v,
1800 s32 t,
1801 u32 i_leakage,
1802 u32 *leakage)
1803{
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805}
1806
1807static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1810{
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1823}
1824
1825static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1827 const u32 fixed_kt,
1828 u16 v,
1829 u32 i_leakage,
1830 u32 *leakage)
1831{
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833}
1834
1835
1836static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1838{
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1845 u32 i;
1846
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1849
1850 for (i = 0; i < k; i++) {
1851 dte_data->r[i] =
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1854 }
1855
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1860 }
1861 } else {
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 }
1864}
1865
1866static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867{
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1871
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1878
1879 switch (rdev->pdev->device) {
1880 case 0x6798:
1881 si_pi->dte_data.enable_dte_by_default = true;
1882 break;
1883 case 0x6799:
1884 si_pi->dte_data = dte_data_new_zealand;
1885 break;
1886 case 0x6790:
1887 case 0x6791:
1888 case 0x6792:
1889 case 0x679E:
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679B:
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1896 break;
1897 case 0x679A:
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1900 break;
1901 default:
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1904 break;
1905 }
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1908 case 0x6810:
1909 case 0x6818:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6819:
1918 case 0x6811:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1925 break;
1926 case 0x6800:
1927 case 0x6806:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1934 break;
1935 default:
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1941 break;
1942 }
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948 switch (rdev->pdev->device) {
1949 case 0x683B:
1950 case 0x683F:
1951 case 0x6829:
1952 case 0x6835:
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682C:
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 break;
1960 case 0x6825:
1961 case 0x6827:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6824:
1966 case 0x682D:
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1969 break;
1970 case 0x682F:
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1973 break;
1974 case 0x6820:
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1977 break;
1978 case 0x6821:
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1981 break;
1982 case 0x6823:
1983 case 0x682B:
1984 case 0x6822:
1985 case 0x682A:
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1988 break;
1989 default:
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1992 break;
1993 }
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
1996 case 0x6601:
1997 case 0x6621:
1998 case 0x6603:
1999 case 0x6605:
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x6600:
2008 case 0x6606:
2009 case 0x6620:
2010 case 0x6604:
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x6611:
2019 case 0x6613:
2020 case 0x6608:
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6610:
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2035 break;
2036 default:
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2042 break;
2043 }
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2051 } else {
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 return;
2054 }
2055
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2060
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069 }
2070 ni_pi->enable_sq_ramping = true;
2071 }
2072
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2075
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2082 } else {
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2086 }
2087
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089}
2090
2091static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092{
2093 return 1;
2094}
2095
2096static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097{
2098 u32 xclk;
2099 u32 wintime;
2100 u32 cac_window;
2101 u32 cac_window_size;
2102
2103 xclk = radeon_get_xclk(rdev);
2104
2105 if (xclk == 0)
2106 return 0;
2107
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111 wintime = (cac_window_size * 100) / xclk;
2112
2113 return wintime;
2114}
2115
2116static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117{
2118 return power_in_watts;
2119}
2120
2121static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2123 u32 tdp_adjustment,
2124 u32 *tdp_limit,
2125 u32 *near_tdp_limit)
2126{
2127 u32 adjustment_delta, max_tdp_limit;
2128
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 return -EINVAL;
2131
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 } else {
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 else
2143 *near_tdp_limit = 0;
2144 }
2145
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 return -EINVAL;
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 return -EINVAL;
2150
2151 return 0;
2152}
2153
2154static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2156{
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 u32 tdp_limit;
2166 u32 near_tdp_limit;
2167 int ret;
2168
2169 if (scaling_factor == 0)
2170 return -EINVAL;
2171
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 false, /* ??? */
2176 rdev->pm.dpm.tdp_adjustment,
2177 &tdp_limit,
2178 &near_tdp_limit);
2179 if (ret)
2180 return ret;
2181
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 sizeof(u32) * 3,
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 (u8 *)papm_parm,
2210 sizeof(PP_SIslands_PAPMParameters),
2211 si_pi->sram_end);
2212 if (ret)
2213 return ret;
2214 }
2215 }
2216 return 0;
2217}
2218
2219static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2221{
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 int ret;
2229
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 sizeof(u32) * 2,
2243 si_pi->sram_end);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 return 0;
2249}
2250
2251static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2254{
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2259
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2261 return 0;
2262
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2266
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 return 0;
2269
2270 return (u16)pwr_efficiency_ratio;
2271}
2272
2273static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2275{
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2280 return true;
2281
2282 return false;
2283}
2284
2285static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2288{
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 u32 prev_sclk;
2294 u32 max_sclk;
2295 u32 min_sclk;
2296 u16 prev_std_vddc;
2297 u16 curr_std_vddc;
2298 int i;
2299 u16 pwr_efficiency_ratio;
2300 u8 max_ps_percent;
2301 bool disable_uvd_power_tune;
2302 int ret;
2303
2304 if (ni_pi->enable_power_containment == false)
2305 return 0;
2306
2307 if (state->performance_level_count == 0)
2308 return -EINVAL;
2309
2310 if (smc_state->levelCount != state->performance_level_count)
2311 return -EINVAL;
2312
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2324 if (i == 1)
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 else
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329 if (prev_sclk > max_sclk)
2330 return -EINVAL;
2331
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2338 } else {
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 }
2341
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2344
2345 if (min_sclk == 0)
2346 return -EINVAL;
2347
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2350 if (ret)
2351 return ret;
2352
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2359 if (ret)
2360 return ret;
2361
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 if (ret)
2364 return ret;
2365
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2368
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 }
2375
2376 return 0;
2377}
2378
2379static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2382{
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 int i;
2388
2389 if (state->performance_level_count == 0)
2390 return -EINVAL;
2391
2392 if (smc_state->levelCount != state->performance_level_count)
2393 return -EINVAL;
2394
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 return -EINVAL;
2397
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2403
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2406
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2409
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2412
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2416
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 } else {
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 }
2428
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 }
2432
2433 return 0;
2434}
2435
2436static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2438 bool enable)
2439{
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2442 int ret = 0;
2443
2444 if (ni_pi->enable_power_containment) {
2445 if (enable) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2449 ret = -EINVAL;
2450 ni_pi->pc_enabled = false;
2451 } else {
2452 ni_pi->pc_enabled = true;
2453 }
2454 }
2455 } else {
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2458 ret = -EINVAL;
2459 ni_pi->pc_enabled = false;
2460 }
2461 }
2462
2463 return ret;
2464}
2465
2466static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467{
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2469 int ret = 0;
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 u32 table_size;
2473 u8 tdep_count;
2474 u32 i;
2475
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2478
2479 if (si_pi->enable_dte == false)
2480 return 0;
2481
2482 if (dte_data->k <= 0)
2483 return -EINVAL;
2484
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2488 return -ENOMEM;
2489 }
2490
2491 table_size = dte_data->k;
2492
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508 if (tdep_count > 0)
2509 table_size--;
2510
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2514 }
2515
2516 dte_tables->Tdep_count = tdep_count;
2517
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 }
2523
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 kfree(dte_tables);
2527
2528 return ret;
2529}
2530
2531static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 u16 *max, u16 *min)
2533{
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 u32 i;
2538 u32 v0_loadline;
2539
2540
2541 if (table == NULL)
2542 return -EINVAL;
2543
2544 *max = 0;
2545 *min = 0xFFFF;
2546
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2552 }
2553
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 return -EINVAL;
2556
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559 if (v0_loadline > 0xFFFFUL)
2560 return -EINVAL;
2561
2562 *min = (u16)v0_loadline;
2563
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2565 return -EINVAL;
2566
2567 return 0;
2568}
2569
2570static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571{
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574}
2575
2576static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 u16 t0, u16 t_step)
2580{
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2582 u32 leakage;
2583 unsigned int i, j;
2584 s32 t;
2585 u32 smc_leakage;
2586 u32 scaling_factor;
2587 u16 voltage;
2588
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2593
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2596
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2599 voltage,
2600 t,
2601 si_pi->dyn_powertune_data.cac_leakage,
2602 &leakage);
2603
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2608
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2611 }
2612 }
2613 return 0;
2614}
2615
2616static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619{
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2621 u32 leakage;
2622 unsigned int i, j;
2623 u32 smc_leakage;
2624 u32 scaling_factor;
2625 u16 voltage;
2626
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2631
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2635 voltage,
2636 si_pi->dyn_powertune_data.cac_leakage,
2637 &leakage);
2638
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2643
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2647 }
2648 return 0;
2649}
2650
2651static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652{
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2657 u16 t0, t_step;
2658 u32 load_line_slope, reg;
2659 int ret = 0;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662 if (ni_pi->enable_cac == false)
2663 return 0;
2664
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 if (!cac_tables)
2667 return -ENOMEM;
2668
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2672
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 if (ret)
2683 goto done_free;
2684
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 t_step = 4;
2688 t0 = 60;
2689
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2693 t0, t_step);
2694 else
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2697 if (ret)
2698 goto done_free;
2699
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719 if (ret)
2720 goto done_free;
2721
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724done_free:
2725 if (ret) {
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2728 }
2729
2730 kfree(cac_tables);
2731
2732 return 0;
2733}
2734
2735static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2737{
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2740
2741 if (!config_regs)
2742 return -EINVAL;
2743
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2750 break;
2751 default:
2752 data = RREG32(config_regs->offset << 2);
2753 break;
2754 }
2755
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2764 break;
2765 default:
2766 WREG32(config_regs->offset << 2, data);
2767 break;
2768 }
2769 config_regs++;
2770 }
2771 return 0;
2772}
2773
2774static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775{
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2778 int ret;
2779
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2782 return 0;
2783
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 if (ret)
2786 return ret;
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 if (ret)
2789 return ret;
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 if (ret)
2792 return ret;
2793
2794 return 0;
2795}
2796
2797static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2799 bool enable)
2800{
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2804 int ret = 0;
2805
2806 if (ni_pi->enable_cac) {
2807 if (enable) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2813 }
2814
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2817 ret = -EINVAL;
2818 ni_pi->cac_enabled = false;
2819 } else {
2820 ni_pi->cac_enabled = true;
2821 }
2822
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2826 ret = -EINVAL;
2827 }
2828 }
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835 ni_pi->cac_enabled = false;
2836
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 }
2840 }
2841 return ret;
2842}
2843
2844static int si_init_smc_spll_table(struct radeon_device *rdev)
2845{
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 u32 fb_div, p_div;
2851 u32 clk_s, clk_v;
2852 u32 sclk = 0;
2853 int ret = 0;
2854 u32 tmp;
2855 int i;
2856
2857 if (si_pi->spll_table_start == 0)
2858 return -EINVAL;
2859
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2862 return -ENOMEM;
2863
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 if (ret)
2867 break;
2868
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874 fb_div &= ~0x00001FFF;
2875 fb_div >>= 1;
2876 clk_v >>= 6;
2877
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 ret = -EINVAL;
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 ret = -EINVAL;
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 ret = -EINVAL;
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 ret = -EINVAL;
2886
2887 if (ret)
2888 break;
2889
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898 sclk += 512;
2899 }
2900
2901
2902 if (!ret)
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 si_pi->sram_end);
2906
2907 if (ret)
2908 ni_pi->enable_power_containment = false;
2909
2910 kfree(spll_table);
2911
2912 return ret;
2913}
2914
2915struct si_dpm_quirk {
2916 u32 chip_vendor;
2917 u32 chip_device;
2918 u32 subsys_vendor;
2919 u32 subsys_device;
2920 u32 max_sclk;
2921 u32 max_mclk;
2922};
2923
2924/* cards with dpm stability problems */
2925static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2930 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2935 { 0, 0, 0, 0 },
2936};
2937
2938static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2939 u16 vce_voltage)
2940{
2941 u16 highest_leakage = 0;
2942 struct si_power_info *si_pi = si_get_pi(rdev);
2943 int i;
2944
2945 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2946 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2947 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2948 }
2949
2950 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2951 return highest_leakage;
2952
2953 return vce_voltage;
2954}
2955
2956static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2957 u32 evclk, u32 ecclk, u16 *voltage)
2958{
2959 u32 i;
2960 int ret = -EINVAL;
2961 struct radeon_vce_clock_voltage_dependency_table *table =
2962 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2963
2964 if (((evclk == 0) && (ecclk == 0)) ||
2965 (table && (table->count == 0))) {
2966 *voltage = 0;
2967 return 0;
2968 }
2969
2970 for (i = 0; i < table->count; i++) {
2971 if ((evclk <= table->entries[i].evclk) &&
2972 (ecclk <= table->entries[i].ecclk)) {
2973 *voltage = table->entries[i].v;
2974 ret = 0;
2975 break;
2976 }
2977 }
2978
2979 /* if no match return the highest voltage */
2980 if (ret)
2981 *voltage = table->entries[table->count - 1].v;
2982
2983 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2984
2985 return ret;
2986}
2987
2988static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2989 struct radeon_ps *rps)
2990{
2991 struct ni_ps *ps = ni_get_ps(rps);
2992 struct radeon_clock_and_voltage_limits *max_limits;
2993 bool disable_mclk_switching = false;
2994 bool disable_sclk_switching = false;
2995 u32 mclk, sclk;
2996 u16 vddc, vddci, min_vce_voltage = 0;
2997 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2998 u32 max_sclk = 0, max_mclk = 0;
2999 int i;
3000 struct si_dpm_quirk *p = si_dpm_quirk_list;
3001
3002 /* limit all SI kickers */
3003 if (rdev->family == CHIP_PITCAIRN) {
3004 if ((rdev->pdev->revision == 0x81) ||
3005 (rdev->pdev->device == 0x6810) ||
3006 (rdev->pdev->device == 0x6811) ||
3007 (rdev->pdev->device == 0x6816) ||
3008 (rdev->pdev->device == 0x6817) ||
3009 (rdev->pdev->device == 0x6806))
3010 max_mclk = 120000;
3011 } else if (rdev->family == CHIP_HAINAN) {
3012 if ((rdev->pdev->revision == 0x81) ||
3013 (rdev->pdev->revision == 0x83) ||
3014 (rdev->pdev->revision == 0xC3) ||
3015 (rdev->pdev->device == 0x6664) ||
3016 (rdev->pdev->device == 0x6665) ||
3017 (rdev->pdev->device == 0x6667)) {
3018 max_sclk = 75000;
3019 }
3020 }
3021 /* Apply dpm quirks */
3022 while (p && p->chip_device != 0) {
3023 if (rdev->pdev->vendor == p->chip_vendor &&
3024 rdev->pdev->device == p->chip_device &&
3025 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3026 rdev->pdev->subsystem_device == p->subsys_device) {
3027 max_sclk = p->max_sclk;
3028 max_mclk = p->max_mclk;
3029 break;
3030 }
3031 ++p;
3032 }
3033
3034 if (rps->vce_active) {
3035 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3036 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3037 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3038 &min_vce_voltage);
3039 } else {
3040 rps->evclk = 0;
3041 rps->ecclk = 0;
3042 }
3043
3044 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3045 ni_dpm_vblank_too_short(rdev))
3046 disable_mclk_switching = true;
3047
3048 if (rps->vclk || rps->dclk) {
3049 disable_mclk_switching = true;
3050 disable_sclk_switching = true;
3051 }
3052
3053 if (rdev->pm.dpm.ac_power)
3054 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3055 else
3056 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3057
3058 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3059 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3060 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3061 }
3062 if (rdev->pm.dpm.ac_power == false) {
3063 for (i = 0; i < ps->performance_level_count; i++) {
3064 if (ps->performance_levels[i].mclk > max_limits->mclk)
3065 ps->performance_levels[i].mclk = max_limits->mclk;
3066 if (ps->performance_levels[i].sclk > max_limits->sclk)
3067 ps->performance_levels[i].sclk = max_limits->sclk;
3068 if (ps->performance_levels[i].vddc > max_limits->vddc)
3069 ps->performance_levels[i].vddc = max_limits->vddc;
3070 if (ps->performance_levels[i].vddci > max_limits->vddci)
3071 ps->performance_levels[i].vddci = max_limits->vddci;
3072 }
3073 }
3074
3075 /* limit clocks to max supported clocks based on voltage dependency tables */
3076 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3077 &max_sclk_vddc);
3078 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3079 &max_mclk_vddci);
3080 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3081 &max_mclk_vddc);
3082
3083 for (i = 0; i < ps->performance_level_count; i++) {
3084 if (max_sclk_vddc) {
3085 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3086 ps->performance_levels[i].sclk = max_sclk_vddc;
3087 }
3088 if (max_mclk_vddci) {
3089 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3090 ps->performance_levels[i].mclk = max_mclk_vddci;
3091 }
3092 if (max_mclk_vddc) {
3093 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3094 ps->performance_levels[i].mclk = max_mclk_vddc;
3095 }
3096 if (max_mclk) {
3097 if (ps->performance_levels[i].mclk > max_mclk)
3098 ps->performance_levels[i].mclk = max_mclk;
3099 }
3100 if (max_sclk) {
3101 if (ps->performance_levels[i].sclk > max_sclk)
3102 ps->performance_levels[i].sclk = max_sclk;
3103 }
3104 }
3105
3106 /* XXX validate the min clocks required for display */
3107
3108 if (disable_mclk_switching) {
3109 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3110 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3111 } else {
3112 mclk = ps->performance_levels[0].mclk;
3113 vddci = ps->performance_levels[0].vddci;
3114 }
3115
3116 if (disable_sclk_switching) {
3117 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3118 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3119 } else {
3120 sclk = ps->performance_levels[0].sclk;
3121 vddc = ps->performance_levels[0].vddc;
3122 }
3123
3124 if (rps->vce_active) {
3125 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3126 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3127 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3128 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3129 }
3130
3131 /* adjusted low state */
3132 ps->performance_levels[0].sclk = sclk;
3133 ps->performance_levels[0].mclk = mclk;
3134 ps->performance_levels[0].vddc = vddc;
3135 ps->performance_levels[0].vddci = vddci;
3136
3137 if (disable_sclk_switching) {
3138 sclk = ps->performance_levels[0].sclk;
3139 for (i = 1; i < ps->performance_level_count; i++) {
3140 if (sclk < ps->performance_levels[i].sclk)
3141 sclk = ps->performance_levels[i].sclk;
3142 }
3143 for (i = 0; i < ps->performance_level_count; i++) {
3144 ps->performance_levels[i].sclk = sclk;
3145 ps->performance_levels[i].vddc = vddc;
3146 }
3147 } else {
3148 for (i = 1; i < ps->performance_level_count; i++) {
3149 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3150 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3151 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3152 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3153 }
3154 }
3155
3156 if (disable_mclk_switching) {
3157 mclk = ps->performance_levels[0].mclk;
3158 for (i = 1; i < ps->performance_level_count; i++) {
3159 if (mclk < ps->performance_levels[i].mclk)
3160 mclk = ps->performance_levels[i].mclk;
3161 }
3162 for (i = 0; i < ps->performance_level_count; i++) {
3163 ps->performance_levels[i].mclk = mclk;
3164 ps->performance_levels[i].vddci = vddci;
3165 }
3166 } else {
3167 for (i = 1; i < ps->performance_level_count; i++) {
3168 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3169 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3170 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3171 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3172 }
3173 }
3174
3175 for (i = 0; i < ps->performance_level_count; i++)
3176 btc_adjust_clock_combinations(rdev, max_limits,
3177 &ps->performance_levels[i]);
3178
3179 for (i = 0; i < ps->performance_level_count; i++) {
3180 if (ps->performance_levels[i].vddc < min_vce_voltage)
3181 ps->performance_levels[i].vddc = min_vce_voltage;
3182 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3183 ps->performance_levels[i].sclk,
3184 max_limits->vddc, &ps->performance_levels[i].vddc);
3185 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3186 ps->performance_levels[i].mclk,
3187 max_limits->vddci, &ps->performance_levels[i].vddci);
3188 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3189 ps->performance_levels[i].mclk,
3190 max_limits->vddc, &ps->performance_levels[i].vddc);
3191 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3192 rdev->clock.current_dispclk,
3193 max_limits->vddc, &ps->performance_levels[i].vddc);
3194 }
3195
3196 for (i = 0; i < ps->performance_level_count; i++) {
3197 btc_apply_voltage_delta_rules(rdev,
3198 max_limits->vddc, max_limits->vddci,
3199 &ps->performance_levels[i].vddc,
3200 &ps->performance_levels[i].vddci);
3201 }
3202
3203 ps->dc_compatible = true;
3204 for (i = 0; i < ps->performance_level_count; i++) {
3205 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3206 ps->dc_compatible = false;
3207 }
3208}
3209
3210#if 0
3211static int si_read_smc_soft_register(struct radeon_device *rdev,
3212 u16 reg_offset, u32 *value)
3213{
3214 struct si_power_info *si_pi = si_get_pi(rdev);
3215
3216 return si_read_smc_sram_dword(rdev,
3217 si_pi->soft_regs_start + reg_offset, value,
3218 si_pi->sram_end);
3219}
3220#endif
3221
3222static int si_write_smc_soft_register(struct radeon_device *rdev,
3223 u16 reg_offset, u32 value)
3224{
3225 struct si_power_info *si_pi = si_get_pi(rdev);
3226
3227 return si_write_smc_sram_dword(rdev,
3228 si_pi->soft_regs_start + reg_offset,
3229 value, si_pi->sram_end);
3230}
3231
3232static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3233{
3234 bool ret = false;
3235 u32 tmp, width, row, column, bank, density;
3236 bool is_memory_gddr5, is_special;
3237
3238 tmp = RREG32(MC_SEQ_MISC0);
3239 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3240 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3241 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3242
3243 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3244 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3245
3246 tmp = RREG32(MC_ARB_RAMCFG);
3247 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3248 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3249 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3250
3251 density = (1 << (row + column - 20 + bank)) * width;
3252
3253 if ((rdev->pdev->device == 0x6819) &&
3254 is_memory_gddr5 && is_special && (density == 0x400))
3255 ret = true;
3256
3257 return ret;
3258}
3259
3260static void si_get_leakage_vddc(struct radeon_device *rdev)
3261{
3262 struct si_power_info *si_pi = si_get_pi(rdev);
3263 u16 vddc, count = 0;
3264 int i, ret;
3265
3266 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3267 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3268
3269 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3270 si_pi->leakage_voltage.entries[count].voltage = vddc;
3271 si_pi->leakage_voltage.entries[count].leakage_index =
3272 SISLANDS_LEAKAGE_INDEX0 + i;
3273 count++;
3274 }
3275 }
3276 si_pi->leakage_voltage.count = count;
3277}
3278
3279static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3280 u32 index, u16 *leakage_voltage)
3281{
3282 struct si_power_info *si_pi = si_get_pi(rdev);
3283 int i;
3284
3285 if (leakage_voltage == NULL)
3286 return -EINVAL;
3287
3288 if ((index & 0xff00) != 0xff00)
3289 return -EINVAL;
3290
3291 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3292 return -EINVAL;
3293
3294 if (index < SISLANDS_LEAKAGE_INDEX0)
3295 return -EINVAL;
3296
3297 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3298 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3299 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3300 return 0;
3301 }
3302 }
3303 return -EAGAIN;
3304}
3305
3306static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3307{
3308 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3309 bool want_thermal_protection;
3310 enum radeon_dpm_event_src dpm_event_src;
3311
3312 switch (sources) {
3313 case 0:
3314 default:
3315 want_thermal_protection = false;
3316 break;
3317 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3318 want_thermal_protection = true;
3319 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3320 break;
3321 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3322 want_thermal_protection = true;
3323 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3324 break;
3325 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3326 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3327 want_thermal_protection = true;
3328 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3329 break;
3330 }
3331
3332 if (want_thermal_protection) {
3333 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3334 if (pi->thermal_protection)
3335 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3336 } else {
3337 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3338 }
3339}
3340
3341static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3342 enum radeon_dpm_auto_throttle_src source,
3343 bool enable)
3344{
3345 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3346
3347 if (enable) {
3348 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3349 pi->active_auto_throttle_sources |= 1 << source;
3350 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3351 }
3352 } else {
3353 if (pi->active_auto_throttle_sources & (1 << source)) {
3354 pi->active_auto_throttle_sources &= ~(1 << source);
3355 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3356 }
3357 }
3358}
3359
3360static void si_start_dpm(struct radeon_device *rdev)
3361{
3362 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3363}
3364
3365static void si_stop_dpm(struct radeon_device *rdev)
3366{
3367 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3368}
3369
3370static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3371{
3372 if (enable)
3373 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3374 else
3375 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3376
3377}
3378
3379#if 0
3380static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3381 u32 thermal_level)
3382{
3383 PPSMC_Result ret;
3384
3385 if (thermal_level == 0) {
3386 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3387 if (ret == PPSMC_Result_OK)
3388 return 0;
3389 else
3390 return -EINVAL;
3391 }
3392 return 0;
3393}
3394
3395static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3396{
3397 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3398}
3399#endif
3400
3401#if 0
3402static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3403{
3404 if (ac_power)
3405 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3406 0 : -EINVAL;
3407
3408 return 0;
3409}
3410#endif
3411
3412static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3413 PPSMC_Msg msg, u32 parameter)
3414{
3415 WREG32(SMC_SCRATCH0, parameter);
3416 return si_send_msg_to_smc(rdev, msg);
3417}
3418
3419static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3420{
3421 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3422 return -EINVAL;
3423
3424 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3425 0 : -EINVAL;
3426}
3427
3428int si_dpm_force_performance_level(struct radeon_device *rdev,
3429 enum radeon_dpm_forced_level level)
3430{
3431 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3432 struct ni_ps *ps = ni_get_ps(rps);
3433 u32 levels = ps->performance_level_count;
3434
3435 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3436 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3437 return -EINVAL;
3438
3439 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3440 return -EINVAL;
3441 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3442 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3443 return -EINVAL;
3444
3445 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3446 return -EINVAL;
3447 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3448 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3449 return -EINVAL;
3450
3451 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3452 return -EINVAL;
3453 }
3454
3455 rdev->pm.dpm.forced_level = level;
3456
3457 return 0;
3458}
3459
3460#if 0
3461static int si_set_boot_state(struct radeon_device *rdev)
3462{
3463 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3464 0 : -EINVAL;
3465}
3466#endif
3467
3468static int si_set_sw_state(struct radeon_device *rdev)
3469{
3470 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3471 0 : -EINVAL;
3472}
3473
3474static int si_halt_smc(struct radeon_device *rdev)
3475{
3476 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3477 return -EINVAL;
3478
3479 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3480 0 : -EINVAL;
3481}
3482
3483static int si_resume_smc(struct radeon_device *rdev)
3484{
3485 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3486 return -EINVAL;
3487
3488 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3489 0 : -EINVAL;
3490}
3491
3492static void si_dpm_start_smc(struct radeon_device *rdev)
3493{
3494 si_program_jump_on_start(rdev);
3495 si_start_smc(rdev);
3496 si_start_smc_clock(rdev);
3497}
3498
3499static void si_dpm_stop_smc(struct radeon_device *rdev)
3500{
3501 si_reset_smc(rdev);
3502 si_stop_smc_clock(rdev);
3503}
3504
3505static int si_process_firmware_header(struct radeon_device *rdev)
3506{
3507 struct si_power_info *si_pi = si_get_pi(rdev);
3508 u32 tmp;
3509 int ret;
3510
3511 ret = si_read_smc_sram_dword(rdev,
3512 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3513 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3514 &tmp, si_pi->sram_end);
3515 if (ret)
3516 return ret;
3517
3518 si_pi->state_table_start = tmp;
3519
3520 ret = si_read_smc_sram_dword(rdev,
3521 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3522 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3523 &tmp, si_pi->sram_end);
3524 if (ret)
3525 return ret;
3526
3527 si_pi->soft_regs_start = tmp;
3528
3529 ret = si_read_smc_sram_dword(rdev,
3530 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3531 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3532 &tmp, si_pi->sram_end);
3533 if (ret)
3534 return ret;
3535
3536 si_pi->mc_reg_table_start = tmp;
3537
3538 ret = si_read_smc_sram_dword(rdev,
3539 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3540 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3541 &tmp, si_pi->sram_end);
3542 if (ret)
3543 return ret;
3544
3545 si_pi->fan_table_start = tmp;
3546
3547 ret = si_read_smc_sram_dword(rdev,
3548 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3549 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3550 &tmp, si_pi->sram_end);
3551 if (ret)
3552 return ret;
3553
3554 si_pi->arb_table_start = tmp;
3555
3556 ret = si_read_smc_sram_dword(rdev,
3557 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3558 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3559 &tmp, si_pi->sram_end);
3560 if (ret)
3561 return ret;
3562
3563 si_pi->cac_table_start = tmp;
3564
3565 ret = si_read_smc_sram_dword(rdev,
3566 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3567 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3568 &tmp, si_pi->sram_end);
3569 if (ret)
3570 return ret;
3571
3572 si_pi->dte_table_start = tmp;
3573
3574 ret = si_read_smc_sram_dword(rdev,
3575 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3576 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3577 &tmp, si_pi->sram_end);
3578 if (ret)
3579 return ret;
3580
3581 si_pi->spll_table_start = tmp;
3582
3583 ret = si_read_smc_sram_dword(rdev,
3584 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3585 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3586 &tmp, si_pi->sram_end);
3587 if (ret)
3588 return ret;
3589
3590 si_pi->papm_cfg_table_start = tmp;
3591
3592 return ret;
3593}
3594
3595static void si_read_clock_registers(struct radeon_device *rdev)
3596{
3597 struct si_power_info *si_pi = si_get_pi(rdev);
3598
3599 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3600 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3601 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3602 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3603 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3604 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3605 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3606 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3607 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3608 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3609 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3610 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3611 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3612 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3613 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3614}
3615
3616static void si_enable_thermal_protection(struct radeon_device *rdev,
3617 bool enable)
3618{
3619 if (enable)
3620 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3621 else
3622 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3623}
3624
3625static void si_enable_acpi_power_management(struct radeon_device *rdev)
3626{
3627 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3628}
3629
3630#if 0
3631static int si_enter_ulp_state(struct radeon_device *rdev)
3632{
3633 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3634
3635 udelay(25000);
3636
3637 return 0;
3638}
3639
3640static int si_exit_ulp_state(struct radeon_device *rdev)
3641{
3642 int i;
3643
3644 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3645
3646 udelay(7000);
3647
3648 for (i = 0; i < rdev->usec_timeout; i++) {
3649 if (RREG32(SMC_RESP_0) == 1)
3650 break;
3651 udelay(1000);
3652 }
3653
3654 return 0;
3655}
3656#endif
3657
3658static int si_notify_smc_display_change(struct radeon_device *rdev,
3659 bool has_display)
3660{
3661 PPSMC_Msg msg = has_display ?
3662 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3663
3664 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3665 0 : -EINVAL;
3666}
3667
3668static void si_program_response_times(struct radeon_device *rdev)
3669{
3670 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3671 u32 vddc_dly, acpi_dly, vbi_dly;
3672 u32 reference_clock;
3673
3674 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3675
3676 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3677 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3678
3679 if (voltage_response_time == 0)
3680 voltage_response_time = 1000;
3681
3682 acpi_delay_time = 15000;
3683 vbi_time_out = 100000;
3684
3685 reference_clock = radeon_get_xclk(rdev);
3686
3687 vddc_dly = (voltage_response_time * reference_clock) / 100;
3688 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3689 vbi_dly = (vbi_time_out * reference_clock) / 100;
3690
3691 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3692 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3693 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3694 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3695}
3696
3697static void si_program_ds_registers(struct radeon_device *rdev)
3698{
3699 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3700 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3701
3702 if (eg_pi->sclk_deep_sleep) {
3703 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3704 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3705 ~AUTOSCALE_ON_SS_CLEAR);
3706 }
3707}
3708
3709static void si_program_display_gap(struct radeon_device *rdev)
3710{
3711 u32 tmp, pipe;
3712 int i;
3713
3714 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3715 if (rdev->pm.dpm.new_active_crtc_count > 0)
3716 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3717 else
3718 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3719
3720 if (rdev->pm.dpm.new_active_crtc_count > 1)
3721 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3722 else
3723 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3724
3725 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3726
3727 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3728 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3729
3730 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3731 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3732 /* find the first active crtc */
3733 for (i = 0; i < rdev->num_crtc; i++) {
3734 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3735 break;
3736 }
3737 if (i == rdev->num_crtc)
3738 pipe = 0;
3739 else
3740 pipe = i;
3741
3742 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3743 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3744 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3745 }
3746
3747 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3748 * This can be a problem on PowerXpress systems or if you want to use the card
3749 * for offscreen rendering or compute if there are no crtcs enabled.
3750 */
3751 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3752}
3753
3754static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3755{
3756 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3757
3758 if (enable) {
3759 if (pi->sclk_ss)
3760 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3761 } else {
3762 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3763 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3764 }
3765}
3766
3767static void si_setup_bsp(struct radeon_device *rdev)
3768{
3769 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3770 u32 xclk = radeon_get_xclk(rdev);
3771
3772 r600_calculate_u_and_p(pi->asi,
3773 xclk,
3774 16,
3775 &pi->bsp,
3776 &pi->bsu);
3777
3778 r600_calculate_u_and_p(pi->pasi,
3779 xclk,
3780 16,
3781 &pi->pbsp,
3782 &pi->pbsu);
3783
3784
3785 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3786 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3787
3788 WREG32(CG_BSP, pi->dsp);
3789}
3790
3791static void si_program_git(struct radeon_device *rdev)
3792{
3793 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3794}
3795
3796static void si_program_tp(struct radeon_device *rdev)
3797{
3798 int i;
3799 enum r600_td td = R600_TD_DFLT;
3800
3801 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3802 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3803
3804 if (td == R600_TD_AUTO)
3805 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3806 else
3807 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3808
3809 if (td == R600_TD_UP)
3810 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3811
3812 if (td == R600_TD_DOWN)
3813 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3814}
3815
3816static void si_program_tpp(struct radeon_device *rdev)
3817{
3818 WREG32(CG_TPC, R600_TPC_DFLT);
3819}
3820
3821static void si_program_sstp(struct radeon_device *rdev)
3822{
3823 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3824}
3825
3826static void si_enable_display_gap(struct radeon_device *rdev)
3827{
3828 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3829
3830 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3831 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3832 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3833
3834 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3835 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3836 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3837 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3838}
3839
3840static void si_program_vc(struct radeon_device *rdev)
3841{
3842 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3843
3844 WREG32(CG_FTV, pi->vrc);
3845}
3846
3847static void si_clear_vc(struct radeon_device *rdev)
3848{
3849 WREG32(CG_FTV, 0);
3850}
3851
3852u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3853{
3854 u8 mc_para_index;
3855
3856 if (memory_clock < 10000)
3857 mc_para_index = 0;
3858 else if (memory_clock >= 80000)
3859 mc_para_index = 0x0f;
3860 else
3861 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3862 return mc_para_index;
3863}
3864
3865u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3866{
3867 u8 mc_para_index;
3868
3869 if (strobe_mode) {
3870 if (memory_clock < 12500)
3871 mc_para_index = 0x00;
3872 else if (memory_clock > 47500)
3873 mc_para_index = 0x0f;
3874 else
3875 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3876 } else {
3877 if (memory_clock < 65000)
3878 mc_para_index = 0x00;
3879 else if (memory_clock > 135000)
3880 mc_para_index = 0x0f;
3881 else
3882 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3883 }
3884 return mc_para_index;
3885}
3886
3887static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3888{
3889 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3890 bool strobe_mode = false;
3891 u8 result = 0;
3892
3893 if (mclk <= pi->mclk_strobe_mode_threshold)
3894 strobe_mode = true;
3895
3896 if (pi->mem_gddr5)
3897 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3898 else
3899 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3900
3901 if (strobe_mode)
3902 result |= SISLANDS_SMC_STROBE_ENABLE;
3903
3904 return result;
3905}
3906
3907static int si_upload_firmware(struct radeon_device *rdev)
3908{
3909 struct si_power_info *si_pi = si_get_pi(rdev);
3910 int ret;
3911
3912 si_reset_smc(rdev);
3913 si_stop_smc_clock(rdev);
3914
3915 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3916
3917 return ret;
3918}
3919
3920static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3921 const struct atom_voltage_table *table,
3922 const struct radeon_phase_shedding_limits_table *limits)
3923{
3924 u32 data, num_bits, num_levels;
3925
3926 if ((table == NULL) || (limits == NULL))
3927 return false;
3928
3929 data = table->mask_low;
3930
3931 num_bits = hweight32(data);
3932
3933 if (num_bits == 0)
3934 return false;
3935
3936 num_levels = (1 << num_bits);
3937
3938 if (table->count != num_levels)
3939 return false;
3940
3941 if (limits->count != (num_levels - 1))
3942 return false;
3943
3944 return true;
3945}
3946
3947void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3948 u32 max_voltage_steps,
3949 struct atom_voltage_table *voltage_table)
3950{
3951 unsigned int i, diff;
3952
3953 if (voltage_table->count <= max_voltage_steps)
3954 return;
3955
3956 diff = voltage_table->count - max_voltage_steps;
3957
3958 for (i= 0; i < max_voltage_steps; i++)
3959 voltage_table->entries[i] = voltage_table->entries[i + diff];
3960
3961 voltage_table->count = max_voltage_steps;
3962}
3963
3964static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3965 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3966 struct atom_voltage_table *voltage_table)
3967{
3968 u32 i;
3969
3970 if (voltage_dependency_table == NULL)
3971 return -EINVAL;
3972
3973 voltage_table->mask_low = 0;
3974 voltage_table->phase_delay = 0;
3975
3976 voltage_table->count = voltage_dependency_table->count;
3977 for (i = 0; i < voltage_table->count; i++) {
3978 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3979 voltage_table->entries[i].smio_low = 0;
3980 }
3981
3982 return 0;
3983}
3984
3985static int si_construct_voltage_tables(struct radeon_device *rdev)
3986{
3987 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3988 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3989 struct si_power_info *si_pi = si_get_pi(rdev);
3990 int ret;
3991
3992 if (pi->voltage_control) {
3993 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3994 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3995 if (ret)
3996 return ret;
3997
3998 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3999 si_trim_voltage_table_to_fit_state_table(rdev,
4000 SISLANDS_MAX_NO_VREG_STEPS,
4001 &eg_pi->vddc_voltage_table);
4002 } else if (si_pi->voltage_control_svi2) {
4003 ret = si_get_svi2_voltage_table(rdev,
4004 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4005 &eg_pi->vddc_voltage_table);
4006 if (ret)
4007 return ret;
4008 } else {
4009 return -EINVAL;
4010 }
4011
4012 if (eg_pi->vddci_control) {
4013 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4014 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4015 if (ret)
4016 return ret;
4017
4018 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4019 si_trim_voltage_table_to_fit_state_table(rdev,
4020 SISLANDS_MAX_NO_VREG_STEPS,
4021 &eg_pi->vddci_voltage_table);
4022 }
4023 if (si_pi->vddci_control_svi2) {
4024 ret = si_get_svi2_voltage_table(rdev,
4025 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4026 &eg_pi->vddci_voltage_table);
4027 if (ret)
4028 return ret;
4029 }
4030
4031 if (pi->mvdd_control) {
4032 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4033 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4034
4035 if (ret) {
4036 pi->mvdd_control = false;
4037 return ret;
4038 }
4039
4040 if (si_pi->mvdd_voltage_table.count == 0) {
4041 pi->mvdd_control = false;
4042 return -EINVAL;
4043 }
4044
4045 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4046 si_trim_voltage_table_to_fit_state_table(rdev,
4047 SISLANDS_MAX_NO_VREG_STEPS,
4048 &si_pi->mvdd_voltage_table);
4049 }
4050
4051 if (si_pi->vddc_phase_shed_control) {
4052 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4053 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4054 if (ret)
4055 si_pi->vddc_phase_shed_control = false;
4056
4057 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4058 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4059 si_pi->vddc_phase_shed_control = false;
4060 }
4061
4062 return 0;
4063}
4064
4065static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4066 const struct atom_voltage_table *voltage_table,
4067 SISLANDS_SMC_STATETABLE *table)
4068{
4069 unsigned int i;
4070
4071 for (i = 0; i < voltage_table->count; i++)
4072 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4073}
4074
4075static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4076 SISLANDS_SMC_STATETABLE *table)
4077{
4078 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4079 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4080 struct si_power_info *si_pi = si_get_pi(rdev);
4081 u8 i;
4082
4083 if (si_pi->voltage_control_svi2) {
4084 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4085 si_pi->svc_gpio_id);
4086 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4087 si_pi->svd_gpio_id);
4088 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4089 2);
4090 } else {
4091 if (eg_pi->vddc_voltage_table.count) {
4092 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4093 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4094 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4095
4096 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4097 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4098 table->maxVDDCIndexInPPTable = i;
4099 break;
4100 }
4101 }
4102 }
4103
4104 if (eg_pi->vddci_voltage_table.count) {
4105 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4106
4107 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4108 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4109 }
4110
4111
4112 if (si_pi->mvdd_voltage_table.count) {
4113 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4114
4115 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4116 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4117 }
4118
4119 if (si_pi->vddc_phase_shed_control) {
4120 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4121 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4122 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4123
4124 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4125 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4126
4127 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4128 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4129 } else {
4130 si_pi->vddc_phase_shed_control = false;
4131 }
4132 }
4133 }
4134
4135 return 0;
4136}
4137
4138static int si_populate_voltage_value(struct radeon_device *rdev,
4139 const struct atom_voltage_table *table,
4140 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4141{
4142 unsigned int i;
4143
4144 for (i = 0; i < table->count; i++) {
4145 if (value <= table->entries[i].value) {
4146 voltage->index = (u8)i;
4147 voltage->value = cpu_to_be16(table->entries[i].value);
4148 break;
4149 }
4150 }
4151
4152 if (i >= table->count)
4153 return -EINVAL;
4154
4155 return 0;
4156}
4157
4158static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4159 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4160{
4161 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4162 struct si_power_info *si_pi = si_get_pi(rdev);
4163
4164 if (pi->mvdd_control) {
4165 if (mclk <= pi->mvdd_split_frequency)
4166 voltage->index = 0;
4167 else
4168 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4169
4170 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4171 }
4172 return 0;
4173}
4174
4175static int si_get_std_voltage_value(struct radeon_device *rdev,
4176 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4177 u16 *std_voltage)
4178{
4179 u16 v_index;
4180 bool voltage_found = false;
4181 *std_voltage = be16_to_cpu(voltage->value);
4182
4183 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4184 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4185 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4186 return -EINVAL;
4187
4188 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4189 if (be16_to_cpu(voltage->value) ==
4190 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4191 voltage_found = true;
4192 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4193 *std_voltage =
4194 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4195 else
4196 *std_voltage =
4197 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4198 break;
4199 }
4200 }
4201
4202 if (!voltage_found) {
4203 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4204 if (be16_to_cpu(voltage->value) <=
4205 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4206 voltage_found = true;
4207 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4208 *std_voltage =
4209 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4210 else
4211 *std_voltage =
4212 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4213 break;
4214 }
4215 }
4216 }
4217 } else {
4218 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4219 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4220 }
4221 }
4222
4223 return 0;
4224}
4225
4226static int si_populate_std_voltage_value(struct radeon_device *rdev,
4227 u16 value, u8 index,
4228 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4229{
4230 voltage->index = index;
4231 voltage->value = cpu_to_be16(value);
4232
4233 return 0;
4234}
4235
4236static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4237 const struct radeon_phase_shedding_limits_table *limits,
4238 u16 voltage, u32 sclk, u32 mclk,
4239 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4240{
4241 unsigned int i;
4242
4243 for (i = 0; i < limits->count; i++) {
4244 if ((voltage <= limits->entries[i].voltage) &&
4245 (sclk <= limits->entries[i].sclk) &&
4246 (mclk <= limits->entries[i].mclk))
4247 break;
4248 }
4249
4250 smc_voltage->phase_settings = (u8)i;
4251
4252 return 0;
4253}
4254
4255static int si_init_arb_table_index(struct radeon_device *rdev)
4256{
4257 struct si_power_info *si_pi = si_get_pi(rdev);
4258 u32 tmp;
4259 int ret;
4260
4261 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4262 if (ret)
4263 return ret;
4264
4265 tmp &= 0x00FFFFFF;
4266 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4267
4268 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4269}
4270
4271static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4272{
4273 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4274}
4275
4276static int si_reset_to_default(struct radeon_device *rdev)
4277{
4278 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4279 0 : -EINVAL;
4280}
4281
4282static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4283{
4284 struct si_power_info *si_pi = si_get_pi(rdev);
4285 u32 tmp;
4286 int ret;
4287
4288 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4289 &tmp, si_pi->sram_end);
4290 if (ret)
4291 return ret;
4292
4293 tmp = (tmp >> 24) & 0xff;
4294
4295 if (tmp == MC_CG_ARB_FREQ_F0)
4296 return 0;
4297
4298 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4299}
4300
4301static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4302 u32 engine_clock)
4303{
4304 u32 dram_rows;
4305 u32 dram_refresh_rate;
4306 u32 mc_arb_rfsh_rate;
4307 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4308
4309 if (tmp >= 4)
4310 dram_rows = 16384;
4311 else
4312 dram_rows = 1 << (tmp + 10);
4313
4314 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4315 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4316
4317 return mc_arb_rfsh_rate;
4318}
4319
4320static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4321 struct rv7xx_pl *pl,
4322 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4323{
4324 u32 dram_timing;
4325 u32 dram_timing2;
4326 u32 burst_time;
4327
4328 arb_regs->mc_arb_rfsh_rate =
4329 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4330
4331 radeon_atom_set_engine_dram_timings(rdev,
4332 pl->sclk,
4333 pl->mclk);
4334
4335 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4336 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4337 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4338
4339 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4340 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4341 arb_regs->mc_arb_burst_time = (u8)burst_time;
4342
4343 return 0;
4344}
4345
4346static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4347 struct radeon_ps *radeon_state,
4348 unsigned int first_arb_set)
4349{
4350 struct si_power_info *si_pi = si_get_pi(rdev);
4351 struct ni_ps *state = ni_get_ps(radeon_state);
4352 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4353 int i, ret = 0;
4354
4355 for (i = 0; i < state->performance_level_count; i++) {
4356 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4357 if (ret)
4358 break;
4359 ret = si_copy_bytes_to_smc(rdev,
4360 si_pi->arb_table_start +
4361 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4362 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4363 (u8 *)&arb_regs,
4364 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4365 si_pi->sram_end);
4366 if (ret)
4367 break;
4368 }
4369
4370 return ret;
4371}
4372
4373static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4374 struct radeon_ps *radeon_new_state)
4375{
4376 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4377 SISLANDS_DRIVER_STATE_ARB_INDEX);
4378}
4379
4380static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4381 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4382{
4383 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4384 struct si_power_info *si_pi = si_get_pi(rdev);
4385
4386 if (pi->mvdd_control)
4387 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4388 si_pi->mvdd_bootup_value, voltage);
4389
4390 return 0;
4391}
4392
4393static int si_populate_smc_initial_state(struct radeon_device *rdev,
4394 struct radeon_ps *radeon_initial_state,
4395 SISLANDS_SMC_STATETABLE *table)
4396{
4397 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4398 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4399 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4400 struct si_power_info *si_pi = si_get_pi(rdev);
4401 u32 reg;
4402 int ret;
4403
4404 table->initialState.levels[0].mclk.vDLL_CNTL =
4405 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4406 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4407 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4408 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4409 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4410 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4411 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4412 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4413 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4414 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4415 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4416 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4417 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4418 table->initialState.levels[0].mclk.vMPLL_SS =
4419 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4420 table->initialState.levels[0].mclk.vMPLL_SS2 =
4421 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4422
4423 table->initialState.levels[0].mclk.mclk_value =
4424 cpu_to_be32(initial_state->performance_levels[0].mclk);
4425
4426 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4427 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4428 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4429 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4430 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4431 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4432 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4433 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4434 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4435 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4436 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4437 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4438
4439 table->initialState.levels[0].sclk.sclk_value =
4440 cpu_to_be32(initial_state->performance_levels[0].sclk);
4441
4442 table->initialState.levels[0].arbRefreshState =
4443 SISLANDS_INITIAL_STATE_ARB_INDEX;
4444
4445 table->initialState.levels[0].ACIndex = 0;
4446
4447 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4448 initial_state->performance_levels[0].vddc,
4449 &table->initialState.levels[0].vddc);
4450
4451 if (!ret) {
4452 u16 std_vddc;
4453
4454 ret = si_get_std_voltage_value(rdev,
4455 &table->initialState.levels[0].vddc,
4456 &std_vddc);
4457 if (!ret)
4458 si_populate_std_voltage_value(rdev, std_vddc,
4459 table->initialState.levels[0].vddc.index,
4460 &table->initialState.levels[0].std_vddc);
4461 }
4462
4463 if (eg_pi->vddci_control)
4464 si_populate_voltage_value(rdev,
4465 &eg_pi->vddci_voltage_table,
4466 initial_state->performance_levels[0].vddci,
4467 &table->initialState.levels[0].vddci);
4468
4469 if (si_pi->vddc_phase_shed_control)
4470 si_populate_phase_shedding_value(rdev,
4471 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4472 initial_state->performance_levels[0].vddc,
4473 initial_state->performance_levels[0].sclk,
4474 initial_state->performance_levels[0].mclk,
4475 &table->initialState.levels[0].vddc);
4476
4477 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4478
4479 reg = CG_R(0xffff) | CG_L(0);
4480 table->initialState.levels[0].aT = cpu_to_be32(reg);
4481
4482 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4483
4484 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4485
4486 if (pi->mem_gddr5) {
4487 table->initialState.levels[0].strobeMode =
4488 si_get_strobe_mode_settings(rdev,
4489 initial_state->performance_levels[0].mclk);
4490
4491 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4492 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4493 else
4494 table->initialState.levels[0].mcFlags = 0;
4495 }
4496
4497 table->initialState.levelCount = 1;
4498
4499 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4500
4501 table->initialState.levels[0].dpm2.MaxPS = 0;
4502 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4503 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4504 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4505 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4506
4507 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4508 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4509
4510 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4511 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4512
4513 return 0;
4514}
4515
4516static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4517 SISLANDS_SMC_STATETABLE *table)
4518{
4519 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4520 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4521 struct si_power_info *si_pi = si_get_pi(rdev);
4522 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4523 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4524 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4525 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4526 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4527 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4528 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4529 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4530 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4531 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4532 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4533 u32 reg;
4534 int ret;
4535
4536 table->ACPIState = table->initialState;
4537
4538 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4539
4540 if (pi->acpi_vddc) {
4541 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4542 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4543 if (!ret) {
4544 u16 std_vddc;
4545
4546 ret = si_get_std_voltage_value(rdev,
4547 &table->ACPIState.levels[0].vddc, &std_vddc);
4548 if (!ret)
4549 si_populate_std_voltage_value(rdev, std_vddc,
4550 table->ACPIState.levels[0].vddc.index,
4551 &table->ACPIState.levels[0].std_vddc);
4552 }
4553 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4554
4555 if (si_pi->vddc_phase_shed_control) {
4556 si_populate_phase_shedding_value(rdev,
4557 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4558 pi->acpi_vddc,
4559 0,
4560 0,
4561 &table->ACPIState.levels[0].vddc);
4562 }
4563 } else {
4564 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4565 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4566 if (!ret) {
4567 u16 std_vddc;
4568
4569 ret = si_get_std_voltage_value(rdev,
4570 &table->ACPIState.levels[0].vddc, &std_vddc);
4571
4572 if (!ret)
4573 si_populate_std_voltage_value(rdev, std_vddc,
4574 table->ACPIState.levels[0].vddc.index,
4575 &table->ACPIState.levels[0].std_vddc);
4576 }
4577 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4578 si_pi->sys_pcie_mask,
4579 si_pi->boot_pcie_gen,
4580 RADEON_PCIE_GEN1);
4581
4582 if (si_pi->vddc_phase_shed_control)
4583 si_populate_phase_shedding_value(rdev,
4584 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4585 pi->min_vddc_in_table,
4586 0,
4587 0,
4588 &table->ACPIState.levels[0].vddc);
4589 }
4590
4591 if (pi->acpi_vddc) {
4592 if (eg_pi->acpi_vddci)
4593 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4594 eg_pi->acpi_vddci,
4595 &table->ACPIState.levels[0].vddci);
4596 }
4597
4598 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4599 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4600
4601 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4602
4603 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4604 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4605
4606 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4607 cpu_to_be32(dll_cntl);
4608 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4609 cpu_to_be32(mclk_pwrmgt_cntl);
4610 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4611 cpu_to_be32(mpll_ad_func_cntl);
4612 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4613 cpu_to_be32(mpll_dq_func_cntl);
4614 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4615 cpu_to_be32(mpll_func_cntl);
4616 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4617 cpu_to_be32(mpll_func_cntl_1);
4618 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4619 cpu_to_be32(mpll_func_cntl_2);
4620 table->ACPIState.levels[0].mclk.vMPLL_SS =
4621 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4622 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4623 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4624
4625 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4626 cpu_to_be32(spll_func_cntl);
4627 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4628 cpu_to_be32(spll_func_cntl_2);
4629 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4630 cpu_to_be32(spll_func_cntl_3);
4631 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4632 cpu_to_be32(spll_func_cntl_4);
4633
4634 table->ACPIState.levels[0].mclk.mclk_value = 0;
4635 table->ACPIState.levels[0].sclk.sclk_value = 0;
4636
4637 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4638
4639 if (eg_pi->dynamic_ac_timing)
4640 table->ACPIState.levels[0].ACIndex = 0;
4641
4642 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4643 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4644 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4645 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4646 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4647
4648 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4649 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4650
4651 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4652 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4653
4654 return 0;
4655}
4656
4657static int si_populate_ulv_state(struct radeon_device *rdev,
4658 SISLANDS_SMC_SWSTATE *state)
4659{
4660 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4661 struct si_power_info *si_pi = si_get_pi(rdev);
4662 struct si_ulv_param *ulv = &si_pi->ulv;
4663 u32 sclk_in_sr = 1350; /* ??? */
4664 int ret;
4665
4666 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4667 &state->levels[0]);
4668 if (!ret) {
4669 if (eg_pi->sclk_deep_sleep) {
4670 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4671 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4672 else
4673 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4674 }
4675 if (ulv->one_pcie_lane_in_ulv)
4676 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4677 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4678 state->levels[0].ACIndex = 1;
4679 state->levels[0].std_vddc = state->levels[0].vddc;
4680 state->levelCount = 1;
4681
4682 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4683 }
4684
4685 return ret;
4686}
4687
4688static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4689{
4690 struct si_power_info *si_pi = si_get_pi(rdev);
4691 struct si_ulv_param *ulv = &si_pi->ulv;
4692 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4693 int ret;
4694
4695 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4696 &arb_regs);
4697 if (ret)
4698 return ret;
4699
4700 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4701 ulv->volt_change_delay);
4702
4703 ret = si_copy_bytes_to_smc(rdev,
4704 si_pi->arb_table_start +
4705 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4706 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4707 (u8 *)&arb_regs,
4708 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4709 si_pi->sram_end);
4710
4711 return ret;
4712}
4713
4714static void si_get_mvdd_configuration(struct radeon_device *rdev)
4715{
4716 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4717
4718 pi->mvdd_split_frequency = 30000;
4719}
4720
4721static int si_init_smc_table(struct radeon_device *rdev)
4722{
4723 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4724 struct si_power_info *si_pi = si_get_pi(rdev);
4725 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4726 const struct si_ulv_param *ulv = &si_pi->ulv;
4727 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4728 int ret;
4729 u32 lane_width;
4730 u32 vr_hot_gpio;
4731
4732 si_populate_smc_voltage_tables(rdev, table);
4733
4734 switch (rdev->pm.int_thermal_type) {
4735 case THERMAL_TYPE_SI:
4736 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4737 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4738 break;
4739 case THERMAL_TYPE_NONE:
4740 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4741 break;
4742 default:
4743 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4744 break;
4745 }
4746
4747 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4748 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4749
4750 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4751 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4752 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4753 }
4754
4755 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4756 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4757
4758 if (pi->mem_gddr5)
4759 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4760
4761 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4762 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4763
4764 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4765 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4766 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4767 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4768 vr_hot_gpio);
4769 }
4770
4771 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4772 if (ret)
4773 return ret;
4774
4775 ret = si_populate_smc_acpi_state(rdev, table);
4776 if (ret)
4777 return ret;
4778
4779 table->driverState = table->initialState;
4780
4781 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4782 SISLANDS_INITIAL_STATE_ARB_INDEX);
4783 if (ret)
4784 return ret;
4785
4786 if (ulv->supported && ulv->pl.vddc) {
4787 ret = si_populate_ulv_state(rdev, &table->ULVState);
4788 if (ret)
4789 return ret;
4790
4791 ret = si_program_ulv_memory_timing_parameters(rdev);
4792 if (ret)
4793 return ret;
4794
4795 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4796 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4797
4798 lane_width = radeon_get_pcie_lanes(rdev);
4799 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4800 } else {
4801 table->ULVState = table->initialState;
4802 }
4803
4804 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4805 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4806 si_pi->sram_end);
4807}
4808
4809static int si_calculate_sclk_params(struct radeon_device *rdev,
4810 u32 engine_clock,
4811 SISLANDS_SMC_SCLK_VALUE *sclk)
4812{
4813 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4814 struct si_power_info *si_pi = si_get_pi(rdev);
4815 struct atom_clock_dividers dividers;
4816 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4817 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4818 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4819 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4820 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4821 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4822 u64 tmp;
4823 u32 reference_clock = rdev->clock.spll.reference_freq;
4824 u32 reference_divider;
4825 u32 fbdiv;
4826 int ret;
4827
4828 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4829 engine_clock, false, ÷rs);
4830 if (ret)
4831 return ret;
4832
4833 reference_divider = 1 + dividers.ref_div;
4834
4835 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4836 do_div(tmp, reference_clock);
4837 fbdiv = (u32) tmp;
4838
4839 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4840 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4841 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4842
4843 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4844 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4845
4846 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4847 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4848 spll_func_cntl_3 |= SPLL_DITHEN;
4849
4850 if (pi->sclk_ss) {
4851 struct radeon_atom_ss ss;
4852 u32 vco_freq = engine_clock * dividers.post_div;
4853
4854 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4855 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4856 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4857 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4858
4859 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4860 cg_spll_spread_spectrum |= CLK_S(clk_s);
4861 cg_spll_spread_spectrum |= SSEN;
4862
4863 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4864 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4865 }
4866 }
4867
4868 sclk->sclk_value = engine_clock;
4869 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4870 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4871 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4872 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4873 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4874 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4875
4876 return 0;
4877}
4878
4879static int si_populate_sclk_value(struct radeon_device *rdev,
4880 u32 engine_clock,
4881 SISLANDS_SMC_SCLK_VALUE *sclk)
4882{
4883 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4884 int ret;
4885
4886 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4887 if (!ret) {
4888 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4889 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4890 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4891 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4892 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4893 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4894 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4895 }
4896
4897 return ret;
4898}
4899
4900static int si_populate_mclk_value(struct radeon_device *rdev,
4901 u32 engine_clock,
4902 u32 memory_clock,
4903 SISLANDS_SMC_MCLK_VALUE *mclk,
4904 bool strobe_mode,
4905 bool dll_state_on)
4906{
4907 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4908 struct si_power_info *si_pi = si_get_pi(rdev);
4909 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4910 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4911 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4912 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4913 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4914 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4915 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4916 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4917 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4918 struct atom_mpll_param mpll_param;
4919 int ret;
4920
4921 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4922 if (ret)
4923 return ret;
4924
4925 mpll_func_cntl &= ~BWCTRL_MASK;
4926 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4927
4928 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4929 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4930 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4931
4932 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4933 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4934
4935 if (pi->mem_gddr5) {
4936 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4937 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4938 YCLK_POST_DIV(mpll_param.post_div);
4939 }
4940
4941 if (pi->mclk_ss) {
4942 struct radeon_atom_ss ss;
4943 u32 freq_nom;
4944 u32 tmp;
4945 u32 reference_clock = rdev->clock.mpll.reference_freq;
4946
4947 if (pi->mem_gddr5)
4948 freq_nom = memory_clock * 4;
4949 else
4950 freq_nom = memory_clock * 2;
4951
4952 tmp = freq_nom / reference_clock;
4953 tmp = tmp * tmp;
4954 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4955 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4956 u32 clks = reference_clock * 5 / ss.rate;
4957 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4958
4959 mpll_ss1 &= ~CLKV_MASK;
4960 mpll_ss1 |= CLKV(clkv);
4961
4962 mpll_ss2 &= ~CLKS_MASK;
4963 mpll_ss2 |= CLKS(clks);
4964 }
4965 }
4966
4967 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4968 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4969
4970 if (dll_state_on)
4971 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4972 else
4973 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4974
4975 mclk->mclk_value = cpu_to_be32(memory_clock);
4976 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4977 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4978 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4979 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4980 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4981 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4982 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4983 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4984 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4985
4986 return 0;
4987}
4988
4989static void si_populate_smc_sp(struct radeon_device *rdev,
4990 struct radeon_ps *radeon_state,
4991 SISLANDS_SMC_SWSTATE *smc_state)
4992{
4993 struct ni_ps *ps = ni_get_ps(radeon_state);
4994 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4995 int i;
4996
4997 for (i = 0; i < ps->performance_level_count - 1; i++)
4998 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4999
5000 smc_state->levels[ps->performance_level_count - 1].bSP =
5001 cpu_to_be32(pi->psp);
5002}
5003
5004static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5005 struct rv7xx_pl *pl,
5006 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5007{
5008 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5009 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5010 struct si_power_info *si_pi = si_get_pi(rdev);
5011 int ret;
5012 bool dll_state_on;
5013 u16 std_vddc;
5014 bool gmc_pg = false;
5015
5016 if (eg_pi->pcie_performance_request &&
5017 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5018 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5019 else
5020 level->gen2PCIE = (u8)pl->pcie_gen;
5021
5022 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5023 if (ret)
5024 return ret;
5025
5026 level->mcFlags = 0;
5027
5028 if (pi->mclk_stutter_mode_threshold &&
5029 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5030 !eg_pi->uvd_enabled &&
5031 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5032 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5033 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5034
5035 if (gmc_pg)
5036 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5037 }
5038
5039 if (pi->mem_gddr5) {
5040 if (pl->mclk > pi->mclk_edc_enable_threshold)
5041 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5042
5043 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5044 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5045
5046 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5047
5048 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5049 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5050 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5051 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5052 else
5053 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5054 } else {
5055 dll_state_on = false;
5056 }
5057 } else {
5058 level->strobeMode = si_get_strobe_mode_settings(rdev,
5059 pl->mclk);
5060
5061 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5062 }
5063
5064 ret = si_populate_mclk_value(rdev,
5065 pl->sclk,
5066 pl->mclk,
5067 &level->mclk,
5068 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5069 if (ret)
5070 return ret;
5071
5072 ret = si_populate_voltage_value(rdev,
5073 &eg_pi->vddc_voltage_table,
5074 pl->vddc, &level->vddc);
5075 if (ret)
5076 return ret;
5077
5078
5079 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5080 if (ret)
5081 return ret;
5082
5083 ret = si_populate_std_voltage_value(rdev, std_vddc,
5084 level->vddc.index, &level->std_vddc);
5085 if (ret)
5086 return ret;
5087
5088 if (eg_pi->vddci_control) {
5089 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5090 pl->vddci, &level->vddci);
5091 if (ret)
5092 return ret;
5093 }
5094
5095 if (si_pi->vddc_phase_shed_control) {
5096 ret = si_populate_phase_shedding_value(rdev,
5097 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5098 pl->vddc,
5099 pl->sclk,
5100 pl->mclk,
5101 &level->vddc);
5102 if (ret)
5103 return ret;
5104 }
5105
5106 level->MaxPoweredUpCU = si_pi->max_cu;
5107
5108 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5109
5110 return ret;
5111}
5112
5113static int si_populate_smc_t(struct radeon_device *rdev,
5114 struct radeon_ps *radeon_state,
5115 SISLANDS_SMC_SWSTATE *smc_state)
5116{
5117 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5118 struct ni_ps *state = ni_get_ps(radeon_state);
5119 u32 a_t;
5120 u32 t_l, t_h;
5121 u32 high_bsp;
5122 int i, ret;
5123
5124 if (state->performance_level_count >= 9)
5125 return -EINVAL;
5126
5127 if (state->performance_level_count < 2) {
5128 a_t = CG_R(0xffff) | CG_L(0);
5129 smc_state->levels[0].aT = cpu_to_be32(a_t);
5130 return 0;
5131 }
5132
5133 smc_state->levels[0].aT = cpu_to_be32(0);
5134
5135 for (i = 0; i <= state->performance_level_count - 2; i++) {
5136 ret = r600_calculate_at(
5137 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5138 100 * R600_AH_DFLT,
5139 state->performance_levels[i + 1].sclk,
5140 state->performance_levels[i].sclk,
5141 &t_l,
5142 &t_h);
5143
5144 if (ret) {
5145 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5146 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5147 }
5148
5149 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5150 a_t |= CG_R(t_l * pi->bsp / 20000);
5151 smc_state->levels[i].aT = cpu_to_be32(a_t);
5152
5153 high_bsp = (i == state->performance_level_count - 2) ?
5154 pi->pbsp : pi->bsp;
5155 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5156 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5157 }
5158
5159 return 0;
5160}
5161
5162static int si_disable_ulv(struct radeon_device *rdev)
5163{
5164 struct si_power_info *si_pi = si_get_pi(rdev);
5165 struct si_ulv_param *ulv = &si_pi->ulv;
5166
5167 if (ulv->supported)
5168 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5169 0 : -EINVAL;
5170
5171 return 0;
5172}
5173
5174static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5175 struct radeon_ps *radeon_state)
5176{
5177 const struct si_power_info *si_pi = si_get_pi(rdev);
5178 const struct si_ulv_param *ulv = &si_pi->ulv;
5179 const struct ni_ps *state = ni_get_ps(radeon_state);
5180 int i;
5181
5182 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5183 return false;
5184
5185 /* XXX validate against display requirements! */
5186
5187 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5188 if (rdev->clock.current_dispclk <=
5189 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5190 if (ulv->pl.vddc <
5191 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5192 return false;
5193 }
5194 }
5195
5196 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5197 return false;
5198
5199 return true;
5200}
5201
5202static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5203 struct radeon_ps *radeon_new_state)
5204{
5205 const struct si_power_info *si_pi = si_get_pi(rdev);
5206 const struct si_ulv_param *ulv = &si_pi->ulv;
5207
5208 if (ulv->supported) {
5209 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5210 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5211 0 : -EINVAL;
5212 }
5213 return 0;
5214}
5215
5216static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5217 struct radeon_ps *radeon_state,
5218 SISLANDS_SMC_SWSTATE *smc_state)
5219{
5220 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5221 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5222 struct si_power_info *si_pi = si_get_pi(rdev);
5223 struct ni_ps *state = ni_get_ps(radeon_state);
5224 int i, ret;
5225 u32 threshold;
5226 u32 sclk_in_sr = 1350; /* ??? */
5227
5228 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5229 return -EINVAL;
5230
5231 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5232
5233 if (radeon_state->vclk && radeon_state->dclk) {
5234 eg_pi->uvd_enabled = true;
5235 if (eg_pi->smu_uvd_hs)
5236 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5237 } else {
5238 eg_pi->uvd_enabled = false;
5239 }
5240
5241 if (state->dc_compatible)
5242 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5243
5244 smc_state->levelCount = 0;
5245 for (i = 0; i < state->performance_level_count; i++) {
5246 if (eg_pi->sclk_deep_sleep) {
5247 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5248 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5249 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5250 else
5251 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5252 }
5253 }
5254
5255 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5256 &smc_state->levels[i]);
5257 smc_state->levels[i].arbRefreshState =
5258 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5259
5260 if (ret)
5261 return ret;
5262
5263 if (ni_pi->enable_power_containment)
5264 smc_state->levels[i].displayWatermark =
5265 (state->performance_levels[i].sclk < threshold) ?
5266 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5267 else
5268 smc_state->levels[i].displayWatermark = (i < 2) ?
5269 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5270
5271 if (eg_pi->dynamic_ac_timing)
5272 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5273 else
5274 smc_state->levels[i].ACIndex = 0;
5275
5276 smc_state->levelCount++;
5277 }
5278
5279 si_write_smc_soft_register(rdev,
5280 SI_SMC_SOFT_REGISTER_watermark_threshold,
5281 threshold / 512);
5282
5283 si_populate_smc_sp(rdev, radeon_state, smc_state);
5284
5285 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5286 if (ret)
5287 ni_pi->enable_power_containment = false;
5288
5289 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5290 if (ret)
5291 ni_pi->enable_sq_ramping = false;
5292
5293 return si_populate_smc_t(rdev, radeon_state, smc_state);
5294}
5295
5296static int si_upload_sw_state(struct radeon_device *rdev,
5297 struct radeon_ps *radeon_new_state)
5298{
5299 struct si_power_info *si_pi = si_get_pi(rdev);
5300 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5301 int ret;
5302 u32 address = si_pi->state_table_start +
5303 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5304 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5305 ((new_state->performance_level_count - 1) *
5306 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5307 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5308
5309 memset(smc_state, 0, state_size);
5310
5311 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5312 if (ret)
5313 return ret;
5314
5315 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5316 state_size, si_pi->sram_end);
5317
5318 return ret;
5319}
5320
5321static int si_upload_ulv_state(struct radeon_device *rdev)
5322{
5323 struct si_power_info *si_pi = si_get_pi(rdev);
5324 struct si_ulv_param *ulv = &si_pi->ulv;
5325 int ret = 0;
5326
5327 if (ulv->supported && ulv->pl.vddc) {
5328 u32 address = si_pi->state_table_start +
5329 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5330 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5331 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5332
5333 memset(smc_state, 0, state_size);
5334
5335 ret = si_populate_ulv_state(rdev, smc_state);
5336 if (!ret)
5337 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5338 state_size, si_pi->sram_end);
5339 }
5340
5341 return ret;
5342}
5343
5344static int si_upload_smc_data(struct radeon_device *rdev)
5345{
5346 struct radeon_crtc *radeon_crtc = NULL;
5347 int i;
5348
5349 if (rdev->pm.dpm.new_active_crtc_count == 0)
5350 return 0;
5351
5352 for (i = 0; i < rdev->num_crtc; i++) {
5353 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5354 radeon_crtc = rdev->mode_info.crtcs[i];
5355 break;
5356 }
5357 }
5358
5359 if (radeon_crtc == NULL)
5360 return 0;
5361
5362 if (radeon_crtc->line_time <= 0)
5363 return 0;
5364
5365 if (si_write_smc_soft_register(rdev,
5366 SI_SMC_SOFT_REGISTER_crtc_index,
5367 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5368 return 0;
5369
5370 if (si_write_smc_soft_register(rdev,
5371 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5372 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5373 return 0;
5374
5375 if (si_write_smc_soft_register(rdev,
5376 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5377 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5378 return 0;
5379
5380 return 0;
5381}
5382
5383static int si_set_mc_special_registers(struct radeon_device *rdev,
5384 struct si_mc_reg_table *table)
5385{
5386 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5387 u8 i, j, k;
5388 u32 temp_reg;
5389
5390 for (i = 0, j = table->last; i < table->last; i++) {
5391 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5392 return -EINVAL;
5393 switch (table->mc_reg_address[i].s1 << 2) {
5394 case MC_SEQ_MISC1:
5395 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5396 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5397 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5398 for (k = 0; k < table->num_entries; k++)
5399 table->mc_reg_table_entry[k].mc_data[j] =
5400 ((temp_reg & 0xffff0000)) |
5401 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5402 j++;
5403 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5404 return -EINVAL;
5405
5406 temp_reg = RREG32(MC_PMG_CMD_MRS);
5407 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5408 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5409 for (k = 0; k < table->num_entries; k++) {
5410 table->mc_reg_table_entry[k].mc_data[j] =
5411 (temp_reg & 0xffff0000) |
5412 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5413 if (!pi->mem_gddr5)
5414 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5415 }
5416 j++;
5417 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5418 return -EINVAL;
5419
5420 if (!pi->mem_gddr5) {
5421 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5422 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5423 for (k = 0; k < table->num_entries; k++)
5424 table->mc_reg_table_entry[k].mc_data[j] =
5425 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5426 j++;
5427 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5428 return -EINVAL;
5429 }
5430 break;
5431 case MC_SEQ_RESERVE_M:
5432 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5433 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5434 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5435 for(k = 0; k < table->num_entries; k++)
5436 table->mc_reg_table_entry[k].mc_data[j] =
5437 (temp_reg & 0xffff0000) |
5438 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5439 j++;
5440 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5441 return -EINVAL;
5442 break;
5443 default:
5444 break;
5445 }
5446 }
5447
5448 table->last = j;
5449
5450 return 0;
5451}
5452
5453static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5454{
5455 bool result = true;
5456
5457 switch (in_reg) {
5458 case MC_SEQ_RAS_TIMING >> 2:
5459 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5460 break;
5461 case MC_SEQ_CAS_TIMING >> 2:
5462 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5463 break;
5464 case MC_SEQ_MISC_TIMING >> 2:
5465 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5466 break;
5467 case MC_SEQ_MISC_TIMING2 >> 2:
5468 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5469 break;
5470 case MC_SEQ_RD_CTL_D0 >> 2:
5471 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5472 break;
5473 case MC_SEQ_RD_CTL_D1 >> 2:
5474 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5475 break;
5476 case MC_SEQ_WR_CTL_D0 >> 2:
5477 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5478 break;
5479 case MC_SEQ_WR_CTL_D1 >> 2:
5480 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5481 break;
5482 case MC_PMG_CMD_EMRS >> 2:
5483 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5484 break;
5485 case MC_PMG_CMD_MRS >> 2:
5486 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5487 break;
5488 case MC_PMG_CMD_MRS1 >> 2:
5489 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5490 break;
5491 case MC_SEQ_PMG_TIMING >> 2:
5492 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5493 break;
5494 case MC_PMG_CMD_MRS2 >> 2:
5495 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5496 break;
5497 case MC_SEQ_WR_CTL_2 >> 2:
5498 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5499 break;
5500 default:
5501 result = false;
5502 break;
5503 }
5504
5505 return result;
5506}
5507
5508static void si_set_valid_flag(struct si_mc_reg_table *table)
5509{
5510 u8 i, j;
5511
5512 for (i = 0; i < table->last; i++) {
5513 for (j = 1; j < table->num_entries; j++) {
5514 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5515 table->valid_flag |= 1 << i;
5516 break;
5517 }
5518 }
5519 }
5520}
5521
5522static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5523{
5524 u32 i;
5525 u16 address;
5526
5527 for (i = 0; i < table->last; i++)
5528 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5529 address : table->mc_reg_address[i].s1;
5530
5531}
5532
5533static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5534 struct si_mc_reg_table *si_table)
5535{
5536 u8 i, j;
5537
5538 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5539 return -EINVAL;
5540 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5541 return -EINVAL;
5542
5543 for (i = 0; i < table->last; i++)
5544 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5545 si_table->last = table->last;
5546
5547 for (i = 0; i < table->num_entries; i++) {
5548 si_table->mc_reg_table_entry[i].mclk_max =
5549 table->mc_reg_table_entry[i].mclk_max;
5550 for (j = 0; j < table->last; j++) {
5551 si_table->mc_reg_table_entry[i].mc_data[j] =
5552 table->mc_reg_table_entry[i].mc_data[j];
5553 }
5554 }
5555 si_table->num_entries = table->num_entries;
5556
5557 return 0;
5558}
5559
5560static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5561{
5562 struct si_power_info *si_pi = si_get_pi(rdev);
5563 struct atom_mc_reg_table *table;
5564 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5565 u8 module_index = rv770_get_memory_module_index(rdev);
5566 int ret;
5567
5568 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5569 if (!table)
5570 return -ENOMEM;
5571
5572 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5573 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5574 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5575 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5576 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5577 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5578 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5579 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5580 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5581 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5582 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5583 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5584 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5585 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5586
5587 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5588 if (ret)
5589 goto init_mc_done;
5590
5591 ret = si_copy_vbios_mc_reg_table(table, si_table);
5592 if (ret)
5593 goto init_mc_done;
5594
5595 si_set_s0_mc_reg_index(si_table);
5596
5597 ret = si_set_mc_special_registers(rdev, si_table);
5598 if (ret)
5599 goto init_mc_done;
5600
5601 si_set_valid_flag(si_table);
5602
5603init_mc_done:
5604 kfree(table);
5605
5606 return ret;
5607
5608}
5609
5610static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5611 SMC_SIslands_MCRegisters *mc_reg_table)
5612{
5613 struct si_power_info *si_pi = si_get_pi(rdev);
5614 u32 i, j;
5615
5616 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5617 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5618 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5619 break;
5620 mc_reg_table->address[i].s0 =
5621 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5622 mc_reg_table->address[i].s1 =
5623 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5624 i++;
5625 }
5626 }
5627 mc_reg_table->last = (u8)i;
5628}
5629
5630static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5631 SMC_SIslands_MCRegisterSet *data,
5632 u32 num_entries, u32 valid_flag)
5633{
5634 u32 i, j;
5635
5636 for(i = 0, j = 0; j < num_entries; j++) {
5637 if (valid_flag & (1 << j)) {
5638 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5639 i++;
5640 }
5641 }
5642}
5643
5644static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5645 struct rv7xx_pl *pl,
5646 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5647{
5648 struct si_power_info *si_pi = si_get_pi(rdev);
5649 u32 i = 0;
5650
5651 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5652 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5653 break;
5654 }
5655
5656 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5657 --i;
5658
5659 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5660 mc_reg_table_data, si_pi->mc_reg_table.last,
5661 si_pi->mc_reg_table.valid_flag);
5662}
5663
5664static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5665 struct radeon_ps *radeon_state,
5666 SMC_SIslands_MCRegisters *mc_reg_table)
5667{
5668 struct ni_ps *state = ni_get_ps(radeon_state);
5669 int i;
5670
5671 for (i = 0; i < state->performance_level_count; i++) {
5672 si_convert_mc_reg_table_entry_to_smc(rdev,
5673 &state->performance_levels[i],
5674 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5675 }
5676}
5677
5678static int si_populate_mc_reg_table(struct radeon_device *rdev,
5679 struct radeon_ps *radeon_boot_state)
5680{
5681 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5682 struct si_power_info *si_pi = si_get_pi(rdev);
5683 struct si_ulv_param *ulv = &si_pi->ulv;
5684 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5685
5686 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5687
5688 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5689
5690 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5691
5692 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5693 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5694
5695 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5696 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5697 si_pi->mc_reg_table.last,
5698 si_pi->mc_reg_table.valid_flag);
5699
5700 if (ulv->supported && ulv->pl.vddc != 0)
5701 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5702 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5703 else
5704 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5705 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5706 si_pi->mc_reg_table.last,
5707 si_pi->mc_reg_table.valid_flag);
5708
5709 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5710
5711 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5712 (u8 *)smc_mc_reg_table,
5713 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5714}
5715
5716static int si_upload_mc_reg_table(struct radeon_device *rdev,
5717 struct radeon_ps *radeon_new_state)
5718{
5719 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5720 struct si_power_info *si_pi = si_get_pi(rdev);
5721 u32 address = si_pi->mc_reg_table_start +
5722 offsetof(SMC_SIslands_MCRegisters,
5723 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5724 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5725
5726 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5727
5728 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5729
5730
5731 return si_copy_bytes_to_smc(rdev, address,
5732 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5733 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5734 si_pi->sram_end);
5735
5736}
5737
5738static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5739{
5740 if (enable)
5741 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5742 else
5743 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5744}
5745
5746static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5747 struct radeon_ps *radeon_state)
5748{
5749 struct ni_ps *state = ni_get_ps(radeon_state);
5750 int i;
5751 u16 pcie_speed, max_speed = 0;
5752
5753 for (i = 0; i < state->performance_level_count; i++) {
5754 pcie_speed = state->performance_levels[i].pcie_gen;
5755 if (max_speed < pcie_speed)
5756 max_speed = pcie_speed;
5757 }
5758 return max_speed;
5759}
5760
5761static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5762{
5763 u32 speed_cntl;
5764
5765 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5766 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5767
5768 return (u16)speed_cntl;
5769}
5770
5771static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5772 struct radeon_ps *radeon_new_state,
5773 struct radeon_ps *radeon_current_state)
5774{
5775 struct si_power_info *si_pi = si_get_pi(rdev);
5776 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5777 enum radeon_pcie_gen current_link_speed;
5778
5779 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5780 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5781 else
5782 current_link_speed = si_pi->force_pcie_gen;
5783
5784 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5785 si_pi->pspp_notify_required = false;
5786 if (target_link_speed > current_link_speed) {
5787 switch (target_link_speed) {
5788#if defined(CONFIG_ACPI)
5789 case RADEON_PCIE_GEN3:
5790 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5791 break;
5792 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5793 if (current_link_speed == RADEON_PCIE_GEN2)
5794 break;
5795 case RADEON_PCIE_GEN2:
5796 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5797 break;
5798#endif
5799 default:
5800 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5801 break;
5802 }
5803 } else {
5804 if (target_link_speed < current_link_speed)
5805 si_pi->pspp_notify_required = true;
5806 }
5807}
5808
5809static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5810 struct radeon_ps *radeon_new_state,
5811 struct radeon_ps *radeon_current_state)
5812{
5813 struct si_power_info *si_pi = si_get_pi(rdev);
5814 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5815 u8 request;
5816
5817 if (si_pi->pspp_notify_required) {
5818 if (target_link_speed == RADEON_PCIE_GEN3)
5819 request = PCIE_PERF_REQ_PECI_GEN3;
5820 else if (target_link_speed == RADEON_PCIE_GEN2)
5821 request = PCIE_PERF_REQ_PECI_GEN2;
5822 else
5823 request = PCIE_PERF_REQ_PECI_GEN1;
5824
5825 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5826 (si_get_current_pcie_speed(rdev) > 0))
5827 return;
5828
5829#if defined(CONFIG_ACPI)
5830 radeon_acpi_pcie_performance_request(rdev, request, false);
5831#endif
5832 }
5833}
5834
5835#if 0
5836static int si_ds_request(struct radeon_device *rdev,
5837 bool ds_status_on, u32 count_write)
5838{
5839 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5840
5841 if (eg_pi->sclk_deep_sleep) {
5842 if (ds_status_on)
5843 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5844 PPSMC_Result_OK) ?
5845 0 : -EINVAL;
5846 else
5847 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5848 PPSMC_Result_OK) ? 0 : -EINVAL;
5849 }
5850 return 0;
5851}
5852#endif
5853
5854static void si_set_max_cu_value(struct radeon_device *rdev)
5855{
5856 struct si_power_info *si_pi = si_get_pi(rdev);
5857
5858 if (rdev->family == CHIP_VERDE) {
5859 switch (rdev->pdev->device) {
5860 case 0x6820:
5861 case 0x6825:
5862 case 0x6821:
5863 case 0x6823:
5864 case 0x6827:
5865 si_pi->max_cu = 10;
5866 break;
5867 case 0x682D:
5868 case 0x6824:
5869 case 0x682F:
5870 case 0x6826:
5871 si_pi->max_cu = 8;
5872 break;
5873 case 0x6828:
5874 case 0x6830:
5875 case 0x6831:
5876 case 0x6838:
5877 case 0x6839:
5878 case 0x683D:
5879 si_pi->max_cu = 10;
5880 break;
5881 case 0x683B:
5882 case 0x683F:
5883 case 0x6829:
5884 si_pi->max_cu = 8;
5885 break;
5886 default:
5887 si_pi->max_cu = 0;
5888 break;
5889 }
5890 } else {
5891 si_pi->max_cu = 0;
5892 }
5893}
5894
5895static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5896 struct radeon_clock_voltage_dependency_table *table)
5897{
5898 u32 i;
5899 int j;
5900 u16 leakage_voltage;
5901
5902 if (table) {
5903 for (i = 0; i < table->count; i++) {
5904 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5905 table->entries[i].v,
5906 &leakage_voltage)) {
5907 case 0:
5908 table->entries[i].v = leakage_voltage;
5909 break;
5910 case -EAGAIN:
5911 return -EINVAL;
5912 case -EINVAL:
5913 default:
5914 break;
5915 }
5916 }
5917
5918 for (j = (table->count - 2); j >= 0; j--) {
5919 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5920 table->entries[j].v : table->entries[j + 1].v;
5921 }
5922 }
5923 return 0;
5924}
5925
5926static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5927{
5928 int ret = 0;
5929
5930 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5931 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5932 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5933 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5934 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5935 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5936 return ret;
5937}
5938
5939static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5940 struct radeon_ps *radeon_new_state,
5941 struct radeon_ps *radeon_current_state)
5942{
5943 u32 lane_width;
5944 u32 new_lane_width =
5945 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5946 u32 current_lane_width =
5947 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5948
5949 if (new_lane_width != current_lane_width) {
5950 radeon_set_pcie_lanes(rdev, new_lane_width);
5951 lane_width = radeon_get_pcie_lanes(rdev);
5952 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5953 }
5954}
5955
5956static void si_set_vce_clock(struct radeon_device *rdev,
5957 struct radeon_ps *new_rps,
5958 struct radeon_ps *old_rps)
5959{
5960 if ((old_rps->evclk != new_rps->evclk) ||
5961 (old_rps->ecclk != new_rps->ecclk)) {
5962 /* turn the clocks on when encoding, off otherwise */
5963 if (new_rps->evclk || new_rps->ecclk)
5964 vce_v1_0_enable_mgcg(rdev, false);
5965 else
5966 vce_v1_0_enable_mgcg(rdev, true);
5967 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5968 }
5969}
5970
5971void si_dpm_setup_asic(struct radeon_device *rdev)
5972{
5973 int r;
5974
5975 r = si_mc_load_microcode(rdev);
5976 if (r)
5977 DRM_ERROR("Failed to load MC firmware!\n");
5978 rv770_get_memory_type(rdev);
5979 si_read_clock_registers(rdev);
5980 si_enable_acpi_power_management(rdev);
5981}
5982
5983static int si_thermal_enable_alert(struct radeon_device *rdev,
5984 bool enable)
5985{
5986 u32 thermal_int = RREG32(CG_THERMAL_INT);
5987
5988 if (enable) {
5989 PPSMC_Result result;
5990
5991 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5992 WREG32(CG_THERMAL_INT, thermal_int);
5993 rdev->irq.dpm_thermal = false;
5994 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5995 if (result != PPSMC_Result_OK) {
5996 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5997 return -EINVAL;
5998 }
5999 } else {
6000 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6001 WREG32(CG_THERMAL_INT, thermal_int);
6002 rdev->irq.dpm_thermal = true;
6003 }
6004
6005 return 0;
6006}
6007
6008static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6009 int min_temp, int max_temp)
6010{
6011 int low_temp = 0 * 1000;
6012 int high_temp = 255 * 1000;
6013
6014 if (low_temp < min_temp)
6015 low_temp = min_temp;
6016 if (high_temp > max_temp)
6017 high_temp = max_temp;
6018 if (high_temp < low_temp) {
6019 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6020 return -EINVAL;
6021 }
6022
6023 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6024 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6025 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6026
6027 rdev->pm.dpm.thermal.min_temp = low_temp;
6028 rdev->pm.dpm.thermal.max_temp = high_temp;
6029
6030 return 0;
6031}
6032
6033static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6034{
6035 struct si_power_info *si_pi = si_get_pi(rdev);
6036 u32 tmp;
6037
6038 if (si_pi->fan_ctrl_is_in_default_mode) {
6039 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6040 si_pi->fan_ctrl_default_mode = tmp;
6041 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6042 si_pi->t_min = tmp;
6043 si_pi->fan_ctrl_is_in_default_mode = false;
6044 }
6045
6046 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6047 tmp |= TMIN(0);
6048 WREG32(CG_FDO_CTRL2, tmp);
6049
6050 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6051 tmp |= FDO_PWM_MODE(mode);
6052 WREG32(CG_FDO_CTRL2, tmp);
6053}
6054
6055static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6056{
6057 struct si_power_info *si_pi = si_get_pi(rdev);
6058 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6059 u32 duty100;
6060 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6061 u16 fdo_min, slope1, slope2;
6062 u32 reference_clock, tmp;
6063 int ret;
6064 u64 tmp64;
6065
6066 if (!si_pi->fan_table_start) {
6067 rdev->pm.dpm.fan.ucode_fan_control = false;
6068 return 0;
6069 }
6070
6071 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6072
6073 if (duty100 == 0) {
6074 rdev->pm.dpm.fan.ucode_fan_control = false;
6075 return 0;
6076 }
6077
6078 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6079 do_div(tmp64, 10000);
6080 fdo_min = (u16)tmp64;
6081
6082 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6083 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6084
6085 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6086 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6087
6088 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6089 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6090
6091 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6092 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6093 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6094
6095 fan_table.slope1 = cpu_to_be16(slope1);
6096 fan_table.slope2 = cpu_to_be16(slope2);
6097
6098 fan_table.fdo_min = cpu_to_be16(fdo_min);
6099
6100 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6101
6102 fan_table.hys_up = cpu_to_be16(1);
6103
6104 fan_table.hys_slope = cpu_to_be16(1);
6105
6106 fan_table.temp_resp_lim = cpu_to_be16(5);
6107
6108 reference_clock = radeon_get_xclk(rdev);
6109
6110 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6111 reference_clock) / 1600);
6112
6113 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6114
6115 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6116 fan_table.temp_src = (uint8_t)tmp;
6117
6118 ret = si_copy_bytes_to_smc(rdev,
6119 si_pi->fan_table_start,
6120 (u8 *)(&fan_table),
6121 sizeof(fan_table),
6122 si_pi->sram_end);
6123
6124 if (ret) {
6125 DRM_ERROR("Failed to load fan table to the SMC.");
6126 rdev->pm.dpm.fan.ucode_fan_control = false;
6127 }
6128
6129 return 0;
6130}
6131
6132static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6133{
6134 struct si_power_info *si_pi = si_get_pi(rdev);
6135 PPSMC_Result ret;
6136
6137 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6138 if (ret == PPSMC_Result_OK) {
6139 si_pi->fan_is_controlled_by_smc = true;
6140 return 0;
6141 } else {
6142 return -EINVAL;
6143 }
6144}
6145
6146static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6147{
6148 struct si_power_info *si_pi = si_get_pi(rdev);
6149 PPSMC_Result ret;
6150
6151 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6152
6153 if (ret == PPSMC_Result_OK) {
6154 si_pi->fan_is_controlled_by_smc = false;
6155 return 0;
6156 } else {
6157 return -EINVAL;
6158 }
6159}
6160
6161int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6162 u32 *speed)
6163{
6164 u32 duty, duty100;
6165 u64 tmp64;
6166
6167 if (rdev->pm.no_fan)
6168 return -ENOENT;
6169
6170 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6171 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6172
6173 if (duty100 == 0)
6174 return -EINVAL;
6175
6176 tmp64 = (u64)duty * 100;
6177 do_div(tmp64, duty100);
6178 *speed = (u32)tmp64;
6179
6180 if (*speed > 100)
6181 *speed = 100;
6182
6183 return 0;
6184}
6185
6186int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6187 u32 speed)
6188{
6189 struct si_power_info *si_pi = si_get_pi(rdev);
6190 u32 tmp;
6191 u32 duty, duty100;
6192 u64 tmp64;
6193
6194 if (rdev->pm.no_fan)
6195 return -ENOENT;
6196
6197 if (si_pi->fan_is_controlled_by_smc)
6198 return -EINVAL;
6199
6200 if (speed > 100)
6201 return -EINVAL;
6202
6203 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6204
6205 if (duty100 == 0)
6206 return -EINVAL;
6207
6208 tmp64 = (u64)speed * duty100;
6209 do_div(tmp64, 100);
6210 duty = (u32)tmp64;
6211
6212 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6213 tmp |= FDO_STATIC_DUTY(duty);
6214 WREG32(CG_FDO_CTRL0, tmp);
6215
6216 return 0;
6217}
6218
6219void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6220{
6221 if (mode) {
6222 /* stop auto-manage */
6223 if (rdev->pm.dpm.fan.ucode_fan_control)
6224 si_fan_ctrl_stop_smc_fan_control(rdev);
6225 si_fan_ctrl_set_static_mode(rdev, mode);
6226 } else {
6227 /* restart auto-manage */
6228 if (rdev->pm.dpm.fan.ucode_fan_control)
6229 si_thermal_start_smc_fan_control(rdev);
6230 else
6231 si_fan_ctrl_set_default_mode(rdev);
6232 }
6233}
6234
6235u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6236{
6237 struct si_power_info *si_pi = si_get_pi(rdev);
6238 u32 tmp;
6239
6240 if (si_pi->fan_is_controlled_by_smc)
6241 return 0;
6242
6243 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6244 return (tmp >> FDO_PWM_MODE_SHIFT);
6245}
6246
6247#if 0
6248static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6249 u32 *speed)
6250{
6251 u32 tach_period;
6252 u32 xclk = radeon_get_xclk(rdev);
6253
6254 if (rdev->pm.no_fan)
6255 return -ENOENT;
6256
6257 if (rdev->pm.fan_pulses_per_revolution == 0)
6258 return -ENOENT;
6259
6260 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6261 if (tach_period == 0)
6262 return -ENOENT;
6263
6264 *speed = 60 * xclk * 10000 / tach_period;
6265
6266 return 0;
6267}
6268
6269static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6270 u32 speed)
6271{
6272 u32 tach_period, tmp;
6273 u32 xclk = radeon_get_xclk(rdev);
6274
6275 if (rdev->pm.no_fan)
6276 return -ENOENT;
6277
6278 if (rdev->pm.fan_pulses_per_revolution == 0)
6279 return -ENOENT;
6280
6281 if ((speed < rdev->pm.fan_min_rpm) ||
6282 (speed > rdev->pm.fan_max_rpm))
6283 return -EINVAL;
6284
6285 if (rdev->pm.dpm.fan.ucode_fan_control)
6286 si_fan_ctrl_stop_smc_fan_control(rdev);
6287
6288 tach_period = 60 * xclk * 10000 / (8 * speed);
6289 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6290 tmp |= TARGET_PERIOD(tach_period);
6291 WREG32(CG_TACH_CTRL, tmp);
6292
6293 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6294
6295 return 0;
6296}
6297#endif
6298
6299static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6300{
6301 struct si_power_info *si_pi = si_get_pi(rdev);
6302 u32 tmp;
6303
6304 if (!si_pi->fan_ctrl_is_in_default_mode) {
6305 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6306 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6307 WREG32(CG_FDO_CTRL2, tmp);
6308
6309 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6310 tmp |= TMIN(si_pi->t_min);
6311 WREG32(CG_FDO_CTRL2, tmp);
6312 si_pi->fan_ctrl_is_in_default_mode = true;
6313 }
6314}
6315
6316static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6317{
6318 if (rdev->pm.dpm.fan.ucode_fan_control) {
6319 si_fan_ctrl_start_smc_fan_control(rdev);
6320 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6321 }
6322}
6323
6324static void si_thermal_initialize(struct radeon_device *rdev)
6325{
6326 u32 tmp;
6327
6328 if (rdev->pm.fan_pulses_per_revolution) {
6329 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6330 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6331 WREG32(CG_TACH_CTRL, tmp);
6332 }
6333
6334 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6335 tmp |= TACH_PWM_RESP_RATE(0x28);
6336 WREG32(CG_FDO_CTRL2, tmp);
6337}
6338
6339static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6340{
6341 int ret;
6342
6343 si_thermal_initialize(rdev);
6344 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6345 if (ret)
6346 return ret;
6347 ret = si_thermal_enable_alert(rdev, true);
6348 if (ret)
6349 return ret;
6350 if (rdev->pm.dpm.fan.ucode_fan_control) {
6351 ret = si_halt_smc(rdev);
6352 if (ret)
6353 return ret;
6354 ret = si_thermal_setup_fan_table(rdev);
6355 if (ret)
6356 return ret;
6357 ret = si_resume_smc(rdev);
6358 if (ret)
6359 return ret;
6360 si_thermal_start_smc_fan_control(rdev);
6361 }
6362
6363 return 0;
6364}
6365
6366static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6367{
6368 if (!rdev->pm.no_fan) {
6369 si_fan_ctrl_set_default_mode(rdev);
6370 si_fan_ctrl_stop_smc_fan_control(rdev);
6371 }
6372}
6373
6374int si_dpm_enable(struct radeon_device *rdev)
6375{
6376 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6377 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6378 struct si_power_info *si_pi = si_get_pi(rdev);
6379 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6380 int ret;
6381
6382 if (si_is_smc_running(rdev))
6383 return -EINVAL;
6384 if (pi->voltage_control || si_pi->voltage_control_svi2)
6385 si_enable_voltage_control(rdev, true);
6386 if (pi->mvdd_control)
6387 si_get_mvdd_configuration(rdev);
6388 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6389 ret = si_construct_voltage_tables(rdev);
6390 if (ret) {
6391 DRM_ERROR("si_construct_voltage_tables failed\n");
6392 return ret;
6393 }
6394 }
6395 if (eg_pi->dynamic_ac_timing) {
6396 ret = si_initialize_mc_reg_table(rdev);
6397 if (ret)
6398 eg_pi->dynamic_ac_timing = false;
6399 }
6400 if (pi->dynamic_ss)
6401 si_enable_spread_spectrum(rdev, true);
6402 if (pi->thermal_protection)
6403 si_enable_thermal_protection(rdev, true);
6404 si_setup_bsp(rdev);
6405 si_program_git(rdev);
6406 si_program_tp(rdev);
6407 si_program_tpp(rdev);
6408 si_program_sstp(rdev);
6409 si_enable_display_gap(rdev);
6410 si_program_vc(rdev);
6411 ret = si_upload_firmware(rdev);
6412 if (ret) {
6413 DRM_ERROR("si_upload_firmware failed\n");
6414 return ret;
6415 }
6416 ret = si_process_firmware_header(rdev);
6417 if (ret) {
6418 DRM_ERROR("si_process_firmware_header failed\n");
6419 return ret;
6420 }
6421 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6422 if (ret) {
6423 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6424 return ret;
6425 }
6426 ret = si_init_smc_table(rdev);
6427 if (ret) {
6428 DRM_ERROR("si_init_smc_table failed\n");
6429 return ret;
6430 }
6431 ret = si_init_smc_spll_table(rdev);
6432 if (ret) {
6433 DRM_ERROR("si_init_smc_spll_table failed\n");
6434 return ret;
6435 }
6436 ret = si_init_arb_table_index(rdev);
6437 if (ret) {
6438 DRM_ERROR("si_init_arb_table_index failed\n");
6439 return ret;
6440 }
6441 if (eg_pi->dynamic_ac_timing) {
6442 ret = si_populate_mc_reg_table(rdev, boot_ps);
6443 if (ret) {
6444 DRM_ERROR("si_populate_mc_reg_table failed\n");
6445 return ret;
6446 }
6447 }
6448 ret = si_initialize_smc_cac_tables(rdev);
6449 if (ret) {
6450 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6451 return ret;
6452 }
6453 ret = si_initialize_hardware_cac_manager(rdev);
6454 if (ret) {
6455 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6456 return ret;
6457 }
6458 ret = si_initialize_smc_dte_tables(rdev);
6459 if (ret) {
6460 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6461 return ret;
6462 }
6463 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6464 if (ret) {
6465 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6466 return ret;
6467 }
6468 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6469 if (ret) {
6470 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6471 return ret;
6472 }
6473 si_program_response_times(rdev);
6474 si_program_ds_registers(rdev);
6475 si_dpm_start_smc(rdev);
6476 ret = si_notify_smc_display_change(rdev, false);
6477 if (ret) {
6478 DRM_ERROR("si_notify_smc_display_change failed\n");
6479 return ret;
6480 }
6481 si_enable_sclk_control(rdev, true);
6482 si_start_dpm(rdev);
6483
6484 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6485
6486 si_thermal_start_thermal_controller(rdev);
6487
6488 ni_update_current_ps(rdev, boot_ps);
6489
6490 return 0;
6491}
6492
6493static int si_set_temperature_range(struct radeon_device *rdev)
6494{
6495 int ret;
6496
6497 ret = si_thermal_enable_alert(rdev, false);
6498 if (ret)
6499 return ret;
6500 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6501 if (ret)
6502 return ret;
6503 ret = si_thermal_enable_alert(rdev, true);
6504 if (ret)
6505 return ret;
6506
6507 return ret;
6508}
6509
6510int si_dpm_late_enable(struct radeon_device *rdev)
6511{
6512 int ret;
6513
6514 ret = si_set_temperature_range(rdev);
6515 if (ret)
6516 return ret;
6517
6518 return ret;
6519}
6520
6521void si_dpm_disable(struct radeon_device *rdev)
6522{
6523 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6524 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6525
6526 if (!si_is_smc_running(rdev))
6527 return;
6528 si_thermal_stop_thermal_controller(rdev);
6529 si_disable_ulv(rdev);
6530 si_clear_vc(rdev);
6531 if (pi->thermal_protection)
6532 si_enable_thermal_protection(rdev, false);
6533 si_enable_power_containment(rdev, boot_ps, false);
6534 si_enable_smc_cac(rdev, boot_ps, false);
6535 si_enable_spread_spectrum(rdev, false);
6536 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6537 si_stop_dpm(rdev);
6538 si_reset_to_default(rdev);
6539 si_dpm_stop_smc(rdev);
6540 si_force_switch_to_arb_f0(rdev);
6541
6542 ni_update_current_ps(rdev, boot_ps);
6543}
6544
6545int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6546{
6547 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6548 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6549 struct radeon_ps *new_ps = &requested_ps;
6550
6551 ni_update_requested_ps(rdev, new_ps);
6552
6553 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6554
6555 return 0;
6556}
6557
6558static int si_power_control_set_level(struct radeon_device *rdev)
6559{
6560 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6561 int ret;
6562
6563 ret = si_restrict_performance_levels_before_switch(rdev);
6564 if (ret)
6565 return ret;
6566 ret = si_halt_smc(rdev);
6567 if (ret)
6568 return ret;
6569 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6570 if (ret)
6571 return ret;
6572 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6573 if (ret)
6574 return ret;
6575 ret = si_resume_smc(rdev);
6576 if (ret)
6577 return ret;
6578 ret = si_set_sw_state(rdev);
6579 if (ret)
6580 return ret;
6581 return 0;
6582}
6583
6584int si_dpm_set_power_state(struct radeon_device *rdev)
6585{
6586 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6587 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6588 struct radeon_ps *old_ps = &eg_pi->current_rps;
6589 int ret;
6590
6591 ret = si_disable_ulv(rdev);
6592 if (ret) {
6593 DRM_ERROR("si_disable_ulv failed\n");
6594 return ret;
6595 }
6596 ret = si_restrict_performance_levels_before_switch(rdev);
6597 if (ret) {
6598 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6599 return ret;
6600 }
6601 if (eg_pi->pcie_performance_request)
6602 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6603 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6604 ret = si_enable_power_containment(rdev, new_ps, false);
6605 if (ret) {
6606 DRM_ERROR("si_enable_power_containment failed\n");
6607 return ret;
6608 }
6609 ret = si_enable_smc_cac(rdev, new_ps, false);
6610 if (ret) {
6611 DRM_ERROR("si_enable_smc_cac failed\n");
6612 return ret;
6613 }
6614 ret = si_halt_smc(rdev);
6615 if (ret) {
6616 DRM_ERROR("si_halt_smc failed\n");
6617 return ret;
6618 }
6619 ret = si_upload_sw_state(rdev, new_ps);
6620 if (ret) {
6621 DRM_ERROR("si_upload_sw_state failed\n");
6622 return ret;
6623 }
6624 ret = si_upload_smc_data(rdev);
6625 if (ret) {
6626 DRM_ERROR("si_upload_smc_data failed\n");
6627 return ret;
6628 }
6629 ret = si_upload_ulv_state(rdev);
6630 if (ret) {
6631 DRM_ERROR("si_upload_ulv_state failed\n");
6632 return ret;
6633 }
6634 if (eg_pi->dynamic_ac_timing) {
6635 ret = si_upload_mc_reg_table(rdev, new_ps);
6636 if (ret) {
6637 DRM_ERROR("si_upload_mc_reg_table failed\n");
6638 return ret;
6639 }
6640 }
6641 ret = si_program_memory_timing_parameters(rdev, new_ps);
6642 if (ret) {
6643 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6644 return ret;
6645 }
6646 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6647
6648 ret = si_resume_smc(rdev);
6649 if (ret) {
6650 DRM_ERROR("si_resume_smc failed\n");
6651 return ret;
6652 }
6653 ret = si_set_sw_state(rdev);
6654 if (ret) {
6655 DRM_ERROR("si_set_sw_state failed\n");
6656 return ret;
6657 }
6658 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6659 si_set_vce_clock(rdev, new_ps, old_ps);
6660 if (eg_pi->pcie_performance_request)
6661 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6662 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6663 if (ret) {
6664 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6665 return ret;
6666 }
6667 ret = si_enable_smc_cac(rdev, new_ps, true);
6668 if (ret) {
6669 DRM_ERROR("si_enable_smc_cac failed\n");
6670 return ret;
6671 }
6672 ret = si_enable_power_containment(rdev, new_ps, true);
6673 if (ret) {
6674 DRM_ERROR("si_enable_power_containment failed\n");
6675 return ret;
6676 }
6677
6678 ret = si_power_control_set_level(rdev);
6679 if (ret) {
6680 DRM_ERROR("si_power_control_set_level failed\n");
6681 return ret;
6682 }
6683
6684 return 0;
6685}
6686
6687void si_dpm_post_set_power_state(struct radeon_device *rdev)
6688{
6689 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6690 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6691
6692 ni_update_current_ps(rdev, new_ps);
6693}
6694
6695#if 0
6696void si_dpm_reset_asic(struct radeon_device *rdev)
6697{
6698 si_restrict_performance_levels_before_switch(rdev);
6699 si_disable_ulv(rdev);
6700 si_set_boot_state(rdev);
6701}
6702#endif
6703
6704void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6705{
6706 si_program_display_gap(rdev);
6707}
6708
6709union power_info {
6710 struct _ATOM_POWERPLAY_INFO info;
6711 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6712 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6713 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6714 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6715 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6716};
6717
6718union pplib_clock_info {
6719 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6720 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6721 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6722 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6723 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6724};
6725
6726union pplib_power_state {
6727 struct _ATOM_PPLIB_STATE v1;
6728 struct _ATOM_PPLIB_STATE_V2 v2;
6729};
6730
6731static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6732 struct radeon_ps *rps,
6733 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6734 u8 table_rev)
6735{
6736 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6737 rps->class = le16_to_cpu(non_clock_info->usClassification);
6738 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6739
6740 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6741 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6742 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6743 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6744 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6745 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6746 } else {
6747 rps->vclk = 0;
6748 rps->dclk = 0;
6749 }
6750
6751 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6752 rdev->pm.dpm.boot_ps = rps;
6753 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6754 rdev->pm.dpm.uvd_ps = rps;
6755}
6756
6757static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6758 struct radeon_ps *rps, int index,
6759 union pplib_clock_info *clock_info)
6760{
6761 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6762 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6763 struct si_power_info *si_pi = si_get_pi(rdev);
6764 struct ni_ps *ps = ni_get_ps(rps);
6765 u16 leakage_voltage;
6766 struct rv7xx_pl *pl = &ps->performance_levels[index];
6767 int ret;
6768
6769 ps->performance_level_count = index + 1;
6770
6771 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6772 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6773 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6774 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6775
6776 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6777 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6778 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6779 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6780 si_pi->sys_pcie_mask,
6781 si_pi->boot_pcie_gen,
6782 clock_info->si.ucPCIEGen);
6783
6784 /* patch up vddc if necessary */
6785 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6786 &leakage_voltage);
6787 if (ret == 0)
6788 pl->vddc = leakage_voltage;
6789
6790 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6791 pi->acpi_vddc = pl->vddc;
6792 eg_pi->acpi_vddci = pl->vddci;
6793 si_pi->acpi_pcie_gen = pl->pcie_gen;
6794 }
6795
6796 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6797 index == 0) {
6798 /* XXX disable for A0 tahiti */
6799 si_pi->ulv.supported = false;
6800 si_pi->ulv.pl = *pl;
6801 si_pi->ulv.one_pcie_lane_in_ulv = false;
6802 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6803 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6804 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6805 }
6806
6807 if (pi->min_vddc_in_table > pl->vddc)
6808 pi->min_vddc_in_table = pl->vddc;
6809
6810 if (pi->max_vddc_in_table < pl->vddc)
6811 pi->max_vddc_in_table = pl->vddc;
6812
6813 /* patch up boot state */
6814 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6815 u16 vddc, vddci, mvdd;
6816 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6817 pl->mclk = rdev->clock.default_mclk;
6818 pl->sclk = rdev->clock.default_sclk;
6819 pl->vddc = vddc;
6820 pl->vddci = vddci;
6821 si_pi->mvdd_bootup_value = mvdd;
6822 }
6823
6824 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6825 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6826 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6827 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6828 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6829 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6830 }
6831}
6832
6833static int si_parse_power_table(struct radeon_device *rdev)
6834{
6835 struct radeon_mode_info *mode_info = &rdev->mode_info;
6836 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6837 union pplib_power_state *power_state;
6838 int i, j, k, non_clock_array_index, clock_array_index;
6839 union pplib_clock_info *clock_info;
6840 struct _StateArray *state_array;
6841 struct _ClockInfoArray *clock_info_array;
6842 struct _NonClockInfoArray *non_clock_info_array;
6843 union power_info *power_info;
6844 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6845 u16 data_offset;
6846 u8 frev, crev;
6847 u8 *power_state_offset;
6848 struct ni_ps *ps;
6849
6850 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6851 &frev, &crev, &data_offset))
6852 return -EINVAL;
6853 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6854
6855 state_array = (struct _StateArray *)
6856 (mode_info->atom_context->bios + data_offset +
6857 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6858 clock_info_array = (struct _ClockInfoArray *)
6859 (mode_info->atom_context->bios + data_offset +
6860 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6861 non_clock_info_array = (struct _NonClockInfoArray *)
6862 (mode_info->atom_context->bios + data_offset +
6863 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6864
6865 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6866 state_array->ucNumEntries, GFP_KERNEL);
6867 if (!rdev->pm.dpm.ps)
6868 return -ENOMEM;
6869 power_state_offset = (u8 *)state_array->states;
6870 for (i = 0; i < state_array->ucNumEntries; i++) {
6871 u8 *idx;
6872 power_state = (union pplib_power_state *)power_state_offset;
6873 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6874 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6875 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6876 if (!rdev->pm.power_state[i].clock_info)
6877 return -EINVAL;
6878 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6879 if (ps == NULL) {
6880 kfree(rdev->pm.dpm.ps);
6881 return -ENOMEM;
6882 }
6883 rdev->pm.dpm.ps[i].ps_priv = ps;
6884 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6885 non_clock_info,
6886 non_clock_info_array->ucEntrySize);
6887 k = 0;
6888 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6889 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6890 clock_array_index = idx[j];
6891 if (clock_array_index >= clock_info_array->ucNumEntries)
6892 continue;
6893 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6894 break;
6895 clock_info = (union pplib_clock_info *)
6896 ((u8 *)&clock_info_array->clockInfo[0] +
6897 (clock_array_index * clock_info_array->ucEntrySize));
6898 si_parse_pplib_clock_info(rdev,
6899 &rdev->pm.dpm.ps[i], k,
6900 clock_info);
6901 k++;
6902 }
6903 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6904 }
6905 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6906
6907 /* fill in the vce power states */
6908 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6909 u32 sclk, mclk;
6910 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6911 clock_info = (union pplib_clock_info *)
6912 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6913 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6914 sclk |= clock_info->si.ucEngineClockHigh << 16;
6915 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6916 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6917 rdev->pm.dpm.vce_states[i].sclk = sclk;
6918 rdev->pm.dpm.vce_states[i].mclk = mclk;
6919 }
6920
6921 return 0;
6922}
6923
6924int si_dpm_init(struct radeon_device *rdev)
6925{
6926 struct rv7xx_power_info *pi;
6927 struct evergreen_power_info *eg_pi;
6928 struct ni_power_info *ni_pi;
6929 struct si_power_info *si_pi;
6930 struct atom_clock_dividers dividers;
6931 int ret;
6932 u32 mask;
6933
6934 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6935 if (si_pi == NULL)
6936 return -ENOMEM;
6937 rdev->pm.dpm.priv = si_pi;
6938 ni_pi = &si_pi->ni;
6939 eg_pi = &ni_pi->eg;
6940 pi = &eg_pi->rv7xx;
6941
6942 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6943 if (ret)
6944 si_pi->sys_pcie_mask = 0;
6945 else
6946 si_pi->sys_pcie_mask = mask;
6947 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6948 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6949
6950 si_set_max_cu_value(rdev);
6951
6952 rv770_get_max_vddc(rdev);
6953 si_get_leakage_vddc(rdev);
6954 si_patch_dependency_tables_based_on_leakage(rdev);
6955
6956 pi->acpi_vddc = 0;
6957 eg_pi->acpi_vddci = 0;
6958 pi->min_vddc_in_table = 0;
6959 pi->max_vddc_in_table = 0;
6960
6961 ret = r600_get_platform_caps(rdev);
6962 if (ret)
6963 return ret;
6964
6965 ret = r600_parse_extended_power_table(rdev);
6966 if (ret)
6967 return ret;
6968
6969 ret = si_parse_power_table(rdev);
6970 if (ret)
6971 return ret;
6972
6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6974 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6975 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6976 r600_free_extended_power_table(rdev);
6977 return -ENOMEM;
6978 }
6979 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6980 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6981 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6982 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6983 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6984 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6985 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6986 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6987 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6988
6989 if (rdev->pm.dpm.voltage_response_time == 0)
6990 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6991 if (rdev->pm.dpm.backbias_response_time == 0)
6992 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6993
6994 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6995 0, false, ÷rs);
6996 if (ret)
6997 pi->ref_div = dividers.ref_div + 1;
6998 else
6999 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7000
7001 eg_pi->smu_uvd_hs = false;
7002
7003 pi->mclk_strobe_mode_threshold = 40000;
7004 if (si_is_special_1gb_platform(rdev))
7005 pi->mclk_stutter_mode_threshold = 0;
7006 else
7007 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7008 pi->mclk_edc_enable_threshold = 40000;
7009 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7010
7011 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7012
7013 pi->voltage_control =
7014 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7015 VOLTAGE_OBJ_GPIO_LUT);
7016 if (!pi->voltage_control) {
7017 si_pi->voltage_control_svi2 =
7018 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7019 VOLTAGE_OBJ_SVID2);
7020 if (si_pi->voltage_control_svi2)
7021 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7022 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7023 }
7024
7025 pi->mvdd_control =
7026 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7027 VOLTAGE_OBJ_GPIO_LUT);
7028
7029 eg_pi->vddci_control =
7030 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7031 VOLTAGE_OBJ_GPIO_LUT);
7032 if (!eg_pi->vddci_control)
7033 si_pi->vddci_control_svi2 =
7034 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7035 VOLTAGE_OBJ_SVID2);
7036
7037 si_pi->vddc_phase_shed_control =
7038 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7039 VOLTAGE_OBJ_PHASE_LUT);
7040
7041 rv770_get_engine_memory_ss(rdev);
7042
7043 pi->asi = RV770_ASI_DFLT;
7044 pi->pasi = CYPRESS_HASI_DFLT;
7045 pi->vrc = SISLANDS_VRC_DFLT;
7046
7047 pi->gfx_clock_gating = true;
7048
7049 eg_pi->sclk_deep_sleep = true;
7050 si_pi->sclk_deep_sleep_above_low = false;
7051
7052 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7053 pi->thermal_protection = true;
7054 else
7055 pi->thermal_protection = false;
7056
7057 eg_pi->dynamic_ac_timing = true;
7058
7059 eg_pi->light_sleep = true;
7060#if defined(CONFIG_ACPI)
7061 eg_pi->pcie_performance_request =
7062 radeon_acpi_is_pcie_performance_request_supported(rdev);
7063#else
7064 eg_pi->pcie_performance_request = false;
7065#endif
7066
7067 si_pi->sram_end = SMC_RAM_END;
7068
7069 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7070 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7071 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7072 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7073 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7074 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7075 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7076
7077 si_initialize_powertune_defaults(rdev);
7078
7079 /* make sure dc limits are valid */
7080 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7081 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7082 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7083 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7084
7085 si_pi->fan_ctrl_is_in_default_mode = true;
7086
7087 return 0;
7088}
7089
7090void si_dpm_fini(struct radeon_device *rdev)
7091{
7092 int i;
7093
7094 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7095 kfree(rdev->pm.dpm.ps[i].ps_priv);
7096 }
7097 kfree(rdev->pm.dpm.ps);
7098 kfree(rdev->pm.dpm.priv);
7099 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7100 r600_free_extended_power_table(rdev);
7101}
7102
7103void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7104 struct seq_file *m)
7105{
7106 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7107 struct radeon_ps *rps = &eg_pi->current_rps;
7108 struct ni_ps *ps = ni_get_ps(rps);
7109 struct rv7xx_pl *pl;
7110 u32 current_index =
7111 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7112 CURRENT_STATE_INDEX_SHIFT;
7113
7114 if (current_index >= ps->performance_level_count) {
7115 seq_printf(m, "invalid dpm profile %d\n", current_index);
7116 } else {
7117 pl = &ps->performance_levels[current_index];
7118 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7119 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7120 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7121 }
7122}
7123
7124u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7125{
7126 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7127 struct radeon_ps *rps = &eg_pi->current_rps;
7128 struct ni_ps *ps = ni_get_ps(rps);
7129 struct rv7xx_pl *pl;
7130 u32 current_index =
7131 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7132 CURRENT_STATE_INDEX_SHIFT;
7133
7134 if (current_index >= ps->performance_level_count) {
7135 return 0;
7136 } else {
7137 pl = &ps->performance_levels[current_index];
7138 return pl->sclk;
7139 }
7140}
7141
7142u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7143{
7144 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7145 struct radeon_ps *rps = &eg_pi->current_rps;
7146 struct ni_ps *ps = ni_get_ps(rps);
7147 struct rv7xx_pl *pl;
7148 u32 current_index =
7149 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7150 CURRENT_STATE_INDEX_SHIFT;
7151
7152 if (current_index >= ps->performance_level_count) {
7153 return 0;
7154 } else {
7155 pl = &ps->performance_levels[current_index];
7156 return pl->mclk;
7157 }
7158}