1/*
  2 * HDMI PHY
  3 *
  4 * Copyright (C) 2013 Texas Instruments Incorporated
  5 *
  6 * This program is free software; you can redistribute it and/or modify it
  7 * under the terms of the GNU General Public License version 2 as published by
  8 * the Free Software Foundation.
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/err.h>
 13#include <linux/io.h>
 14#include <linux/platform_device.h>
 15#include <linux/slab.h>
 16#include <linux/seq_file.h>
 17
 18#include "omapdss.h"
 19#include "dss.h"
 20#include "hdmi.h"
 21
 22struct hdmi_phy_features {
 23	bool bist_ctrl;
 24	bool ldo_voltage;
 25	unsigned long max_phy;
 26};
 27
 28static const struct hdmi_phy_features *phy_feat;
 29
 30void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
 31{
 32#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
 33		hdmi_read_reg(phy->base, r))
 34
 35	DUMPPHY(HDMI_TXPHY_TX_CTRL);
 36	DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
 37	DUMPPHY(HDMI_TXPHY_POWER_CTRL);
 38	DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
 39	if (phy_feat->bist_ctrl)
 40		DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
 41}
 42
 43int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
 44{
 45	int i;
 46
 47	for (i = 0; i < 8; i += 2) {
 48		u8 lane, pol;
 49		int dx, dy;
 50
 51		dx = lanes[i];
 52		dy = lanes[i + 1];
 53
 54		if (dx < 0 || dx >= 8)
 55			return -EINVAL;
 56
 57		if (dy < 0 || dy >= 8)
 58			return -EINVAL;
 59
 60		if (dx & 1) {
 61			if (dy != dx - 1)
 62				return -EINVAL;
 63			pol = 1;
 64		} else {
 65			if (dy != dx + 1)
 66				return -EINVAL;
 67			pol = 0;
 68		}
 69
 70		lane = dx / 2;
 71
 72		phy->lane_function[lane] = i / 2;
 73		phy->lane_polarity[lane] = pol;
 74	}
 75
 76	return 0;
 77}
 78
 79static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
 80{
 81	static const u16 pad_cfg_list[] = {
 82		0x0123,
 83		0x0132,
 84		0x0312,
 85		0x0321,
 86		0x0231,
 87		0x0213,
 88		0x1023,
 89		0x1032,
 90		0x3012,
 91		0x3021,
 92		0x2031,
 93		0x2013,
 94		0x1203,
 95		0x1302,
 96		0x3102,
 97		0x3201,
 98		0x2301,
 99		0x2103,
100		0x1230,
101		0x1320,
102		0x3120,
103		0x3210,
104		0x2310,
105		0x2130,
106	};
107
108	u16 lane_cfg = 0;
109	int i;
110	unsigned lane_cfg_val;
111	u16 pol_val = 0;
112
113	for (i = 0; i < 4; ++i)
114		lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);
115
116	pol_val |= phy->lane_polarity[0] << 0;
117	pol_val |= phy->lane_polarity[1] << 3;
118	pol_val |= phy->lane_polarity[2] << 2;
119	pol_val |= phy->lane_polarity[3] << 1;
120
121	for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i)
122		if (pad_cfg_list[i] == lane_cfg)
123			break;
124
125	if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list)))
126		i = 0;
127
128	lane_cfg_val = i;
129
130	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);
131	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
132}
133
134int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
135	unsigned long lfbitclk)
136{
137	u8 freqout;
138
139	/*
140	 * Read address 0 in order to get the SCP reset done completed
141	 * Dummy access performed to make sure reset is done
142	 */
143	hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
144
145	/*
146	 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
147	 * HDMI_PHYPWRCMD_LDOON command.
148	*/
149	if (phy_feat->bist_ctrl)
150		REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
151
152	/*
153	 * If the hfbitclk != lfbitclk, it means the lfbitclk was configured
154	 * to be used for TMDS.
155	 */
156	if (hfbitclk != lfbitclk)
157		freqout = 0;
158	else if (hfbitclk / 10 < phy_feat->max_phy)
159		freqout = 1;
160	else
161		freqout = 2;
162
163	/*
164	 * Write to phy address 0 to configure the clock
165	 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
166	 */
167	REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
168
169	/* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
170	hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
171
172	/* Setup max LDO voltage */
173	if (phy_feat->ldo_voltage)
174		REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
175
176	hdmi_phy_configure_lanes(phy);
177
178	return 0;
179}
180
181static const struct hdmi_phy_features omap44xx_phy_feats = {
182	.bist_ctrl	=	false,
183	.ldo_voltage	=	true,
184	.max_phy	=	185675000,
185};
186
187static const struct hdmi_phy_features omap54xx_phy_feats = {
188	.bist_ctrl	=	true,
189	.ldo_voltage	=	false,
190	.max_phy	=	186000000,
191};
192
193static int hdmi_phy_init_features(struct platform_device *pdev)
194{
195	struct hdmi_phy_features *dst;
196	const struct hdmi_phy_features *src;
197
198	dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
199	if (!dst) {
200		dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
201		return -ENOMEM;
202	}
203
204	switch (omapdss_get_version()) {
205	case OMAPDSS_VER_OMAP4430_ES1:
206	case OMAPDSS_VER_OMAP4430_ES2:
207	case OMAPDSS_VER_OMAP4:
208		src = &omap44xx_phy_feats;
209		break;
210
211	case OMAPDSS_VER_OMAP5:
212	case OMAPDSS_VER_DRA7xx:
213		src = &omap54xx_phy_feats;
214		break;
215
216	default:
217		return -ENODEV;
218	}
219
220	memcpy(dst, src, sizeof(*dst));
221	phy_feat = dst;
222
223	return 0;
224}
225
226int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
227{
228	int r;
229	struct resource *res;
230
231	r = hdmi_phy_init_features(pdev);
232	if (r)
233		return r;
234
235	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
236	if (!res) {
237		DSSERR("can't get PHY mem resource\n");
238		return -EINVAL;
239	}
240
241	phy->base = devm_ioremap_resource(&pdev->dev, res);
242	if (IS_ERR(phy->base)) {
243		DSSERR("can't ioremap TX PHY\n");
244		return PTR_ERR(phy->base);
245	}
246
247	return 0;
248}